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FMC ADC 100M 14b 4cha - Gateware
Commit 555b7a24 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl/spec/syn/spec_top_fmc_adc_100Ms.par
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Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Fri Aug 03 16:40:29 2012
pcbe15575:: Fri Nov 30 14:48:11 2012
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
......@@ -22,16 +22,16 @@ Device speed data version: "PRODUCTION 1.20 2011-10-03".
Device Utilization Summary:
Slice Logic Utilization:
Number of Slice Registers: 6,824 out of 54,576 12%
Number used as Flip Flops: 6,824
Number of Slice Registers: 6,576 out of 54,576 12%
Number used as Flip Flops: 6,576
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,460 out of 27,288 20%
Number used as logic: 4,929 out of 27,288 18%
Number using O6 output only: 3,109
Number using O5 output only: 279
Number using O5 and O6: 1,541
Number of Slice LUTs: 5,403 out of 27,288 19%
Number used as logic: 5,150 out of 27,288 18%
Number using O6 output only: 3,289
Number using O5 output only: 360
Number using O5 and O6: 1,501
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -40,18 +40,18 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 529
Number with same-slice register load: 518
Number with same-slice carry load: 11
Number used exclusively as route-thrus: 251
Number with same-slice register load: 230
Number with same-slice carry load: 21
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,365 out of 6,822 34%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,523
Number with an unused Flip Flop: 1,673 out of 7,523 22%
Number with an unused LUT: 2,063 out of 7,523 27%
Number of fully used LUT-FF pairs: 3,787 out of 7,523 50%
Number of occupied Slices: 2,516 out of 6,822 36%
Nummber of MUXCYs used: 1,384 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,794
Number with an unused Flip Flop: 1,901 out of 7,794 24%
Number with an unused LUT: 2,391 out of 7,794 30%
Number of fully used LUT-FF pairs: 3,502 out of 7,794 44%
Number of slice register sites lost
to control set restrictions: 0 out of 54,576 0%
......@@ -66,7 +66,7 @@ IO Utilization:
Number of LOCed IOBs: 188 out of 188 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 67 out of 116 57%
Number of RAMB16BWERs: 68 out of 116 58%
Number of RAMB8BWERs: 2 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
......@@ -122,29 +122,29 @@ WARNING:Par:288 - The signal P_WR_REQ<1>_IBUF has no load. PAR will not attempt
Starting Router
Phase 1 : 43474 unrouted; REAL time: 16 secs
Phase 1 : 44589 unrouted; REAL time: 16 secs
Phase 2 : 33345 unrouted; REAL time: 21 secs
Phase 2 : 34630 unrouted; REAL time: 20 secs
Phase 3 : 13108 unrouted; REAL time: 47 secs
Phase 3 : 14274 unrouted; REAL time: 48 secs
Phase 4 : 13126 unrouted; (Setup:0, Hold:4589, Component Switching Limit:0) REAL time: 51 secs
Phase 4 : 14347 unrouted; (Setup:51, Hold:112, Component Switching Limit:0) REAL time: 54 secs
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:4455, Component Switching Limit:0) REAL time: 1 mins 28 secs
Phase 5 : 0 unrouted; (Setup:131, Hold:112, Component Switching Limit:0) REAL time: 1 mins 40 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:4455, Component Switching Limit:0) REAL time: 1 mins 28 secs
Phase 6 : 0 unrouted; (Setup:131, Hold:112, Component Switching Limit:0) REAL time: 1 mins 41 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:4455, Component Switching Limit:0) REAL time: 1 mins 28 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:112, Component Switching Limit:0) REAL time: 2 mins 6 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:4455, Component Switching Limit:0) REAL time: 1 mins 28 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:112, Component Switching Limit:0) REAL time: 2 mins 6 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 29 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 7 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 32 secs
Total REAL time to Router completion: 1 mins 32 secs
Total CPU time to Router completion: 1 mins 34 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 2 mins 10 secs
Total REAL time to Router completion: 2 mins 10 secs
Total CPU time to Router completion: 2 mins 18 secs
Partition Implementation Status
-------------------------------
......@@ -162,19 +162,19 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X2Y2| No | 1276 | 0.067 | 1.278 |
|cmp_fmc_adc_100Ms_co | | | | | |
| re/fs_clk | BUFGMUX_X2Y4| No | 162 | 0.248 | 1.473 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/sys_ | | | | | |
| clk | BUFGMUX_X2Y12| No | 641 | 0.187 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_fmc_adc_100Ms_co | | | | | |
| re/fs_clk | BUFGMUX_X2Y4| No | 155 | 0.237 | 1.473 |
| clk | BUFGMUX_X2Y12| No | 652 | 0.187 | 1.398 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_ddr_ctrl/cmp_ddr | | | | | |
|3_ctrl_wrapper/gen_s | | | | | |
|pec_bank3_64b_32b.cm | | | | | |
|p_ddr3_ctrl/c3_mcb_d | | | | | |
| rp_clk | BUFGMUX_X3Y13| No | 78 | 0.048 | 1.285 |
| rp_clk | BUFGMUX_X3Y13| No | 82 | 0.072 | 1.285 |
+---------------------+--------------+------+------+------------+-------------+
| sys_clk_125 | BUFGMUX_X2Y2| No | 1352 | 0.065 | 1.276 |
+---------------------+--------------+------+------+------------+-------------+
|cmp_gn4124_core/io_c | | | | | |
| lk | Local| | 41 | 0.064 | 1.562 |
......@@ -290,21 +290,21 @@ Asterisk (*) preceding a constraint indicates it was not met.
k_2x_180" TS_SYS_CLK5 / 2 PHASE 0 | | | | |
.75 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.034ns| 7.966ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.326ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.047ns| 4.953ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.082ns| | 0| 0
TS_cmp_gn4124_core_cmp_clk_in_rx_pllout_x | SETUP | 0.035ns| 4.965ns| 0| 0
1_0 = PERIOD TIMEGRP "cmp_gn4124_ | HOLD | 0.125ns| | 0| 0
core_cmp_clk_in_rx_pllout_x1_0" T | | | | |
S_cmp_gn4124_core_cmp_clk_in_buf_P_clk_0 | | | | |
PHASE 1.25 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_sys_clk_125_buf = PERIOD TIMEGRP "sys_ | SETUP | 0.039ns| 7.961ns| 0| 0
clk_125_buf" TS_clk20_vcxo_i / 6.25 | HOLD | 0.263ns| | 0| 0
HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_adc_dco_n_i = PERIOD TIMEGRP "adc_dco_ | MINLOWPULSE | 0.364ns| 1.636ns| 0| 0
n_i" 2 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_fmc_adc_100Ms_core_fs_clk_buf = PE | SETUP | 0.306ns| 7.694ns| 0| 0
RIOD TIMEGRP "cmp_fmc_adc_100Ms_c | HOLD | 0.399ns| | 0| 0
TS_cmp_fmc_adc_100Ms_core_fs_clk_buf = PE | SETUP | 0.329ns| 7.671ns| 0| 0
RIOD TIMEGRP "cmp_fmc_adc_100Ms_c | HOLD | 0.381ns| | 0| 0
ore_fs_clk_buf" TS_adc_dco_n_i / 0.25 HIG | | | | |
H 50% | | | | |
----------------------------------------------------------------------------------------------------------
......@@ -334,20 +334,20 @@ Asterisk (*) preceding a constraint indicates it was not met.
TS_clk20_vcxo_i = PERIOD TIMEGRP "clk20_v | MINLOWPULSE | 30.000ns| 20.000ns| 0| 0
cxo_i_grp" 50 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 3.924ns| 8.075ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.240ns| | 0| 0
TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | SETUP | 5.651ns| 6.348ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | HOLD | 0.393ns| | 0| 0
nfrastructure_inst_mcb_drp_clk_bufg_in_0 | | | | |
= PERIOD TIMEGRP "cmp_ddr | | | | |
_ctrl_cmp_ddr3_ctrl_wrapper_gen_spec_bank | | | | |
3_64b_32b_cmp_ddr3_ctrl_memc3_infrastruct | | | | |
ure_inst_mcb_drp_clk_bufg_in_0" T | | | | |
S_ddr_clk_buf / 0.25 HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clkn = PERIOD TIMEGRP "p2l_clkn_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_p2l_clkp = PERIOD TIMEGRP "p2l_clkp_gr | MINPERIOD | 4.075ns| 0.925ns| 0| 0
p" 5 ns HIGH 50% | | | | |
----------------------------------------------------------------------------------------------------------
TS_cmp_ddr_ctrl_cmp_ddr3_ctrl_wrapper_gen | MINPERIOD | 10.270ns| 1.730ns| 0| 0
_spec_bank3_64b_32b_cmp_ddr3_ctrl_memc3_i | | | | |
......@@ -402,12 +402,12 @@ Derived Constraints for TS_p2l_clkn
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.953ns| 0| 0| 0| 29020|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.953ns| 0| 0| 0| 29020|
|TS_p2l_clkn | 5.000ns| 0.925ns| 4.965ns| 0| 0| 0| 30220|
| TS_cmp_gn4124_core_cmp_clk_in_| 5.000ns| 2.800ns| 4.965ns| 0| 0| 0| 30220|
| buf_P_clk_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 2.500ns| N/A| N/A| 0| 0| 0| 0|
| _rx_pllout_xs_int_0 | | | | | | | |
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.953ns| N/A| 0| 0| 29020| 0|
| TS_cmp_gn4124_core_cmp_clk_in| 5.000ns| 4.965ns| N/A| 0| 0| 30220| 0|
| _rx_pllout_x1_0 | | | | | | | |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
......@@ -417,10 +417,10 @@ Derived Constraints for TS_clk20_vcxo_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 399507|
| TS_sys_clk_125_buf | 8.000ns| 7.966ns| N/A| 0| 0| 389107| 0|
|TS_clk20_vcxo_i | 50.000ns| 20.000ns| 49.967ns| 0| 0| 0| 403095|
| TS_sys_clk_125_buf | 8.000ns| 7.961ns| N/A| 0| 0| 392695| 0|
| TS_ddr_clk_buf | 3.000ns| 2.572ns| 2.998ns| 0| 0| 0| 10400|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 8.075ns| N/A| 0| 0| 10400| 0|
| TS_cmp_ddr_ctrl_cmp_ddr3_ctrl| 12.000ns| 6.348ns| N/A| 0| 0| 10400| 0|
| _wrapper_gen_spec_bank3_64b_3| | | | | | | |
| 2b_cmp_ddr3_ctrl_memc3_infras| | | | | | | |
| tructure_inst_mcb_drp_clk_buf| | | | | | | |
......@@ -462,8 +462,8 @@ Derived Constraints for TS_adc_dco_n_i
| Constraint | Requirement |-------------+-------------|-------------+-------------|-------------+-------------|
| | | Direct | Derivative | Direct | Derivative | Direct | Derivative |
+-------------------------------+-------------+-------------+-------------+-------------+-------------+-------------+-------------+
|TS_adc_dco_n_i | 2.000ns| 1.636ns| 1.923ns| 0| 0| 0| 18373|
| TS_cmp_fmc_adc_100Ms_core_fs_c| 8.000ns| 7.694ns| N/A| 0| 0| 18373| 0|
|TS_adc_dco_n_i | 2.000ns| 1.636ns| 1.918ns| 0| 0| 0| 18373|
| TS_cmp_fmc_adc_100Ms_core_fs_c| 8.000ns| 7.671ns| N/A| 0| 0| 18373| 0|
| lk_buf | | | | | | | |
| TS_cmp_fmc_adc_100Ms_core_serd| 1.000ns| N/A| N/A| 0| 0| 0| 0|
| es_clk | | | | | | | |
......@@ -483,10 +483,10 @@ All signals are completely routed.
WARNING:Par:283 - There are 7 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 35 secs
Total CPU time to PAR completion: 1 mins 37 secs
Total REAL time to PAR completion: 2 mins 13 secs
Total CPU time to PAR completion: 2 mins 21 secs
Peak Memory Usage: 340 MB
Peak Memory Usage: 351 MB
Placer: Placement generated during map.
Routing: Completed - No errors found.
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
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hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
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hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
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......@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Aug 3 16:35:35 2012
Mapped Date : Fri Nov 30 14:43:16 2012
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,824 out of 54,576 12%
Number used as Flip Flops: 6,824
Number of Slice Registers: 6,576 out of 54,576 12%
Number used as Flip Flops: 6,576
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,460 out of 27,288 20%
Number used as logic: 4,929 out of 27,288 18%
Number using O6 output only: 3,109
Number using O5 output only: 279
Number using O5 and O6: 1,541
Number of Slice LUTs: 5,403 out of 27,288 19%
Number used as logic: 5,150 out of 27,288 18%
Number using O6 output only: 3,289
Number using O5 output only: 360
Number using O5 and O6: 1,501
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,21 +36,21 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 529
Number with same-slice register load: 518
Number with same-slice carry load: 11
Number used exclusively as route-thrus: 251
Number with same-slice register load: 230
Number with same-slice carry load: 21
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,365 out of 6,822 34%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,523
Number with an unused Flip Flop: 1,673 out of 7,523 22%
Number with an unused LUT: 2,063 out of 7,523 27%
Number of fully used LUT-FF pairs: 3,787 out of 7,523 50%
Number of unique control sets: 261
Number of occupied Slices: 2,516 out of 6,822 36%
Nummber of MUXCYs used: 1,384 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,794
Number with an unused Flip Flop: 1,901 out of 7,794 24%
Number with an unused LUT: 2,391 out of 7,794 30%
Number of fully used LUT-FF pairs: 3,502 out of 7,794 44%
Number of unique control sets: 235
Number of slice register sites lost
to control set restrictions: 686 out of 54,576 1%
to control set restrictions: 542 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -63,7 +63,7 @@ IO Utilization:
Number of LOCed IOBs: 188 out of 188 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 67 out of 116 57%
Number of RAMB16BWERs: 68 out of 116 58%
Number of RAMB8BWERs: 2 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.76
Average Fanout of Non-Clock Nets: 3.78
Peak Memory Usage: 413 MB
Total REAL time to MAP completion: 4 mins 48 secs
Total CPU time to MAP completion (all processors): 4 mins 50 secs
Peak Memory Usage: 415 MB
Total REAL time to MAP completion: 4 mins 49 secs
Total CPU time to MAP completion (all processors): 4 mins 53 secs
Table of Contents
-----------------
......@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 9 more times for the following
(max. 5 shown):
N648,
N650,
N686,
N688,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......
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