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FMC ADC 100M 14b 4cha - Gateware
Commit 555b7a24 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl/spec/syn/spec_top_fmc_adc_100Ms.par
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hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
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hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
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hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
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......@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Fri Aug 3 16:35:35 2012
Mapped Date : Fri Nov 30 14:43:16 2012
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,824 out of 54,576 12%
Number used as Flip Flops: 6,824
Number of Slice Registers: 6,576 out of 54,576 12%
Number used as Flip Flops: 6,576
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,460 out of 27,288 20%
Number used as logic: 4,929 out of 27,288 18%
Number using O6 output only: 3,109
Number using O5 output only: 279
Number using O5 and O6: 1,541
Number of Slice LUTs: 5,403 out of 27,288 19%
Number used as logic: 5,150 out of 27,288 18%
Number using O6 output only: 3,289
Number using O5 output only: 360
Number using O5 and O6: 1,501
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,21 +36,21 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 529
Number with same-slice register load: 518
Number with same-slice carry load: 11
Number used exclusively as route-thrus: 251
Number with same-slice register load: 230
Number with same-slice carry load: 21
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,365 out of 6,822 34%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,523
Number with an unused Flip Flop: 1,673 out of 7,523 22%
Number with an unused LUT: 2,063 out of 7,523 27%
Number of fully used LUT-FF pairs: 3,787 out of 7,523 50%
Number of unique control sets: 261
Number of occupied Slices: 2,516 out of 6,822 36%
Nummber of MUXCYs used: 1,384 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,794
Number with an unused Flip Flop: 1,901 out of 7,794 24%
Number with an unused LUT: 2,391 out of 7,794 30%
Number of fully used LUT-FF pairs: 3,502 out of 7,794 44%
Number of unique control sets: 235
Number of slice register sites lost
to control set restrictions: 686 out of 54,576 1%
to control set restrictions: 542 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -63,7 +63,7 @@ IO Utilization:
Number of LOCed IOBs: 188 out of 188 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 67 out of 116 57%
Number of RAMB16BWERs: 68 out of 116 58%
Number of RAMB8BWERs: 2 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.76
Average Fanout of Non-Clock Nets: 3.78
Peak Memory Usage: 413 MB
Total REAL time to MAP completion: 4 mins 48 secs
Total CPU time to MAP completion (all processors): 4 mins 50 secs
Peak Memory Usage: 415 MB
Total REAL time to MAP completion: 4 mins 49 secs
Total CPU time to MAP completion (all processors): 4 mins 53 secs
Table of Contents
-----------------
......@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 9 more times for the following
(max. 5 shown):
N648,
N650,
N686,
N688,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......
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