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FMC ADC 100M 14b 4cha - Gateware
Commit 5e475118 authored by Matthieu Cattin's avatar Matthieu Cattin
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syn: Firmware release 1.0, synthesis reports and sdb meta-info.

parent 2f92c67d
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hdl/spec/rtl/sdb_meta_pkg.vhd
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......@@ -21,14 +21,14 @@ package sdb_meta_pkg is
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-31
syn_commit_id => "150b83db8fa9e0ff9050166b7695ee9a",
-- git log -1 --format="%H" | cut -c1-32
syn_commit_id => "baa41197a02acc5cbdfbc5c893849b40",
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130307",
syn_date => x"20130312",
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
......@@ -38,7 +38,7 @@ package sdb_meta_pkg is
vendor_id => x"000000000000CE42", -- CERN
device_id => x"47c786a2", -- echo "spec_fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130307", -- yyyymmdd
date => x"20130312", -- yyyymmdd
name => "spec_fmcadc100m14b "));
......
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
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hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
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hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
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hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
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......@@ -11,23 +11,23 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Mar 7 18:46:02 2013
Mapped Date : Tue Mar 12 08:37:23 2013
Design Summary
--------------
Number of errors: 0
Number of warnings: 8
Slice Logic Utilization:
Number of Slice Registers: 6,805 out of 54,576 12%
Number used as Flip Flops: 6,805
Number of Slice Registers: 6,840 out of 54,576 12%
Number used as Flip Flops: 6,840
Number used as Latches: 0
Number used as Latch-thrus: 0
Number used as AND/OR logics: 0
Number of Slice LUTs: 5,450 out of 27,288 19%
Number used as logic: 5,169 out of 27,288 18%
Number using O6 output only: 3,262
Number using O5 output only: 281
Number using O5 and O6: 1,626
Number of Slice LUTs: 5,481 out of 27,288 20%
Number used as logic: 5,116 out of 27,288 18%
Number using O6 output only: 3,207
Number using O5 output only: 278
Number using O5 and O6: 1,631
Number used as ROM: 0
Number used as Memory: 2 out of 6,408 1%
Number used as Dual Port RAM: 0
......@@ -36,21 +36,21 @@ Slice Logic Utilization:
Number using O6 output only: 2
Number using O5 output only: 0
Number using O5 and O6: 0
Number used exclusively as route-thrus: 279
Number with same-slice register load: 268
Number with same-slice carry load: 11
Number used exclusively as route-thrus: 363
Number with same-slice register load: 351
Number with same-slice carry load: 12
Number with other load: 0
Slice Logic Distribution:
Number of occupied Slices: 2,618 out of 6,822 38%
Nummber of MUXCYs used: 1,424 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,968
Number with an unused Flip Flop: 1,934 out of 7,968 24%
Number with an unused LUT: 2,518 out of 7,968 31%
Number of fully used LUT-FF pairs: 3,516 out of 7,968 44%
Number of unique control sets: 260
Number of occupied Slices: 2,465 out of 6,822 36%
Nummber of MUXCYs used: 1,456 out of 13,644 10%
Number of LUT Flip Flop pairs used: 7,735
Number with an unused Flip Flop: 1,738 out of 7,735 22%
Number with an unused LUT: 2,254 out of 7,735 29%
Number of fully used LUT-FF pairs: 3,743 out of 7,735 48%
Number of unique control sets: 261
Number of slice register sites lost
to control set restrictions: 673 out of 54,576 1%
to control set restrictions: 678 out of 54,576 1%
A LUT Flip Flop pair for this architecture represents one LUT paired with
one Flip Flop within a slice. A control set is a unique combination of
......@@ -63,7 +63,7 @@ IO Utilization:
Number of LOCed IOBs: 188 out of 188 100%
Specific Feature Utilization:
Number of RAMB16BWERs: 68 out of 116 58%
Number of RAMB16BWERs: 26 out of 116 22%
Number of RAMB8BWERs: 2 out of 232 1%
Number of BUFIO2/BUFIO2_2CLKs: 3 out of 32 9%
Number used as BUFIO2s: 3
......@@ -100,11 +100,11 @@ Specific Feature Utilization:
Number of STARTUPs: 0 out of 1 0%
Number of SUSPEND_SYNCs: 0 out of 1 0%
Average Fanout of Non-Clock Nets: 3.79
Average Fanout of Non-Clock Nets: 3.78
Peak Memory Usage: 417 MB
Total REAL time to MAP completion: 4 mins 50 secs
Total CPU time to MAP completion (all processors): 4 mins 52 secs
Peak Memory Usage: 409 MB
Total REAL time to MAP completion: 4 mins 37 secs
Total CPU time to MAP completion (all processors): 4 mins 37 secs
Table of Contents
-----------------
......@@ -164,8 +164,8 @@ INFO:LIT:243 - Logical network
_infrastructure_inst/rst0_sync_r<24> has no load.
INFO:LIT:395 - The above info message is repeated 8 more times for the following
(max. 5 shown):
N754,
N756,
N786,
N788,
aux_buttons_i<1>_IBUF,
aux_buttons_i<0>_IBUF,
P_WR_REQ<1>_IBUF
......@@ -186,8 +186,8 @@ INFO:Pack:1650 - Map created a placed design.
Section 4 - Removed Logic Summary
---------------------------------
101 block(s) removed
8 block(s) optimized away
93 block(s) removed
2 block(s) optimized away
74 signal(s) removed
Section 5 - Removed Logic
......@@ -599,25 +599,11 @@ The trimmed logic reported below is either:
The signal "DDR3_ZIO" is unused and has been removed.
Unused block "DDR3_ZIO_OBUFT" (TRI) removed.
Unused block "DDR3_ZIO" (PAD) removed.
Unused block "cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/GND" (ZERO) removed.
Unused block "cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/VCC" (ONE) removed.
Unused block "cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/GND" (ZERO) removed.
Unused block "cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/VCC" (ONE) removed.
Unused block "cmp_fmc_adc_100Ms_core/cmp_multishot_dpram1/GND" (ZERO) removed.
Unused block "cmp_fmc_adc_100Ms_core/cmp_multishot_dpram1/VCC" (ONE) removed.
Unused block "cmp_fmc_adc_100Ms_core/cmp_wb_ddr_fifo/GND" (ZERO) removed.
Unused block "cmp_fmc_adc_100Ms_core/cmp_wb_ddr_fifo/VCC" (ONE) removed.
Optimized Block(s):
TYPE BLOCK
GND XST_GND
VCC XST_VCC
GND cmp_fmc_adc_100Ms_core/cmp_adc_sync_fifo/BU2/XST_GND
GND cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/BU2/XST_GND
VCC cmp_fmc_adc_100Ms_core/cmp_multishot_dpram0/BU2/XST_VCC
GND cmp_fmc_adc_100Ms_core/cmp_multishot_dpram1/BU2/XST_GND
VCC cmp_fmc_adc_100Ms_core/cmp_multishot_dpram1/BU2/XST_VCC
GND cmp_fmc_adc_100Ms_core/cmp_wb_ddr_fifo/BU2/XST_GND
To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.
......@@ -766,8 +752,8 @@ Section 6 - IOB Properties
| ext_trigger_n_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| ext_trigger_p_i | IOB | INPUT | LVDS_25 | FALSE | | | | | |
| gpio_dac_clr_n_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| gpio_led_power_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| gpio_led_trigger_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| gpio_led_acq_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| gpio_led_trig_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| gpio_si570_oe_o | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| gpio_ssr_ch1_o<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| gpio_ssr_ch1_o<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
......
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