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FMC ADC 100M 14b 4cha - Gateware
Commit 67d2154d authored by mcattin's avatar mcattin
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Add a few missing files to the repo. 

Because a migration to git is foreseen.


git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@132 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent feba6ffa
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hdl/spec/ip_cores/monostable/monostable_tb.vhd 0 → 100755
View file @ 67d2154d
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:59:19 10/22/2009
-- Design Name:
-- Module Name: C:/mcattin/fpga_design/cvorb_cvorg/sources/monostable_tb.vhd
-- Project Name: cvorb_v3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: monostable
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity monostable_tb is
end monostable_tb;
architecture behavior of monostable_tb is
-- Component Declaration for the Unit Under Test (UUT)
component monostable
generic(
g_INPUT_POLARITY : std_logic := '1'; --! pulse_i polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_POLARITY : std_logic := '1'; --! pulse_o polarity
--! ('0'=negative, 1=positive)
g_OUTPUT_RETRIG : boolean := FALSE; --!
g_OUTPUT_LENGTH : natural := 1 --! pulse_o lenght (in clk_i ticks)
);
port(
rst_n_i : in std_logic;
clk_i : in std_logic;
trigger_i : in std_logic;
pulse_o : out std_logic
);
end component;
--Inputs
signal rst_n_i : std_logic := '0';
signal clk_i : std_logic := '0';
signal trigger_i : std_logic := '0';
--Outputs
signal pulse_o : std_logic;
-- Clock period definitions
constant clk_i_period : time := 25 us;
begin
-- Instantiate the Unit Under Test (UUT)
uut : monostable
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '0',
g_OUTPUT_RETRIG => FALSE,
g_OUTPUT_LENGTH => 10
)
port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
trigger_i => trigger_i,
pulse_o => pulse_o
);
-- Clock process definitions
clk_i_process : process
begin
clk_i <= '0';
wait for 12.5 ns;
clk_i <= '1';
wait for 12.5 ns;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state for 1 us.
rst_n_i <= '0';
wait for 1 us;
rst_n_i <= '1';
wait for 100 ns;
wait until rising_edge(clk_i);
trigger_i <= '1';
wait until rising_edge(clk_i);
--wait for 500 ns;
trigger_i <= '0';
wait for 200 ns;
wait until rising_edge(clk_i);
trigger_i <= '1';
wait until rising_edge(clk_i);
trigger_i <= '0';
wait;
end process;
end;
hdl/spec/memory_map.txt 0 → 100755
View file @ 67d2154d
================================================================================
Memory mapping of FmcAdc100m14b4cha firmware for SPEC
-----------------------------------------------------
Matthieu Cattin
21.11.2011
================================================================================
CSR wishbone modules base addresses (BAR0):
0x00000 : DMA configuration
0x10000 : Carrier SPI master (DACs for VCXOs)
0x20000 : Carrier 1-wire master (thermometer + unique ID)
0x30000 : Carrier CSR (control and status registers)
0x40000 : UTC core (counters, time-tag)
0x50000 : Interrupt controller
0x60000 : Mezzanine system managment I2C master (Mezzanine EEPROM)
0x70000 : Mezzanine SPI master (offset DACs, ADC control)
0x80000 : Mezzanine I2C master (Si570)
0x90000 : Mezzanine ADC core (control and status registers)
0xA0000 : Mezzanine 1-wire master (thermometer + unique ID)
--------------------------------------------------------------------------------
DMA configuration:
http://svn.ohwr.org/gn4124-core/trunk/documentation/specifications/func_spec_GN4124_core.pdf
Note:
DMAATTRIBR bit 0 is set to '1' if that is NOT the last item in the list!
--------------------------------------------------------------------------------
Carrier SPI master:
http://opencores.org/websvn,filedetails?repname=spi&path=%2Fspi%2Ftrunk%2Fdoc%2Fspi.pdf
--------------------------------------------------------------------------------
Carrier 1-wire master:
http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf
--------------------------------------------------------------------------------
Carrier CSR:
http://www.ohwr.org/projects/fmc-adc-100m14b4cha/repository/changes/trunk/hdl/spec/wb_gen/carrier_csr.htm
--------------------------------------------------------------------------------
UTC core:
http://www.ohwr.org/projects/fmc-adc-100m14b4cha/repository/changes/trunk/hdl/spec/wb_gen/utc_core_regs.htm
--------------------------------------------------------------------------------
Interrupt controller:
http://www.ohwr.org/projects/fmc-adc-100m14b4cha/repository/changes/trunk/hdl/spec/wb_gen/irq_controller_regs.htm
--------------------------------------------------------------------------------
Mezzanine system managment I2C master:
http://opencores.org/websvn,filedetails?repname=i2c&path=%2Fi2c%2Ftrunk%2Fdoc%2Fi2c_specs.pdf
Note:
Registers are 8-bit wide, but accessed as 32-bit registers (only the 8 LSB are used).
Therefore addresses from the documentation has to be multiplied by 4.
--------------------------------------------------------------------------------
Mezzanine SPI master:
http://opencores.org/websvn,filedetails?repname=spi&path=%2Fspi%2Ftrunk%2Fdoc%2Fspi.pdf
--------------------------------------------------------------------------------
Mezzanine I2C master:
http://opencores.org/websvn,filedetails?repname=i2c&path=%2Fi2c%2Ftrunk%2Fdoc%2Fi2c_specs.pdf
Note:
Registers are 8-bit wide, but accessed as 32-bit registers (only the 8 LSB are used).
Therefore addresses from the documentation has to be multiplied by 4.
--------------------------------------------------------------------------------
Mezzanine ADC core:
http://www.ohwr.org/projects/fmc-adc-100m14b4cha/repository/changes/trunk/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
--------------------------------------------------------------------------------
Mezzanine 1-wire master:
http://opencores.org/websvn,filedetails?repname=sockit_owm&path=%2Fsockit_owm%2Ftrunk%2Fdoc%2Fsockit_owr.pdf
hdl/spec/sim/wave_end_acq_irq.do 0 → 100644
View file @ 67d2154d
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /tb_spec/RSTOUT18n
add wave -noupdate -radix hexadecimal -childformat {{/tb_spec/ADC_DATA(0) -radix hexadecimal} {/tb_spec/ADC_DATA(1) -radix hexadecimal} {/tb_spec/ADC_DATA(2) -radix hexadecimal} {/tb_spec/ADC_DATA(3) -radix hexadecimal}} -expand -subitemconfig {/tb_spec/ADC_DATA(0) {-height 16 -radix hexadecimal} /tb_spec/ADC_DATA(1) {-height 16 -radix hexadecimal} /tb_spec/ADC_DATA(2) {-height 16 -radix hexadecimal} /tb_spec/ADC_DATA(3) {-height 16 -radix hexadecimal}} /tb_spec/ADC_DATA
add wave -noupdate -divider {adc core}
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_clk_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_adr_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_dat_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_sel_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stb_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_we_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_cyc_o
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_ack_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_i
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_fsm_state
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fsm_cmd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/fsm_cmd_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_start
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_stop
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_end
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_pre_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/acq_in_post_trig
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/samples_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_value
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_done
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/shots_decr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/single_shot
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_addr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_din
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dout
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_empty
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_full
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_rd
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_valid
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_dreq
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_fifo_wr_en
add wave -noupdate -radix unsigned /tb_spec/U1/cmp_fmc_adc_100Ms_core/ram_addr_cnt
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/wb_ddr_stall_t
add wave -noupdate -radix hexadecimal /tb_spec/U1/cmp_fmc_adc_100Ms_core/trig_led
add wave -noupdate -divider {ddr core}
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_full
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_en
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_empty
add wave -noupdate /tb_spec/U1/cmp_ddr_ctrl/p0_wr_count
add wave -noupdate -divider irq
add wave -noupdate /tb_spec/U1/acq_end_p
add wave -noupdate /tb_spec/U1/acq_end_irq_p
add wave -noupdate /tb_spec/U1/acq_end
add wave -noupdate /tb_spec/U1/ddr_wr_fifo_empty_p
add wave -noupdate /tb_spec/U1/ddr_wr_fifo_empty_d
add wave -noupdate /tb_spec/U1/ddr_wr_fifo_empty
add wave -noupdate /tb_spec/U1/irq_sources(3)
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {25017769 ps} 0} {{Cursor 2} {24288843 ps} 0}
configure wave -namecolwidth 496
configure wave -valuecolwidth 172
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {31500 ns}
hdl/spec/syn/Makefile 0 → 100644
View file @ 67d2154d
########################################
# This file was generated by hdlmake #
# http://ohwr.org/projects/hdl-make/ #
########################################
PROJECT := spec_fmc_adc_100Ms.xise
ISE_CRAP := *.b spec_top_fmc_adc_100Ms_summary.html *.tcl spec_top_fmc_adc_100Ms.bld spec_top_fmc_adc_100Ms.cmd_log *.drc spec_top_fmc_adc_100Ms.lso *.ncd spec_top_fmc_adc_100Ms.ngc spec_top_fmc_adc_100Ms.ngd spec_top_fmc_adc_100Ms.ngr spec_top_fmc_adc_100Ms.pad spec_top_fmc_adc_100Ms.par spec_top_fmc_adc_100Ms.pcf spec_top_fmc_adc_100Ms.prj spec_top_fmc_adc_100Ms.ptwx spec_top_fmc_adc_100Ms.stx spec_top_fmc_adc_100Ms.syr spec_top_fmc_adc_100Ms.twr spec_top_fmc_adc_100Ms.twx spec_top_fmc_adc_100Ms.gise spec_top_fmc_adc_100Ms.unroutes spec_top_fmc_adc_100Ms.ut spec_top_fmc_adc_100Ms.xpi spec_top_fmc_adc_100Ms.xst spec_top_fmc_adc_100Ms_bitgen.xwbt spec_top_fmc_adc_100Ms_envsettings.html spec_top_fmc_adc_100Ms_guide.ncd spec_top_fmc_adc_100Ms_map.map spec_top_fmc_adc_100Ms_map.mrp spec_top_fmc_adc_100Ms_map.ncd spec_top_fmc_adc_100Ms_map.ngm spec_top_fmc_adc_100Ms_map.xrpt spec_top_fmc_adc_100Ms_ngdbuild.xrpt spec_top_fmc_adc_100Ms_pad.csv spec_top_fmc_adc_100Ms_pad.txt spec_top_fmc_adc_100Ms_par.xrpt spec_top_fmc_adc_100Ms_summary.xml spec_top_fmc_adc_100Ms_usage.xml spec_top_fmc_adc_100Ms_xst.xrpt usage_statistics_webtalk.html webtalk.log webtalk_pn.xml run.tcl
#target for performing local synthesis
local:
echo "project open $(PROJECT)" > run.tcl
echo "process run {Generate Programming File} -force rerun_all" >> run.tcl
xtclsh run.tcl
#target for cleaing all intermediate stuff
clean:
rm -f $(ISE_CRAP)
rm -rf xst xlnx_auto_*_xdb iseconfig _xmsgs _ngo
#target for cleaning final files
mrproper:
rm -f *.bit *.bin *.mcs
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