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FMC ADC 100M 14b 4cha - Gateware
Commit 67f7189d authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Add integration record to sdb rom.

parent 769d01ee
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Showing with 20 additions and 9 deletions
hdl/spec/rtl/sdb_meta_pkg.vhd
View file @ 67f7189d
......@@ -11,24 +11,25 @@ package sdb_meta_pkg is
-- Meta-information sdb records
------------------------------------------------------------------------------
-- Top module repository url (64 bytes)
-- Top module repository url
constant c_REPO_URL : t_sdb_repo_url := (
-- url (utf-8, 63 bytes)
-- url (string, 63 char)
repo_url => "git://ohwr.org/fmc-projects/fmc-adc-100m14b4cha.git ");
-- Synthesis informations (64 bytes)
-- Synthesis informations
constant c_SYNTHESIS : t_sdb_synthesis := (
-- Top module name (utf-8, 16 bytes)
-- Top module name (string, 16 char)
syn_module_name => "spec_top_fmc_adc",
-- Commit ID (hex string, 128-bit = 32 char)
-- git log -1 --format="%H" | cut -c1-31
syn_commit_id => "150b83db8fa9e0ff9050166b7695ee9a",
-- Synthesis tool name (utf-8, 8 bytes)
-- Synthesis tool name (string, 8 char)
syn_tool_name => "ISE ",
-- Synthesis tool version (bcd encoded, 32-bit)
syn_tool_version => x"00000133",
-- Synthesis date (bcd encoded, 32-bit)
syn_date => x"20130307",
-- Synthesised by (utf-8, 15 bytes)
-- Synthesised by (string, 15 char)
syn_username => "mcattin ");
end sdb_meta_pkg;
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 67f7189d
......@@ -241,10 +241,20 @@ architecture rtl of spec_top_fmc_adc_100Ms is
-- WARNING: All address in sdb and crossbar are BYTE addresses!
------------------------------------------------------------------------------
-- Integration record
constant c_INTEGRATION : t_sdb_integration := (
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"c5be045e", -- echo "fmc-adc-100m14b4cha" | md5sum | cut -c1-8
version => x"00010000", -- bcd encoded, [31:16] = major, [15:0] = minor
date => x"20130307", -- yyyymmdd
name => "fmc-adc-100m14b4cha")));
-- Meta-information sdb records
constant c_SDB_INFO : t_sdb_record_array(1 downto 0) := (
0 => f_sdb_embed_repo_url(c_REPO_URL),
1 => f_sdb_embed_synthesis(c_SYNTHESIS)
1 => f_sdb_embed_synthesis(c_SYNTHESIS),
2 => f_sdb_embed_integration(c_INTEGRATION)
);
-- Number of master port(s) on the wishbone crossbar
......@@ -552,8 +562,8 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal acq_end_p : std_logic;
-- Tests
signal led_cnt : unsigned(26 downto 0);
signal led_pps : std_logic;
signal led_cnt : unsigned(26 downto 0);
signal led_pps : std_logic;
begin
......
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