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FMC ADC 100M 14b 4cha - Gateware
Commit 6b1a7ed0 authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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[hdl] private development, do not use this commit

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ddr3-sp6-core @ 6042b89d
Subproject commit 28dad2087c8df45056179796c9337c149e3cec03
Subproject commit 6042b89dd5831aa40963a2494e52659493cbbaac
general-cores @ 6b394362
Subproject commit 63f3671351127a398006e01f66b37adb7eda9a37
Subproject commit 6b394362cda9b87c0ee94aabc3efdffb80e22fc7
gn4124-core @ 692a4195
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
Subproject commit 692a419568a109a2d7c145296136193debfe8f59
spec @ 1ad6101f
Subproject commit 266a209cb945e7946c99ec01bace6990d08688bc
Subproject commit 1ad6101f9c363f0ff83f26ed082c9d63e1c4f89b
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 6b1a7ed0
......@@ -301,18 +301,14 @@ architecture rtl of fmc_adc_100Ms_core is
signal wb_ddr_fifo_full : std_logic;
signal wb_ddr_fifo_wr : std_logic;
signal wb_ddr_fifo_rd : std_logic;
signal wb_ddr_fifo_valid : std_logic;
signal wb_ddr_fifo_wr_en : std_logic;
-- RAM address counter
signal ram_addr_cnt : unsigned(24 downto 0);
signal ram_addr_cnt : unsigned(28 downto 0);
signal test_data_en : std_logic;
signal trig_addr : std_logic_vector(31 downto 0);
signal mem_ovr : std_logic;
-- Wishbone interface to DDR
signal wb_ddr_stall_t : std_logic;
-- IO from CSR registers
signal csr_regin : t_fmc_adc_100ms_csr_master_in;
signal csr_regout : t_fmc_adc_100ms_csr_master_out;
......@@ -1064,7 +1060,7 @@ begin
end if;
end process p_shots_cnt;
multishot_buffer_sel <= std_logic(shots_cnt(0));
multishot_buffer_sel <= not std_logic(shots_cnt(0));
shots_done <= '1' when shots_cnt = to_unsigned(1, shots_cnt'length) else '0';
remaining_shots <= std_logic_vector(shots_cnt);
......@@ -1366,7 +1362,7 @@ begin
p_dpram_addra_cnt : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
if sys_rst_n_i = '0' or single_shot = '1' then
dpram_addra_cnt <= (others => '0');
dpram_addra_trig <= (others => '0');
dpram_addra_post_done <= (others => '0');
......@@ -1389,10 +1385,14 @@ begin
-- DPRAM inputs
dpram0_addra <= std_logic_vector(dpram_addra_cnt);
dpram1_addra <= std_logic_vector(dpram_addra_cnt);
dpram0_dina <= sync_fifo_dout(63 downto 0) when acq_in_trig_tag = '0' else trig_tag_data;
dpram1_dina <= sync_fifo_dout(63 downto 0) when acq_in_trig_tag = '0' else trig_tag_data;
dpram0_wea <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '0' else '0';
dpram1_wea <= (samples_wr_en and sync_fifo_valid) or acq_in_trig_tag when multishot_buffer_sel = '1' else '0';
dpram0_dina <= sync_fifo_dout(63 downto 0)
when acq_in_trig_tag = '0' else trig_tag_data;
dpram1_dina <= sync_fifo_dout(63 downto 0)
when acq_in_trig_tag = '0' else trig_tag_data;
dpram0_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
when multishot_buffer_sel = '0' else '0';
dpram1_wea <= not single_shot and ((samples_wr_en and sync_fifo_valid) or acq_in_trig_tag)
when multishot_buffer_sel = '1' else '0';
-- DPRAMs
cmp_multishot_dpram0 : generic_dpram
......@@ -1453,7 +1453,7 @@ begin
p_dpram_addrb_cnt : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
if sys_rst_n_i = '0' or single_shot = '1' then
dpram_addrb_cnt <= (others => '0');
dpram_valid_t <= '0';
dpram_valid <= '0';
......@@ -1483,7 +1483,7 @@ begin
generic map (
g_DATA_WIDTH => 65,
g_SIZE => 256,
g_SHOW_AHEAD => FALSE,
g_SHOW_AHEAD => TRUE,
g_WITH_EMPTY => TRUE,
g_WITH_FULL => TRUE,
g_WITH_ALMOST_EMPTY => FALSE,
......@@ -1509,15 +1509,15 @@ begin
-- One clock cycle delay for the FIFO's VALID signal. Since the General Cores
-- package does not offer the possibility to use the FWFT feature of the FIFOs,
-- we simulate the valid flag here according to Figure 4-7 in ref. [1].
p_wb_ddr_fifo_valid : process (sys_clk_i) is
begin
if rising_edge(sys_clk_i) then
wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
if (wb_ddr_fifo_empty = '1') then
wb_ddr_fifo_valid <= '0';
end if;
end if;
end process;
-- p_wb_ddr_fifo_valid : process (sys_clk_i) is
-- begin
-- if rising_edge(sys_clk_i) then
-- wb_ddr_fifo_valid <= wb_ddr_fifo_rd;
-- if (wb_ddr_fifo_empty = '1') then
-- wb_ddr_fifo_valid <= '0';
-- end if;
-- end if;
-- end process;
p_wb_ddr_fifo_input : process (sys_clk_i)
begin
......@@ -1544,11 +1544,13 @@ begin
wb_ddr_fifo_wr <= wb_ddr_fifo_wr_en and not(wb_ddr_fifo_full);
wb_ddr_fifo_rd <= not(wb_ddr_fifo_empty or wb_ddr_stall_t);
wb_ddr_fifo_rd <= not(wb_ddr_fifo_empty or wb_ddr_master_i.stall);
------------------------------------------------------------------------------
-- RAM address counter (32-bit word address)
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
-- RAM address counter (64-bit word address)
p_ram_addr_cnt : process (wb_ddr_clk_i)
begin
if rising_edge(wb_ddr_clk_i) then
......@@ -1557,70 +1559,77 @@ begin
else
if acq_start = '1' then
ram_addr_cnt <= (others => '0');
elsif wb_ddr_fifo_valid = '1' then
elsif wb_ddr_fifo_empty = '0' and wb_ddr_master_i.stall = '0' then
ram_addr_cnt <= ram_addr_cnt + 1;
end if;
end if;
end if;
end process p_ram_addr_cnt;
------------------------------------------------------------------------------
wb_ddr_master_o.cyc <= '1';
wb_ddr_master_o.stb <= not wb_ddr_fifo_empty;
-- Convert to 32-bit word addressing for Wishbone
wb_ddr_master_o.adr <= "00" & std_logic_vector(ram_addr_cnt) & "0";
wb_ddr_master_o.we <= '1';
wb_ddr_master_o.sel <= X"FF";
with test_data_en select
wb_ddr_master_o.dat <=
x"00000000" & "000" & std_logic_vector(ram_addr_cnt) when '1',
wb_ddr_fifo_dout(63 downto 0) when others;
-- Store trigger DDR address (byte address)
------------------------------------------------------------------------------
p_trig_addr : process (wb_ddr_clk_i)
begin
if rising_edge(wb_ddr_clk_i) then
if wb_ddr_rst_n_i = '0' then
trig_addr <= (others => '0');
else
if wb_ddr_fifo_dout(64) = '1' and wb_ddr_fifo_valid = '1' then
trig_addr <= "0000" & std_logic_vector(ram_addr_cnt) & "000";
if wb_ddr_fifo_dout(64) = '1' and wb_ddr_fifo_empty = '0' then
-- Convert to byte addressing
trig_addr <= std_logic_vector(ram_addr_cnt) & "000";
end if;
end if;
end if;
end process p_trig_addr;
------------------------------------------------------------------------------
-- Wishbone master (to DDR)
------------------------------------------------------------------------------
p_wb_master : process (wb_ddr_clk_i)
begin
if rising_edge(wb_ddr_clk_i) then
if wb_ddr_rst_n_i = '0' then
wb_ddr_master_o.cyc <= '0';
wb_ddr_master_o.we <= '0';
wb_ddr_master_o.stb <= '0';
wb_ddr_master_o.adr <= (others => '0');
wb_ddr_master_o.dat <= (others => '0');
wb_ddr_stall_t <= '0';
else
if wb_ddr_fifo_valid = '1' then
wb_ddr_master_o.stb <= '1';
wb_ddr_master_o.adr <= "0000000" & std_logic_vector(ram_addr_cnt);
if test_data_en = '1' then
wb_ddr_master_o.dat <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
else
wb_ddr_master_o.dat <= wb_ddr_fifo_dout(63 downto 0);
end if;
else
wb_ddr_master_o.stb <= '0';
end if;
if wb_ddr_fifo_valid = '1' then
wb_ddr_master_o.cyc <= '1';
wb_ddr_master_o.we <= '1';
elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
wb_ddr_master_o.cyc <= '0';
wb_ddr_master_o.we <= '0';
end if;
wb_ddr_stall_t <= wb_ddr_master_i.stall;
-- p_wb_master : process (wb_ddr_clk_i)
-- begin
-- if rising_edge(wb_ddr_clk_i) then
-- if wb_ddr_rst_n_i = '0' then
-- wb_ddr_master_o.cyc <= '0';
-- wb_ddr_master_o.we <= '0';
-- wb_ddr_master_o.stb <= '0';
-- wb_ddr_master_o.adr <= (others => '0');
-- wb_ddr_master_o.dat <= (others => '0');
-- wb_ddr_stall_t <= '0';
-- else
-- if wb_ddr_fifo_valid = '1' then
-- wb_ddr_master_o.stb <= '1';
-- wb_ddr_master_o.adr <= "0000000" & std_logic_vector(ram_addr_cnt);
-- if test_data_en = '1' then
-- wb_ddr_master_o.dat <= x"00000000" & "0000000" & std_logic_vector(ram_addr_cnt);
-- else
-- wb_ddr_master_o.dat <= wb_ddr_fifo_dout(63 downto 0);
-- end if;
-- else
-- wb_ddr_master_o.stb <= '0';
-- end if;
-- if wb_ddr_fifo_valid = '1' then
-- wb_ddr_master_o.cyc <= '1';
-- wb_ddr_master_o.we <= '1';
-- elsif (wb_ddr_fifo_empty = '1') and (acq_fsm_state = "001") then
-- wb_ddr_master_o.cyc <= '0';
-- wb_ddr_master_o.we <= '0';
-- end if;
-- wb_ddr_stall_t <= wb_ddr_master_i.stall;
-- end if;
-- end if;
-- end process p_wb_master;
end if;
end if;
end process p_wb_master;
wb_ddr_master_o.sel <= X"FF";
-- Trigout
......
hdl/testbench/spec_ref_design/.gitignore 0 → 100644
View file @ 6b1a7ed0
Makefile
work/
transcript
vsim.wlf
NullFile
modelsim.ini
buildinfo_pkg.vhd
hdl/testbench/spec_ref_design/Manifest.py 0 → 100644
View file @ 6b1a7ed0
board = "spec"
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
vcom_opt = "-93 -mixedsvvh"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
include_dirs = [
"../include",
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim/",
fetchto + "/general-cores/modules/wishbone/wb_spi/",
fetchto + "/ddr3-sp6-core/hdl/sim/",
]
files = [
"main.sv",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/spec_ref_design",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank3_64b_32b" ]
hdl/testbench/spec_ref_design/main.sv 0 → 100644
View file @ 6b1a7ed0
This diff is collapsed.
hdl/testbench/spec_ref_design/run.do 0 → 100644
View file @ 6b1a7ed0
vsim -quiet -t 10fs -L unisim work.main -voptargs=+acc -suppress 143,1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
hdl/testbench/spec_ref_design/run_ci.do 0 → 100644
View file @ 6b1a7ed0
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run -all
hdl/testbench/spec_ref_design/wave.do 0 → 100644
View file @ 6b1a7ed0
This diff is collapsed.
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