hdl: introduced new hardware trigger source based on time

6dee5c3b · Dimitris Lampridis · f2c83354 · 6dee5c3b · 6dee5c3b · 6dee5c3b
Commit 6dee5c3b authored Jun 16, 2016 by Dimitris Lampridis
15 changed files
--- a/doc/manual/fmc_adc_100Ms_csr.tex
+++ b/doc/manual/fmc_adc_100Ms_csr.tex
@@ -218,41 +218,36 @@ Acquisition configuration status
 @regsection @code{trig_cfg} - Trigger configuration
 @multitable @columnfractions .10 .10 .15 .10 .55
 @headitem Bits @tab Access @tab Prefix @tab Default @tab Name
-@item @code{0}
+@item @code{1...0}
 @tab R/W @tab
 @code{HW_TRIG_SEL}
 @tab @code{0} @tab 
 Hardware trigger selection
-@item @code{1}
+@item @code{2}
 @tab R/W @tab
 @code{HW_TRIG_POL}
 @tab @code{0} @tab 
 Hardware trigger polarity
-@item @code{2}
+@item @code{3}
 @tab R/W @tab
 @code{HW_TRIG_EN}
 @tab @code{0} @tab 
 Hardware trigger enable
-@item @code{3}
+@item @code{4}
 @tab R/W @tab
 @code{SW_TRIG_EN}
 @tab @code{0} @tab 
 Software trigger enable
-@item @code{5...4}
+@item @code{6...5}
 @tab R/W @tab
 @code{INT_TRIG_SEL}
 @tab @code{0} @tab 
 Channel selection for internal trigger
-@item @code{6}
+@item @code{7}
 @tab R/W @tab
 @code{INT_TRIG_TEST_EN}
 @tab @code{0} @tab 
 Enable internal trigger test mode
-@item @code{7}
-@tab R/W @tab
-@code{RESERVED}
-@tab @code{0} @tab 
-Reserved
 @item @code{15...8}
 @tab R/W @tab
 @code{INT_TRIG_THRES_FILT}
@@ -266,13 +261,12 @@ Threshold for internal trigger
 @end multitable
 @multitable @columnfractions 0.15 0.85
 @headitem Field @tab Description
-@item @code{hw_trig_sel} @tab 0: internal (data threshold)@*1: external (front panel trigger input)
+@item @code{hw_trig_sel} @tab 00: internal (data threshold)@*01: external (front panel trigger input)@*10: trigger from timetag core@*11: reserved (for WR message-based trigger)
 @item @code{hw_trig_pol} @tab 0: positive edge/slope@*1: negative edge/slope
 @item @code{hw_trig_en} @tab 0: disable@*1: enable
 @item @code{sw_trig_en} @tab 0: disable@*1: enable
 @item @code{int_trig_sel} @tab 00: channel 1@*01: channel 2@*10: channel 3@*11: channel 4
 @item @code{int_trig_test_en} @tab Test mode:@* ch1 = Channel 1 input(analogue)@* ch2 = Channel input over threshold (digital)@* ch3 = Channel input over threshold filtered (digital)@* ch4 = Trigger (digital)
-@item @code{reserved} @tab Ignore on read, write with 0's
 @item @code{int_trig_thres_filt} @tab Configures the internal trigger threshold glitch filter length.
 @item @code{int_trig_thres} @tab Treated as binary two's complement and compared to raw ADC data.
 @end multitable

--- a/doc/manual/timetag_core_regs.tex
+++ b/doc/manual/timetag_core_regs.tex
@@ -15,49 +15,61 @@ REG @tab
 Timetag coarse time register, system clock ticks (125MHz)
 @item @code{0xc} @tab
 REG @tab
+@code{time_trig_seconds_upper} @tab
+Time trigger seconds register (upper)
+@item @code{0x10} @tab
+REG @tab
+@code{time_trig_seconds_lower} @tab
+Timetag seconds register (lower)
+@item @code{0x14} @tab
+REG @tab
+@code{time_trig_coarse} @tab
+Timetag coarse time register, system clock ticks (125MHz)
+@item @code{0x18} @tab
+REG @tab
 @code{trig_tag_seconds_upper} @tab
 Trigger time-tag seconds register (upper)
-@item @code{0x10} @tab
+@item @code{0x1c} @tab
 REG @tab
 @code{trig_tag_seconds_lower} @tab
 Trigger time-tag seconds register (lower)
-@item @code{0x14} @tab
+@item @code{0x20} @tab
 REG @tab
 @code{trig_tag_coarse} @tab
 Trigger time-tag coarse time (system clock ticks 125MHz) register
-@item @code{0x18} @tab
+@item @code{0x24} @tab
 REG @tab
 @code{acq_start_tag_seconds_upper} @tab
 Acquisition start time-tag seconds register (upper)
-@item @code{0x1c} @tab
+@item @code{0x28} @tab
 REG @tab
 @code{acq_start_tag_seconds_lower} @tab
 Acquisition start time-tag seconds register (lower)
-@item @code{0x20} @tab
+@item @code{0x2c} @tab
 REG @tab
 @code{acq_start_tag_coarse} @tab
 Acquisition start time-tag coarse time (system clock ticks 125MHz) register
-@item @code{0x24} @tab
+@item @code{0x30} @tab
 REG @tab
 @code{acq_stop_tag_seconds_upper} @tab
 Acquisition stop time-tag seconds register (upper)
-@item @code{0x28} @tab
+@item @code{0x34} @tab
 REG @tab
 @code{acq_stop_tag_seconds_lower} @tab
 Acquisition stop time-tag seconds register (lower)
-@item @code{0x2c} @tab
+@item @code{0x38} @tab
 REG @tab
 @code{acq_stop_tag_coarse} @tab
 Acquisition stop time-tag coarse time (system clock ticks 125MHz) register
-@item @code{0x30} @tab
+@item @code{0x3c} @tab
 REG @tab
 @code{acq_end_tag_seconds_upper} @tab
 Acquisition end time-tag seconds register (upper)
-@item @code{0x34} @tab
+@item @code{0x40} @tab
 REG @tab
 @code{acq_end_tag_seconds_lower} @tab
 Acquisition end time-tag seconds register (lower)
-@item @code{0x38} @tab
+@item @code{0x44} @tab
 REG @tab
 @code{acq_end_tag_coarse} @tab
 Acquisition end time-tag coarse time (system clock ticks 125MHz) register
@@ -92,6 +104,36 @@ Coarse time counter clocked by 125MHz system clock.@*Counts from 0 to 125000000.
 @tab @code{X} @tab 
 Timetag coarse time
 @end multitable
+@regsection @code{time_trig_seconds_upper} - Time trigger seconds register (upper)
+8 upper bits of seconds used for timer trigger.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{7...0}
+@tab R/W @tab
+@code{TIME_TRIG_SECONDS_UPPER}
+@tab @code{0} @tab 
+Time trigger seconds
+@end multitable
+@regsection @code{time_trig_seconds_lower} - Timetag seconds register (lower)
+32 lower bits of seconds used for time trigger.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{31...0}
+@tab R/W @tab
+@code{TIME_TRIG_SECONDS_LOWER}
+@tab @code{0} @tab 
+Time trigger seconds
+@end multitable
+@regsection @code{time_trig_coarse} - Timetag coarse time register, system clock ticks (125MHz)
+Coarse time counter clocked by 125MHz system clock.@*Counts from 0 to 125000000.
+@multitable @columnfractions .10 .10 .15 .10 .55
+@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
+@item @code{27...0}
+@tab R/W @tab
+@code{TIME_TRIG_COARSE}
+@tab @code{0} @tab 
+Time trigger coarse value
+@end multitable
 @regsection @code{trig_tag_seconds_upper} - Trigger time-tag seconds register (upper)
 @multitable @columnfractions .10 .10 .15 .10 .55
 @headitem Bits @tab Access @tab Prefix @tab Default @tab Name

--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
@@ -9,7 +9,7 @@
 --              Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-24
-- Last update: 2016-06-08
+-- Last update: 2016-06-15
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
 -- Description: FMC ADC 100Ms/s core.
@@ -88,8 +88,9 @@ entity fmc_adc_100Ms_core is
    acq_stop_p_o  : out std_logic;
    acq_end_p_o   : out std_logic;

-    -- Trigger time-tag input
-    trigger_tag_i : t_timetag;
+    -- Trigger time-tag inputs
+    trigger_tag_i : in t_timetag;
+    time_trig_i   : in std_logic;

    -- FMC interface
    ext_trigger_p_i : in std_logic;               -- External trigger
@@ -174,13 +175,12 @@ architecture rtl of fmc_adc_100Ms_core is
      fmc_adc_core_sta_serdes_pll_i               : in  std_logic;
      fmc_adc_core_sta_serdes_synced_i            : in  std_logic;
      fmc_adc_core_sta_acq_cfg_i                  : in  std_logic;
-      fmc_adc_core_trig_cfg_hw_trig_sel_o         : out std_logic;
+      fmc_adc_core_trig_cfg_hw_trig_sel_o         : out std_logic_vector(1 downto 0);
      fmc_adc_core_trig_cfg_hw_trig_pol_o         : out std_logic;
      fmc_adc_core_trig_cfg_hw_trig_en_o          : out std_logic;
      fmc_adc_core_trig_cfg_sw_trig_en_o          : out std_logic;
      fmc_adc_core_trig_cfg_int_trig_sel_o        : out std_logic_vector(1 downto 0);
      fmc_adc_core_trig_cfg_int_trig_test_en_o    : out std_logic;
-      fmc_adc_core_trig_cfg_reserved_o            : out std_logic;
      fmc_adc_core_trig_cfg_int_trig_thres_filt_o : out std_logic_vector(7 downto 0);
      fmc_adc_core_trig_cfg_int_trig_thres_o      : out std_logic_vector(15 downto 0);
      fmc_adc_core_trig_dly_o                     : out std_logic_vector(31 downto 0);
@@ -320,6 +320,7 @@ architecture rtl of fmc_adc_100Ms_core is
  -- Trigger
  signal ext_trig_a                 : std_logic;
  signal ext_trig                   : std_logic;
+  signal time_trig                  : std_logic;
  signal int_trig                   : std_logic;
  signal int_trig_over_thres        : std_logic;
  signal int_trig_over_thres_d      : std_logic;
@@ -333,7 +334,7 @@ architecture rtl of fmc_adc_100Ms_core is
  signal hw_trig_pol                : std_logic;
  signal hw_trig                    : std_logic;
  signal hw_trig_t                  : std_logic;
-  signal hw_trig_sel                : std_logic;
+  signal hw_trig_sel                : std_logic_vector(1 downto 0);
  signal hw_trig_en                 : std_logic;
  signal sw_trig                    : std_logic;
  signal sw_trig_t                  : std_logic;
@@ -757,7 +758,6 @@ begin
      fmc_adc_core_trig_cfg_sw_trig_en_o          => sw_trig_en,
      fmc_adc_core_trig_cfg_int_trig_sel_o        => int_trig_sel,
      fmc_adc_core_trig_cfg_int_trig_test_en_o    => int_trig_test_en,
-      fmc_adc_core_trig_cfg_reserved_o            => open,
      fmc_adc_core_trig_cfg_int_trig_thres_filt_o => int_trig_thres_filt,
      fmc_adc_core_trig_cfg_int_trig_thres_o      => int_trig_thres,
      fmc_adc_core_trig_dly_o                     => trig_delay,
@@ -825,7 +825,7 @@ begin
      );

  -- External hardware trigger synchronization
-  cmp_trig_sync : ext_pulse_sync
+  cmp_ext_trig_sync : ext_pulse_sync
    generic map(
      g_MIN_PULSE_WIDTH => 1,                     -- clk_i ticks
      g_CLK_FREQUENCY   => 100,                   -- MHz
@@ -841,6 +841,23 @@ begin
      pulse_o          => ext_trig
      );

+  -- Time trigger synchronization (from 125MHz timetag core)
+  cmp_time_trig_sync : ext_pulse_sync
+    generic map(
+      g_MIN_PULSE_WIDTH => 1,                     -- clk_i ticks
+      g_CLK_FREQUENCY   => 100,                   -- MHz
+      g_OUTPUT_POLARITY => '0',                   -- positive pulse
+      g_OUTPUT_RETRIG   => FALSE,
+      g_OUTPUT_LENGTH   => 1                      -- clk_i tick
+      )
+    port map(
+      rst_n_i          => fs_rst_n,
+      clk_i            => fs_clk,
+      input_polarity_i => hw_trig_pol,
+      pulse_i          => time_trig_i,
+      pulse_o          => time_trig
+      );
+
  -- Internal hardware trigger
  int_trig_data <= data_calibr_out(15 downto 0) when int_trig_sel = "00" else   -- CH1 selected
                   data_calibr_out(31 downto 16) when int_trig_sel = "01" else  -- CH2 selected
@@ -889,9 +906,16 @@ begin
              not(int_trig_over_thres_filt) and int_trig_over_thres_filt_d;  -- negative slope

  -- Hardware trigger selection
-  --    internal = adc data threshold
-  --    external = pulse from front panel
-  hw_trig_t <= ext_trig when hw_trig_sel = '1' else int_trig;
+  --    00: internal = adc data threshold
+  --    01: external = pulse from front panel
+  --    10: time     = time trigger
+  --    11: reserved = (for WR message-based interrupts)
+  with hw_trig_sel select
+    hw_trig_t <=
+    int_trig  when "00",
+    ext_trig  when "01",
+    time_trig when "10",
+    '0'       when others;

  -- Hardware trigger enable
  hw_trig <= hw_trig_t and hw_trig_en;
@@ -1047,7 +1071,7 @@ begin
                    trig_tst & int_trig_over_thres_filt_tst &
                    int_trig_over_thres_tst &
                    data_calibr_out_d(3)(15 downto 0)) when int_trig_test_en = '1' else
-                   (trig_align & data_calibr_out_d(3)) when hw_trig_sel = '0' else
+                   (trig_align & data_calibr_out_d(3)) when hw_trig_sel = "00" else
                   (trig_align & data_calibr_out);

  -- FOR DEBUG: FR instead of CH1 and SerDes Synced instead of CH2

--- a/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- FMC ADC 100Ms/s core package
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_100Ms_core_pkg (fmc_adc_100Ms_core_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 16-11-2012
--
-- version: 1.0
--
-- description: Package for FMC ADC 100Ms/s core
--
-- dependencies:
--
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Title      : FMC ADC 100Ms/s core package
+-- Project    : FMC ADC 100M 14B 4CHA gateware
+-- URL        : http://www.ohwr.org/projects/fmc-adc-100m14b4cha-gw
+-------------------------------------------------------------------------------
+-- File       : fmc_adc_100Ms_core_pkg.vhd
+-- Author(s)  : Matthieu Cattin <matthieu.cattin@cern.ch>
+--              Theodor Stana <t.stana@cern.ch>
+--              Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
+-- Company    : CERN (BE-CO-HT)
+-- Created    : 2012-11-16
+-- Last update: 2016-06-15
+-- Standard   : VHDL'93/02
+-------------------------------------------------------------------------------
+-- Description: Package for FMC ADC 100Ms/s core.
+-------------------------------------------------------------------------------
+-- Copyright (c) 2011-2016 CERN (BE-CO-HT)
+-------------------------------------------------------------------------------
 -- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
 -- This source file is free software; you can redistribute it and/or modify it
 -- under the terms of the GNU Lesser General Public License as published by the
 -- Free Software Foundation; either version 2.1 of the License, or (at your
@@ -28,11 +27,11 @@
 -- See the GNU Lesser General Public License for more details. You should have
 -- received a copy of the GNU Lesser General Public License along with this
 -- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: - 
--------------------------------------------------------------------------------
+-------------------------------------------------------------------------------
+-- Revisions  :
+-- Date        Version  Author
+-- 2012-11-16  1.0      Matthieu Cattin
+-------------------------------------------------------------------------------

 library IEEE;
 use IEEE.STD_LOGIC_1164.all;
@@ -88,10 +87,11 @@ package fmc_adc_100Ms_core_pkg is
      acq_end_p_o   : out std_logic;

      -- Trigger time-tag input
-      trigger_tag_i : t_timetag;
+      trigger_tag_i : in t_timetag;
+      time_trig_i   : in std_logic;

      -- FMC interface
-      ext_trigger_p_i : in std_logic;   -- External trigger
+      ext_trigger_p_i : in std_logic;             -- External trigger
      ext_trigger_n_i : in std_logic;

      adc_dco_p_i  : in std_logic;                     -- ADC data clock
@@ -103,14 +103,14 @@ package fmc_adc_100Ms_core_pkg is
      adc_outb_p_i : in std_logic_vector(3 downto 0);  -- ADC serial data (even bits)
      adc_outb_n_i : in std_logic_vector(3 downto 0);

-      gpio_dac_clr_n_o : out std_logic;                     -- offset DACs clear (active low)
-      gpio_led_acq_o   : out std_logic;                     -- Mezzanine front panel power LED (PWR)
-      gpio_led_trig_o  : out std_logic;                     -- Mezzanine front panel trigger LED (TRIG)
+      gpio_dac_clr_n_o : out std_logic;           -- offset DACs clear (active low)
+      gpio_led_acq_o   : out std_logic;           -- Mezzanine front panel power LED (PWR)
+      gpio_led_trig_o  : out std_logic;           -- Mezzanine front panel trigger LED (TRIG)
      gpio_ssr_ch1_o   : out std_logic_vector(6 downto 0);  -- Channel 1 solid state relays control
      gpio_ssr_ch2_o   : out std_logic_vector(6 downto 0);  -- Channel 2 solid state relays control
      gpio_ssr_ch3_o   : out std_logic_vector(6 downto 0);  -- Channel 3 solid state relays control
      gpio_ssr_ch4_o   : out std_logic_vector(6 downto 0);  -- Channel 4 solid state relays control
-      gpio_si570_oe_o  : out std_logic                      -- Si570 (programmable oscillator) output enable
+      gpio_si570_oe_o  : out std_logic            -- Si570 (programmable oscillator) output enable
      );
  end component fmc_adc_100Ms_core;


--- a/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
--- a/hdl/adc/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/adc/rtl/fmc_adc_mezzanine.vhd
@@ -8,7 +8,7 @@
 --              Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2013-05-07
-- Last update: 2016-06-09
+-- Last update: 2016-06-15
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
 -- Description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core
@@ -121,7 +121,7 @@ entity fmc_adc_mezzanine is
    sys_scl_b : inout std_logic;                  -- Mezzanine system I2C clock (EEPROM)
    sys_sda_b : inout std_logic;                  -- Mezzanine system I2C data (EEPROM)

-    wr_enable_i : in std_logic                   -- enable white rabbit features on mezzanine
+    wr_enable_i : in std_logic                    -- enable white rabbit features on mezzanine
    );
 end fmc_adc_mezzanine;

@@ -286,12 +286,12 @@ architecture rtl of fmc_adc_mezzanine is
  signal acq_end_extend      : std_logic;

  -- Time-tagging core
-  signal trigger_p   : std_logic;
-  signal acq_start_p : std_logic;
-  signal acq_stop_p  : std_logic;
-  signal acq_end_p   : std_logic;
-  signal trigger_tag : t_timetag;
-
+  signal trigger_p    : std_logic;
+  signal acq_start_p  : std_logic;
+  signal acq_stop_p   : std_logic;
+  signal acq_end_p    : std_logic;
+  signal trigger_tag  : t_timetag;
+  signal time_trigger : std_logic;

 begin

@@ -487,6 +487,7 @@ begin
      acq_end_p_o   => acq_end_p,

      trigger_tag_i => trigger_tag,
+      time_trig_i   => time_trigger,

      ext_trigger_p_i => ext_trigger_p_i,
      ext_trigger_n_i => ext_trigger_n_i,
@@ -618,9 +619,10 @@ begin
      wr_tm_tai_i        => X"123456789a",
      wr_tm_cycles_i     => X"edcba98",

-      trig_tag_o => trigger_tag,
+      trig_tag_o  => trigger_tag,
+      time_trig_o => time_trigger,

-      wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(5 downto 2),  -- cnx_master_out.adr is byte address
+      wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2),  -- cnx_master_out.adr is byte address
      wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat,
      wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat,
      wb_cyc_i => cnx_master_out(c_WB_SLAVE_TIMETAG).cyc,

--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
@@ -3,7 +3,7 @@

  * File           : fmc_adc_100Ms_csr.h
  * Author         : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-  * Created        : Mon Apr 18 16:09:20 2016
+  * Created        : Thu Jun 16 15:16:07 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
@@ -77,28 +77,28 @@
 /* definitions for register: Trigger configuration */

 /* definitions for field: Hardware trigger selection in reg: Trigger configuration */
-#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL     WBGEN2_GEN_MASK(0, 1)
+#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL_MASK WBGEN2_GEN_MASK(0, 2)
+#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL_SHIFT 0
+#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 0, 2)
+#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 0, 2)

 /* definitions for field: Hardware trigger polarity in reg: Trigger configuration */
-#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_POL     WBGEN2_GEN_MASK(1, 1)
+#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_POL     WBGEN2_GEN_MASK(2, 1)

 /* definitions for field: Hardware trigger enable in reg: Trigger configuration */
-#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_EN      WBGEN2_GEN_MASK(2, 1)
+#define FMC_ADC_CORE_TRIG_CFG_HW_TRIG_EN      WBGEN2_GEN_MASK(3, 1)

 /* definitions for field: Software trigger enable in reg: Trigger configuration */
-#define FMC_ADC_CORE_TRIG_CFG_SW_TRIG_EN      WBGEN2_GEN_MASK(3, 1)
+#define FMC_ADC_CORE_TRIG_CFG_SW_TRIG_EN      WBGEN2_GEN_MASK(4, 1)

 /* definitions for field: Channel selection for internal trigger in reg: Trigger configuration */
-#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_MASK WBGEN2_GEN_MASK(4, 2)
-#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_SHIFT 4
-#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 4, 2)
-#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 4, 2)
+#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_MASK WBGEN2_GEN_MASK(5, 2)
+#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_SHIFT 5
+#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_W(value) WBGEN2_GEN_WRITE(value, 5, 2)
+#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_SEL_R(reg) WBGEN2_GEN_READ(reg, 5, 2)

 /* definitions for field: Enable internal trigger test mode in reg: Trigger configuration */
-#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_TEST_EN WBGEN2_GEN_MASK(6, 1)
-
-/* definitions for field: Reserved in reg: Trigger configuration */
-#define FMC_ADC_CORE_TRIG_CFG_RESERVED        WBGEN2_GEN_MASK(7, 1)
+#define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_TEST_EN WBGEN2_GEN_MASK(7, 1)

 /* definitions for field: Internal trigger threshold glitch filter in reg: Trigger configuration */
 #define FMC_ADC_CORE_TRIG_CFG_INT_TRIG_THRES_FILT_MASK WBGEN2_GEN_MASK(8, 8)

--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
@@ -969,10 +969,10 @@ fmc_adc_core_sta_acq_cfg_i

 </td>
 <td  class="td_pblock_right">
-fmc_adc_core_trig_cfg_hw_trig_sel_o
+fmc_adc_core_trig_cfg_hw_trig_sel_o[1:0]
 </td>
 <td  class="td_arrow_right">
-&rarr;
+&rArr;
 </td>
 </tr>
 <tr>
@@ -1069,23 +1069,6 @@ fmc_adc_core_trig_cfg_int_trig_test_en_o
 </td>
 <td  class="td_sym_center">

-</td>
-<td  class="td_pblock_right">
-fmc_adc_core_trig_cfg_reserved_o
-</td>
-<td  class="td_arrow_right">
-&rarr;
-</td>
-</tr>
-<tr>
-<td  class="td_arrow_left">
-
-</td>
-<td  class="td_pblock_left">
-
-</td>
-<td  class="td_sym_center">
-
 </td>
 <td  class="td_pblock_right">
 fmc_adc_core_trig_cfg_int_trig_thres_filt_o[7:0]
@@ -3488,9 +3471,6 @@ INT_TRIG_THRES_FILT[7:0]
 </tr>
 <tr>
 <td style="border: solid 1px black;" colspan=1  class="td_field">
-RESERVED
-</td>
-<td style="border: solid 1px black;" colspan=1  class="td_field">
 INT_TRIG_TEST_EN
 </td>
 <td style="border: solid 1px black;" colspan=2  class="td_field">
@@ -3505,8 +3485,11 @@ HW_TRIG_EN
 <td style="border: solid 1px black;" colspan=1  class="td_field">
 HW_TRIG_POL
 </td>
-<td style="border: solid 1px black;" colspan=1  class="td_field">
-HW_TRIG_SEL
+<td style="border: solid 1px black;" colspan=2  class="td_field">
+HW_TRIG_SEL[1:0]
+</td>
+<td >
+
 </td>
 <td >

@@ -3517,7 +3500,7 @@ HW_TRIG_SEL
 <li><b>
 HW_TRIG_SEL
 </b>[<i>read/write</i>]: Hardware trigger selection
-<br>0: internal (data threshold)<br>1: external (front panel trigger input)
+<br>00: internal (data threshold)<br>01: external (front panel trigger input)<br>10: trigger from timetag core<br>11: reserved (for WR message-based trigger)
 <li><b>
 HW_TRIG_POL
 </b>[<i>read/write</i>]: Hardware trigger polarity
@@ -3539,10 +3522,6 @@ INT_TRIG_TEST_EN
 </b>[<i>read/write</i>]: Enable internal trigger test mode
 <br>Test mode:<br>  ch1 = Channel 1 input(analogue)<br> ch2 = Channel input over threshold (digital)<br>  ch3 = Channel input over threshold filtered (digital)<br>  ch4 = Trigger (digital)
 <li><b>
-RESERVED
-</b>[<i>read/write</i>]: Reserved
-<br>Ignore on read, write with 0's
-<li><b>
 INT_TRIG_THRES_FILT
 </b>[<i>read/write</i>]: Internal trigger threshold glitch filter
 <br>Configures the internal trigger threshold glitch filter length.

--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
@@ -141,9 +141,10 @@ peripheral {

    field {
      name = "Hardware trigger selection";
-      description = "0: internal (data threshold)\n1: external (front panel trigger input)";
+      description = "00: internal (data threshold)\n01: external (front panel trigger input)\n10: trigger from timetag core\n11: reserved (for WR message-based trigger)";
      prefix = "hw_trig_sel";
-      type = BIT;
+      type = SLV;
+      size = 2;
      access_bus = READ_WRITE;
      access_dev = READ_ONLY;
      clock = "fs_clk_i";
@@ -200,15 +201,6 @@ peripheral {
      clock = "fs_clk_i";
    };

-    field {
-      name = "Reserved";
-      description = "Ignore on read, write with 0's";
-      prefix = "reserved";
-      type = BIT;
-      access_bus = READ_WRITE;
-      access_dev = READ_ONLY;
-    };
-
    field {
      name = "Internal trigger threshold glitch filter";
      description = "Configures the internal trigger threshold glitch filter length.";

--- a/hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
+++ b/hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
@@ -8,7 +8,7 @@
 --            : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-11-18
-- Last update: 2016-06-09
+-- Last update: 2016-06-15
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
 -- Description: Implements a UTC seconds counter and a 125MHz system clock
@@ -59,10 +59,11 @@ entity timetag_core is
    wr_tm_cycles_i     : in std_logic_vector(27 downto 0);

    -- Trigger time-tag output
-    trig_tag_o : out t_timetag;
+    trig_tag_o  : out t_timetag;
+    time_trig_o : out std_logic;

    -- Wishbone interface
-    wb_adr_i : in  std_logic_vector(3 downto 0);
+    wb_adr_i : in  std_logic_vector(4 downto 0);
    wb_dat_i : in  std_logic_vector(31 downto 0);
    wb_dat_o : out std_logic_vector(31 downto 0);
    wb_cyc_i : in  std_logic;
@@ -84,7 +85,7 @@ architecture rtl of timetag_core is
    port (
      rst_n_i                                    : in  std_logic;
      clk_sys_i                                  : in  std_logic;
-      wb_adr_i                                   : in  std_logic_vector(3 downto 0);
+      wb_adr_i                                   : in  std_logic_vector(4 downto 0);
      wb_dat_i                                   : in  std_logic_vector(31 downto 0);
      wb_dat_o                                   : out std_logic_vector(31 downto 0);
      wb_cyc_i                                   : in  std_logic;
@@ -102,6 +103,9 @@ architecture rtl of timetag_core is
      timetag_core_coarse_o                      : out std_logic_vector(27 downto 0);
      timetag_core_coarse_i                      : in  std_logic_vector(27 downto 0);
      timetag_core_coarse_load_o                 : out std_logic;
+      timetag_core_time_trig_seconds_upper_o     : out std_logic_vector(7 downto 0);
+      timetag_core_time_trig_seconds_lower_o     : out std_logic_vector(31 downto 0);
+      timetag_core_time_trig_coarse_o            : out std_logic_vector(27 downto 0);
      timetag_core_trig_tag_seconds_upper_i      : in  std_logic_vector(7 downto 0);
      timetag_core_trig_tag_seconds_lower_i      : in  std_logic_vector(31 downto 0);
      timetag_core_trig_tag_coarse_i             : in  std_logic_vector(27 downto 0);
@@ -127,6 +131,7 @@ architecture rtl of timetag_core is
  signal timetag_coarse_cnt         : unsigned(27 downto 0);
  signal timetag_coarse_load_value  : std_logic_vector(27 downto 0);
  signal timetag_coarse_load_en     : std_logic;
+  signal time_trigger               : t_timetag;
  signal trig_tag                   : t_timetag;
  signal acq_start_tag              : t_timetag;
  signal acq_stop_tag               : t_timetag;
@@ -166,6 +171,9 @@ begin
      timetag_core_coarse_o                      => timetag_coarse_load_value,
      timetag_core_coarse_i                      => timetag_coarse,
      timetag_core_coarse_load_o                 => timetag_coarse_load_en,
+      timetag_core_time_trig_seconds_upper_o     => time_trigger.seconds(39 downto 32),
+      timetag_core_time_trig_seconds_lower_o     => time_trigger.seconds(31 downto 0),
+      timetag_core_time_trig_coarse_o            => time_trigger.coarse,
      timetag_core_trig_tag_seconds_upper_i      => trig_tag.seconds(39 downto 32),
      timetag_core_trig_tag_seconds_lower_i      => trig_tag.seconds(31 downto 0),
      timetag_core_trig_tag_coarse_i             => trig_tag.coarse,
@@ -199,7 +207,7 @@ begin
    end if;
  end process p_timetag_seconds_cnt;

-  timetag_seconds <= wr_tm_tai_i when wr_enabled_i = '1' else std_logic_vector(timetag_seconds_cnt);
+  timetag_seconds <= wr_tm_tai_i when wr_enabled = '1' else std_logic_vector(timetag_seconds_cnt);

  ------------------------------------------------------------------------------
  -- UTC 125MHz clock ticks counter
@@ -223,7 +231,14 @@ begin
    end if;
  end process p_timetag_coarse_cnt;

-  timetag_coarse <= wr_tm_cycles_i when wr_enabled_i = '1' else std_logic_vector(timetag_coarse_cnt);
+  timetag_coarse <= wr_tm_cycles_i when wr_enabled = '1' else std_logic_vector(timetag_coarse_cnt);
+  
+  ------------------------------------------------------------------------------
+  -- Time trigger signal generation
+  ------------------------------------------------------------------------------
+  time_trig_o <= '1' when ((time_trigger.seconds = timetag_seconds) and
+                           (time_trigger.coarse = timetag_coarse))
+                 else '0';

  ------------------------------------------------------------------------------
  -- Last trigger event time-tag

--- a/hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
+++ b/hdl/ip_cores/timetag_core/rtl/timetag_core_pkg.vhd
@@ -8,7 +8,7 @@
 --            : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2013-07-05
-- Last update: 2016-06-09
+-- Last update: 2016-06-15
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
 -- Description: Package for timetag core
@@ -66,7 +66,8 @@ package timetag_core_pkg is
      wr_tm_tai_i        : in  std_logic_vector(39 downto 0);
      wr_tm_cycles_i     : in  std_logic_vector(27 downto 0);
      trig_tag_o         : out t_timetag;
-      wb_adr_i           : in  std_logic_vector(3 downto 0);
+      time_trig_o        : out std_logic;
+      wb_adr_i           : in  std_logic_vector(4 downto 0);
      wb_dat_i           : in  std_logic_vector(31 downto 0);
      wb_dat_o           : out std_logic_vector(31 downto 0);
      wb_cyc_i           : in  std_logic;

--- a/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd
+++ b/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd
--- a/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h
+++ b/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h
@@ -3,7 +3,7 @@

  * File           : timetag_core_regs.h
  * Author         : auto-generated by wbgen2 from timetag_core_regs.wb
-  * Created        : Wed Jun  8 10:54:43 2016
+  * Created        : Wed Jun 15 15:54:40 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
@@ -37,6 +37,12 @@

 /* definitions for register: Timetag coarse time register, system clock ticks (125MHz) */

+/* definitions for register: Time trigger seconds register (upper) */
+
+/* definitions for register: Timetag seconds register (lower) */
+
+/* definitions for register: Timetag coarse time register, system clock ticks (125MHz) */
+
 /* definitions for register: Trigger time-tag seconds register (upper) */

 /* definitions for register: Trigger time-tag seconds register (lower) */
@@ -68,29 +74,35 @@ PACKED struct TIMETAG_CORE_WB {
  uint32_t SECONDS_LOWER;
  /* [0x8]: REG Timetag coarse time register, system clock ticks (125MHz) */
  uint32_t COARSE;
-  /* [0xc]: REG Trigger time-tag seconds register (upper) */
+  /* [0xc]: REG Time trigger seconds register (upper) */
+  uint32_t TIME_TRIG_SECONDS_UPPER;
+  /* [0x10]: REG Timetag seconds register (lower) */
+  uint32_t TIME_TRIG_SECONDS_LOWER;
+  /* [0x14]: REG Timetag coarse time register, system clock ticks (125MHz) */
+  uint32_t TIME_TRIG_COARSE;
+  /* [0x18]: REG Trigger time-tag seconds register (upper) */
  uint32_t TRIG_TAG_SECONDS_UPPER;
-  /* [0x10]: REG Trigger time-tag seconds register (lower) */
+  /* [0x1c]: REG Trigger time-tag seconds register (lower) */
  uint32_t TRIG_TAG_SECONDS_LOWER;
-  /* [0x14]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
+  /* [0x20]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
  uint32_t TRIG_TAG_COARSE;
-  /* [0x18]: REG Acquisition start time-tag seconds register (upper) */
+  /* [0x24]: REG Acquisition start time-tag seconds register (upper) */
  uint32_t ACQ_START_TAG_SECONDS_UPPER;
-  /* [0x1c]: REG Acquisition start time-tag seconds register (lower) */
+  /* [0x28]: REG Acquisition start time-tag seconds register (lower) */
  uint32_t ACQ_START_TAG_SECONDS_LOWER;
-  /* [0x20]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
+  /* [0x2c]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
  uint32_t ACQ_START_TAG_COARSE;
-  /* [0x24]: REG Acquisition stop time-tag seconds register (upper) */
+  /* [0x30]: REG Acquisition stop time-tag seconds register (upper) */
  uint32_t ACQ_STOP_TAG_SECONDS_UPPER;
-  /* [0x28]: REG Acquisition stop time-tag seconds register (lower) */
+  /* [0x34]: REG Acquisition stop time-tag seconds register (lower) */
  uint32_t ACQ_STOP_TAG_SECONDS_LOWER;
-  /* [0x2c]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
+  /* [0x38]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
  uint32_t ACQ_STOP_TAG_COARSE;
-  /* [0x30]: REG Acquisition end time-tag seconds register (upper) */
+  /* [0x3c]: REG Acquisition end time-tag seconds register (upper) */
  uint32_t ACQ_END_TAG_SECONDS_UPPER;
-  /* [0x34]: REG Acquisition end time-tag seconds register (lower) */
+  /* [0x40]: REG Acquisition end time-tag seconds register (lower) */
  uint32_t ACQ_END_TAG_SECONDS_LOWER;
-  /* [0x38]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
+  /* [0x44]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
  uint32_t ACQ_END_TAG_COARSE;
 };


--- a/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.htm
+++ b/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.htm
--- a/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.wb
+++ b/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.wb