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FMC ADC 100M 14b 4cha - Gateware
Commit 6f31510f authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: complete rework of trigger logic and SPEC testbench update. 

The new trigger logic allows for logical OR'ing of all trigger sources, by means
of the new "trigger enable" register. For each trigger the "mask" of the trigger source(s)
is reflected in the "trigger status" register and it is also stored in the data stream
together with the trigger time tag.

Furthermore, the previously used glitch filter has been removed, in favor of a comparator module
with optional hysteresis. This approach makes the internal trigger logic more responsible,
versatile and intuitive to the user.

The SPEC testbench has been updated to test these new features. It is still far from perfect though,
see also issue #1726.
parent edfa6441
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doc/manual/fmc_adc_100Ms_csr.tex
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hdl/adc/rtl/fmc_adc_100Ms_core.vhd
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hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
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......@@ -9,7 +9,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2012-11-16
-- Last update: 2016-06-15
-- Last update: 2018-01-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for FMC ADC 100Ms/s core.
......@@ -60,7 +60,7 @@ package fmc_adc_100Ms_core_pkg is
sys_rst_n_i : in std_logic;
-- CSR wishbone interface
wb_csr_adr_i : in std_logic_vector(5 downto 0);
wb_csr_adr_i : in std_logic_vector(7 downto 0);
wb_csr_dat_i : in std_logic_vector(31 downto 0);
wb_csr_dat_o : out std_logic_vector(31 downto 0);
wb_csr_cyc_i : in std_logic;
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
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hdl/adc/rtl/fmc_adc_mezzanine.vhd
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......@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-05-07
-- Last update: 2016-06-15
-- Last update: 2018-01-24
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: The FMC ADC mezzanine is wrapper around the fmc-adc-100ms core
......@@ -166,10 +166,10 @@ architecture rtl of fmc_adc_mezzanine is
constant c_WB_MASTER : integer := 0;
-- Wishbone slave(s)
constant c_WB_SLAVE_FMC_SYS_I2C : integer := 0; -- Mezzanine system I2C interface (EEPROM)
constant c_WB_SLAVE_FMC_SPI : integer := 1; -- Mezzanine SPI interface
constant c_WB_SLAVE_FMC_I2C : integer := 2; -- Mezzanine I2C controller
constant c_WB_SLAVE_FMC_ADC : integer := 3; -- Mezzanine ADC core
constant c_WB_SLAVE_FMC_ADC : integer := 0; -- Mezzanine ADC core
constant c_WB_SLAVE_FMC_SYS_I2C : integer := 1; -- Mezzanine system I2C interface (EEPROM)
constant c_WB_SLAVE_FMC_SPI : integer := 2; -- Mezzanine SPI interface
constant c_WB_SLAVE_FMC_I2C : integer := 3; -- Mezzanine I2C controller
constant c_WB_SLAVE_FMC_ONEWIRE : integer := 4; -- Mezzanine onewire interface
constant c_WB_SLAVE_FMC_EIC : integer := 5; -- Mezzanine interrupt controller
constant c_WB_SLAVE_TIMETAG : integer := 6; -- Mezzanine timetag core
......@@ -183,7 +183,7 @@ architecture rtl of fmc_adc_mezzanine is
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"00000000000000FF",
addr_last => x"00000000000003FF",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000608",
......@@ -229,13 +229,13 @@ architecture rtl of fmc_adc_mezzanine is
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(
0 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_spi_sdb, x"00001100"),
2 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001200"),
3 => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001300"),
4 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001400"),
5 => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00001500"),
6 => f_sdb_embed_device(c_wb_timetag_sdb, x"00001600")
0 => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001400"),
2 => f_sdb_embed_device(c_xwb_spi_sdb, x"00001500"),
3 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001600"),
4 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001700"),
5 => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00001800"),
6 => f_sdb_embed_device(c_wb_timetag_sdb, x"00001900")
);
......@@ -354,12 +354,12 @@ begin
slave_o => cnx_master_in(c_WB_SLAVE_FMC_SYS_I2C),
desc_o => open,
scl_pad_i => sys_scl_in,
scl_pad_o => sys_scl_out,
scl_padoen_o => sys_scl_oe_n,
sda_pad_i => sys_sda_in,
sda_pad_o => sys_sda_out,
sda_padoen_o => sys_sda_oe_n
scl_pad_i(0) => sys_scl_in,
scl_pad_o(0) => sys_scl_out,
scl_padoen_o(0) => sys_scl_oe_n,
sda_pad_i(0) => sys_sda_in,
sda_pad_o(0) => sys_sda_out,
sda_padoen_o(0) => sys_sda_oe_n
);
-- Tri-state buffer for SDA and SCL
......@@ -431,12 +431,12 @@ begin
slave_o => cnx_master_in(c_WB_SLAVE_FMC_I2C),
desc_o => open,
scl_pad_i => si570_scl_in,
scl_pad_o => si570_scl_out,
scl_padoen_o => si570_scl_oe_n,
sda_pad_i => si570_sda_in,
sda_pad_o => si570_sda_out,
sda_padoen_o => si570_sda_oe_n
scl_pad_i(0) => si570_scl_in,
scl_pad_o(0) => si570_scl_out,
scl_padoen_o(0) => si570_scl_oe_n,
sda_pad_i(0) => si570_sda_in,
sda_pad_o(0) => si570_sda_out,
sda_padoen_o(0) => si570_sda_oe_n
);
-- Tri-state buffer for SDA and SCL
......@@ -462,7 +462,7 @@ begin
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(7 downto 2), -- cnx_master_out.adr is byte address
wb_csr_adr_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).adr(9 downto 2), -- cnx_master_out.adr is byte address
wb_csr_dat_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_dat_o => cnx_master_in(c_WB_SLAVE_FMC_ADC).dat,
wb_csr_cyc_i => cnx_master_out(c_WB_SLAVE_FMC_ADC).cyc,
......
hdl/adc/wb_gen/Makefile
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WBGEN2=$(shell which wbgen2)
RTL=../rtl/
SIM=../../spec/testbench/include/
TEX=../../../doc/manual/
all: fmc_adc_100Ms_csr fmc_adc_eic
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h -K $(SIM)$@.v $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
fmc_adc_eic:
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
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hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
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hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
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general-cores @ c3cfcfdd
Subproject commit c26ee857158e4a65fd9d2add8b63fcb6fb4691ea
Subproject commit c3cfcfdd48308aeb787fde006cd27f15097f3ed1
hdl/spec/testbench/include/fmc_adc_100Ms_csr.v 0 → 100644
View file @ 6f31510f
`define ADDR_FMC_ADC_100MS_CSR_CTL 10'h0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD_OFFSET 0
`define FMC_ADC_100MS_CSR_CTL_FSM_CMD 32'h00000003
`define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE_OFFSET 2
`define FMC_ADC_100MS_CSR_CTL_FMC_CLK_OE 32'h00000004
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N_OFFSET 3
`define FMC_ADC_100MS_CSR_CTL_OFFSET_DAC_CLR_N 32'h00000008
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP_OFFSET 4
`define FMC_ADC_100MS_CSR_CTL_MAN_BITSLIP 32'h00000010
`define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN_OFFSET 5
`define FMC_ADC_100MS_CSR_CTL_TEST_DATA_EN 32'h00000020
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED_OFFSET 6
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED 32'h00000040
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED_OFFSET 7
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED 32'h00000080
`define ADDR_FMC_ADC_100MS_CSR_STA 10'h4
`define FMC_ADC_100MS_CSR_STA_FSM_OFFSET 0
`define FMC_ADC_100MS_CSR_STA_FSM 32'h00000007
`define FMC_ADC_100MS_CSR_STA_SERDES_PLL_OFFSET 3
`define FMC_ADC_100MS_CSR_STA_SERDES_PLL 32'h00000008
`define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED_OFFSET 4
`define FMC_ADC_100MS_CSR_STA_SERDES_SYNCED 32'h00000010
`define FMC_ADC_100MS_CSR_STA_ACQ_CFG_OFFSET 5
`define FMC_ADC_100MS_CSR_STA_ACQ_CFG 32'h00000020
`define ADDR_FMC_ADC_100MS_CSR_TRIG_STAT 10'h8
`define FMC_ADC_100MS_CSR_TRIG_STAT_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_STAT_EXT 32'h00000001
`define FMC_ADC_100MS_CSR_TRIG_STAT_SW_OFFSET 1
`define FMC_ADC_100MS_CSR_TRIG_STAT_SW 32'h00000002
`define FMC_ADC_100MS_CSR_TRIG_STAT_TIME_OFFSET 4
`define FMC_ADC_100MS_CSR_TRIG_STAT_TIME 32'h00000010
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH2_OFFSET 9
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH2 32'h00000200
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH3_OFFSET 10
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_STAT_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_EN 10'hc
`define FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_EN_EXT 32'h00000001
`define FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET 1
`define FMC_ADC_100MS_CSR_TRIG_EN_SW 32'h00000002
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET 4
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME 32'h00000010
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_EN_CH2_OFFSET 9
`define FMC_ADC_100MS_CSR_TRIG_EN_CH2 32'h00000200
`define FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET 10
`define FMC_ADC_100MS_CSR_TRIG_EN_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POL 10'h10
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT 32'h00000001
`define FMC_ADC_100MS_CSR_TRIG_POL_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_POL_CH1 32'h00000100
`define FMC_ADC_100MS_CSR_TRIG_POL_CH2_OFFSET 9
`define FMC_ADC_100MS_CSR_TRIG_POL_CH2 32'h00000200
`define FMC_ADC_100MS_CSR_TRIG_POL_CH3_OFFSET 10
`define FMC_ADC_100MS_CSR_TRIG_POL_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_DLY 10'h14
`define ADDR_FMC_ADC_100MS_CSR_SW_TRIG 10'h18
`define ADDR_FMC_ADC_100MS_CSR_SHOTS 10'h1c
`define FMC_ADC_100MS_CSR_SHOTS_NB_OFFSET 0
`define FMC_ADC_100MS_CSR_SHOTS_NB 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_MULTI_DEPTH 10'h20
`define ADDR_FMC_ADC_100MS_CSR_SHOTS_CNT 10'h24
`define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_SHOTS_CNT_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POS 10'h28
`define ADDR_FMC_ADC_100MS_CSR_FS_FREQ 10'h2c
`define ADDR_FMC_ADC_100MS_CSR_SR 10'h30
`define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE_OFFSET 0
`define FMC_ADC_100MS_CSR_SR_UNDERSAMPLE 32'hffffffff
`define ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES 10'h34
`define ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES 10'h38
`define ADDR_FMC_ADC_100MS_CSR_SAMPLES_CNT 10'h3c
`define ADDR_FMC_ADC_100MS_CSR_CH1_CTL 10'h80
`define FMC_ADC_100MS_CSR_CH1_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH1_STA 10'h84
`define FMC_ADC_100MS_CSR_CH1_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_GAIN 10'h88
`define FMC_ADC_100MS_CSR_CH1_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_OFFSET 10'h8c
`define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH1_SAT 10'h90
`define FMC_ADC_100MS_CSR_CH1_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_THRES 10'h94
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH2_CTL 10'h100
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH2_STA 10'h104
`define FMC_ADC_100MS_CSR_CH2_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_GAIN 10'h108
`define FMC_ADC_100MS_CSR_CH2_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_OFFSET 10'h10c
`define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH2_SAT 10'h110
`define FMC_ADC_100MS_CSR_CH2_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES 10'h114
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH3_CTL 10'h180
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH3_STA 10'h184
`define FMC_ADC_100MS_CSR_CH3_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_GAIN 10'h188
`define FMC_ADC_100MS_CSR_CH3_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_OFFSET 10'h18c
`define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH3_SAT 10'h190
`define FMC_ADC_100MS_CSR_CH3_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES 10'h194
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH4_CTL 10'h200
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR 32'h0000007f
`define ADDR_FMC_ADC_100MS_CSR_CH4_STA 10'h204
`define FMC_ADC_100MS_CSR_CH4_STA_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_STA_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_GAIN 10'h208
`define FMC_ADC_100MS_CSR_CH4_GAIN_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_GAIN_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_OFFSET 10'h20c
`define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_OFFSET_VAL 32'h0000ffff
`define ADDR_FMC_ADC_100MS_CSR_CH4_SAT 10'h210
`define FMC_ADC_100MS_CSR_CH4_SAT_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_SAT_VAL 32'h00007fff
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES 10'h214
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST 32'hffff0000
hdl/spec/testbench/top/main.sv
View file @ 6f31510f
......@@ -3,8 +3,10 @@
`include "gn4124_bfm.svh"
`include "if_wb_master.svh"
`include "if_wb_slave.svh"
`include "fmc_adc_100Ms_csr.v"
`define CSR_BASE 'h3000
`define TAG_BASE 'h3900
module main;
reg clk_125m_pllref_p = 0;
......@@ -12,8 +14,13 @@ module main;
reg rst_n = 0;
reg adc0_dco = 0;
reg adc0_fr = 0;
reg adc0_fr = 1'b0;
reg ext_trig = 1'b0;
reg adc_data_dir = 1'b0;
reg[3:0] adc0_dat_odd = 4'h0;
reg[3:0] adc0_dat_even = 4'h0;
reg signed [13:0] adc0_data = 0;
always #1.25ns adc0_dco <= ~adc0_dco;
always #4ns clk_125m_pllref_p <= ~clk_125m_pllref_p;
......@@ -39,16 +46,16 @@ module main;
) DUT (
.clk_125m_pllref_p_i(clk_125m_pllref_p),
.clk_125m_pllref_n_i(clk_125m_pllref_n),
.adc0_ext_trigger_p_i(1'b0),
.adc0_ext_trigger_n_i(1'b1),
.adc0_ext_trigger_p_i(ext_trig),
.adc0_ext_trigger_n_i(~ext_trig),
.adc0_dco_p_i(adc0_dco),
.adc0_dco_n_i(~adc0_dco),
.adc0_fr_p_i(~adc0_fr),
.adc0_fr_n_i(adc0_fr),
.adc0_outa_p_i(4'h0),
.adc0_outa_n_i(4'hf),
.adc0_outb_p_i(4'h0),
.adc0_outb_n_i(4'hf),
.adc0_outa_p_i(adc0_dat_odd),
.adc0_outa_n_i(~adc0_dat_odd),
.adc0_outb_p_i(adc0_dat_even),
.adc0_outb_n_i(~adc0_dat_even),
.DDR3_CAS_N (ddr_cas_n),
.DDR3_CK_N(ddr_ck_n),
.DDR3_CK_P (ddr_ck_p),
......@@ -97,17 +104,55 @@ module main;
int adc_div = 0;
always@(posedge adc0_dco)
if(adc_div==1) begin
adc0_fr <= ~adc0_fr;
adc_div <= 0;
end
else begin
adc_div <= adc_div + 1;
always@(negedge adc0_dco)
begin
#625ps;
if(adc_div == 1) begin
adc0_fr <= ~adc0_fr;
adc_div <= 0;
end
else begin
adc_div <= adc_div + 1;
end
end
always@(posedge adc0_fr)
begin
if ((adc0_data > 400) || (adc0_data < -400)) begin
adc_data_dir = ~adc_data_dir;
end
if (adc_data_dir == 0) begin
adc0_data = adc0_data + 8;
end
else begin
adc0_data = adc0_data - 8;
end
adc0_dat_odd = {4{adc0_data[13]}};
adc0_dat_even = {4{adc0_data[12]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[11]}};
adc0_dat_even = {4{adc0_data[10]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[9]}};
adc0_dat_even = {4{adc0_data[8]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[7]}};
adc0_dat_even = {4{adc0_data[6]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[5]}};
adc0_dat_even = {4{adc0_data[4]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[3]}};
adc0_dat_even = {4{adc0_data[2]}};
#1250ps;
adc0_dat_odd = {4{adc0_data[1]}};
adc0_dat_even = {4{adc0_data[0]}};
#1250ps;
adc0_dat_odd = {4{1'b0}};
adc0_dat_even = {4{1'b0}};
end
wire[2:0] acq_fsm_state = DUT.cmp_fmc_adc_mezzanine_0.cmp_fmc_adc_100Ms_core.acq_fsm_state;
initial begin
CBusAccessor acc;
......@@ -121,59 +166,133 @@ module main;
//@(posedge DUT.sys_clk_pll_locked);
#15us;
#5us;
acc.read(0, val);
$display("ID: %x", val);
acc.read('h3304, val); // status
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val); // status
$display("STATUS: %x", val);
acc.write('h3308, 'h00000010); // trigger cfg: enable sw trigger
acc.write('h3328, 'h00000000); // #pre-samples
acc.write('h332C, 'h00000010); // #post-samples
acc.write('h3314, 'h00000001); // #nshots: single-shot acq
acc.read('h3304, val); // status
// FMC-ADC core general configuration
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000001);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000001);
// FMC-ADC core channel configuration
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_GAIN, 'h00008000);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_SAT, 'h00007fff);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_SAT, 'h00007fff);
// FMC-ADC core trigger configuration
val = (16'h100 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET) |
(16'h300 << `FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES, val);
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
$display("STATUS: %x", val);
#5us;
acc.write('h3600, 'h00000032); // timetag core seconds high
acc.write('h3604, 'h00005a34); // timetag core seconds low
acc.write('h3608, 'h00000000); // timetag core ticks
acc.write('h3300, 'h00000001); // FSM start
acc.write(`TAG_BASE + 0, 'h00000032); // timetag core seconds high
acc.write(`TAG_BASE + 4, 'h00005a34); // timetag core seconds low
acc.write(`TAG_BASE + 8, 'h00000000); // timetag core ticks
wait (acq_fsm_state == 1);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#1us;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFF); // soft trigger
wait (acq_fsm_state == 1);
#1us;
acc.write('h3310, 'hFFFFFFFF); // soft trigger
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h00000003); // #nshots: 3x multi-shot acq
#2us;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
acc.write('h3314, 'h00000003); // #nshots: 3x multi-shot acq
#1us;
acc.write('h3300, 'h00000001); // FSM start
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFE); // soft trigger
#1us;
acc.write('h3310, 'hFFFFFFFE); // soft trigger
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFD); // soft trigger
#1us;
acc.write('h3310, 'hFFFFFFFD); // soft trigger
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFC); // soft trigger
wait (acq_fsm_state == 1);
#1us;
acc.write('h3310, 'hFFFFFFFC); // soft trigger
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000008);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#1us;
#2us;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFE); // soft trigger
#1us;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SW_TRIG, 'hFFFFFFFD); // soft trigger
wait (acq_fsm_state == 1);
#1us;
// set time trigger
acc.write(`TAG_BASE + 'h0c, 'h00000032); // timetag core seconds high
acc.write(`TAG_BASE + 'h10, 'h00005a34); // timetag core seconds low
acc.write(`TAG_BASE + 'h14, 'h00000e00); // timetag core ticks
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_PRE_SAMPLES, 'h00000010);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000080);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000002);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CTL, 'h00000001); // FSM start
#5us;
ext_trig <= 1'b1;
#100ns;
ext_trig <= 1'b0;
wait (acq_fsm_state == 1);
#1us;
// DMA transfer
acc.write('h100C, 'h00001000); // host addr
acc.write('h1010, 'h00000000);
acc.write('h1014, 'h00001000); // len
acc.write('h1014, 'h00000100); // len
acc.write('h1018, 'h00000000); // next
acc.write('h101C, 'h00000000);
......@@ -184,7 +303,7 @@ module main;
acc.write('h1000, 'h00000001); // xfer start
acc.read('h3304, val); // status
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
$display("STATUS: %x", val);
end
......
hdl/spec/testbench/top/wave.do
View file @ 6f31510f
......@@ -122,6 +122,7 @@ add wave -noupdate -group Top /main/DUT/adc0_dco_p_i
add wave -noupdate -group Top /main/DUT/adc0_dco_n_i
add wave -noupdate -group Top /main/DUT/adc0_fr_p_i
add wave -noupdate -group Top /main/DUT/adc0_fr_n_i
add wave -noupdate -group Top /main/adc0_data
add wave -noupdate -group Top /main/DUT/adc0_outa_p_i
add wave -noupdate -group Top /main/DUT/adc0_outa_n_i
add wave -noupdate -group Top /main/DUT/adc0_outb_p_i
......@@ -216,8 +217,11 @@ add wave -noupdate -group Top /main/DUT/led_pwm_cnt
add wave -noupdate -group Top /main/DUT/led_pwm
add wave -noupdate -radix hexadecimal -group MEZ /main/DUT/cmp_fmc_adc_mezzanine_0/cnx_*
add wave -noupdate -radix hexadecimal -group ADC -group SERDES /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/cmp_adc_serdes/*
add wave -noupdate -radix hexadecimal -group ADC -group CSR /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/csr_regin
add wave -noupdate -radix hexadecimal -group ADC -group CSR /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/csr_regout
add wave -noupdate -radix hexadecimal -group ADC -group CSR /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_*
add wave -noupdate -radix hexadecimal -group ADC -group offset0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/l_offset_gain_calibr(0)/cmp_offset_gain_calibr/*
add wave -noupdate -radix hexadecimal -group ADC -group comparator0 /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/g_int_trig(1)/cmp_gc_comparator/*
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_clk_i
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sys_rst_n_i
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_csr_adr_i
......@@ -273,6 +277,9 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d1
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d2
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/data_calibr_out_d3
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_out_fr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_auto_bitslip
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_man_bitslip
......@@ -280,19 +287,26 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/serdes_synced
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/bitslip_sreg
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_a
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_p
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_n
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_data
add wave -noupdate -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_over_thres
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig_t
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig_sel
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/hw_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_t
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_ch_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_empty
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_full
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_rd
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_wr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_din
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_dout
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_storage
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_d
......@@ -307,6 +321,9 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_wr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_rd
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_valid
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/wb_ddr_fifo*
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram0*
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/dpram1*
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/gain_calibr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/offset_calibr
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/acq_fsm_current_state
......
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