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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
71387ac4
Commit
71387ac4
authored
Nov 27, 2018
by
Dimitris Lampridis
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sim: introduce new svec_ref_design testbench
parent
d1059605
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.gitignore
hdl/testbench/svec_ref_design/.gitignore
+6
-0
Manifest.py
hdl/testbench/svec_ref_design/Manifest.py
+36
-0
main.sv
hdl/testbench/svec_ref_design/main.sv
+362
-0
run.do
hdl/testbench/svec_ref_design/run.do
+12
-0
run_ci.do
hdl/testbench/svec_ref_design/run_ci.do
+6
-0
synthesis_descriptor.vhd
hdl/testbench/svec_ref_design/synthesis_descriptor.vhd
+31
-0
No files found.
hdl/testbench/svec_ref_design/.gitignore
0 → 100644
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71387ac4
Makefile
work/
transcript
vsim.wlf
NullFile
modelsim.ini
hdl/testbench/svec_ref_design/Manifest.py
0 → 100644
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71387ac4
board
=
"svec"
sim_tool
=
"modelsim"
top_module
=
"main"
action
=
"simulation"
target
=
"xilinx"
syn_device
=
"xc6slx150t"
vcom_opt
=
"-93 -mixedsvvh"
fetchto
=
"../../ip_cores"
include_dirs
=
[
"../include"
,
fetchto
+
"/general-cores/sim/"
,
fetchto
+
"/general-cores/modules/wishbone/wb_spi/"
,
fetchto
+
"/vme64x-core/hdl/sim/vme64x_bfm/"
,
]
files
=
[
"main.sv"
,
"synthesis_descriptor.vhd"
,
]
modules
=
{
"local"
:
[
"../../top/svec_ref_design"
,
],
"git"
:
[
"git://ohwr.org/hdl-core-lib/general-cores.git"
,
"git://ohwr.org/hdl-core-lib/wr-cores.git"
,
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git"
,
"git://ohwr.org/hdl-core-lib/vme64x-core.git"
,
],
}
ctrls
=
[
"bank4_64b_32b"
,
"bank5_64b_32b"
]
hdl/testbench/svec_ref_design/main.sv
0 → 100644
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71387ac4
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hdl/testbench/svec_ref_design/run.do
0 → 100644
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71387ac4
vsim -quiet -t 10fs -L unisim work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
wave zoomfull
hdl/testbench/svec_ref_design/run_ci.do
0 → 100644
View file @
71387ac4
vsim -quiet -t 10fs -L unisim work.main
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run -all
hdl/testbench/svec_ref_design/synthesis_descriptor.vhd
0 → 100644
View file @
71387ac4
--------------------------------------------------------------------------------
-- SDB meta information for svec_ref_fmc_adc_100Ms_wr.xise.
--
-- This file was automatically generated by ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl on:
-- Thursday, November 15 2018
--
-- ../../ip_cores/general-cores/tools/sdb_desc_gen.tcl is part of OHWR general-cores:
-- https://www.ohwr.org/projects/general-cores/wiki
--
-- For more information on SDB meta information, see also:
-- https://www.ohwr.org/projects/sdb/wiki
--------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
work
.
wishbone_pkg
.
all
;
package
synthesis_descriptor
is
constant
c_sdb_synthesis_info
:
t_sdb_synthesis
:
=
(
syn_module_name
=>
"svec_ref_fmc_adc"
,
syn_commit_id
=>
"f98f833b0a46c659dd2c68d6bfeb6d9*"
,
syn_tool_name
=>
"ISE "
,
syn_tool_version
=>
x"00000147"
,
syn_date
=>
x"20181115"
,
syn_username
=>
"Dimitris Lampri"
);
constant
c_sdb_repo_url
:
t_sdb_repo_url
:
=
(
repo_url
=>
"ssh://git@gitlab.cern.ch:7999/dlamprid/fmc-adc-100m14b4cha-gw.g"
);
end
package
synthesis_descriptor
;
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