hdl: migrate all wbgen registers to records

77214b2e · Dimitris Lampridis · 6dee5c3b · 77214b2e · 77214b2e · 77214b2e
Commit 77214b2e authored Jun 16, 2016 by Dimitris Lampridis
30 changed files
--- a/hdl/adc/rtl/Manifest.py
+++ b/hdl/adc/rtl/Manifest.py
@@ -4,6 +4,7 @@ files = [
    "fmc_adc_100Ms_core.vhd",
    "fmc_adc_100Ms_core_pkg.vhd",
    "fmc_adc_100Ms_csr.vhd",
+    "fmc_adc_100Ms_csr_wbgen2_pkg.vhd",
    "fmc_adc_eic.vhd",
    "offset_gain_s.vhd",
    "var_sat_s.vhd"]
--- a/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_core.vhd
--- a/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
--- a/hdl/adc/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
+++ b/hdl/adc/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for FMC ADC 100MS/s core registers
+---------------------------------------------------------------------------------------
+-- File           : ../rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
+-- Created        : Thu Jun 16 17:04:12 2016
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package fmc_adc_100ms_csr_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_fmc_adc_100ms_csr_in_registers is record
+    sta_fsm_i                                : std_logic_vector(2 downto 0);
+    sta_serdes_pll_i                         : std_logic;
+    sta_serdes_synced_i                      : std_logic;
+    sta_acq_cfg_i                            : std_logic;
+    shots_cnt_val_i                          : std_logic_vector(15 downto 0);
+    trig_pos_i                               : std_logic_vector(31 downto 0);
+    fs_freq_i                                : std_logic_vector(31 downto 0);
+    samples_cnt_i                            : std_logic_vector(31 downto 0);
+    ch1_sta_val_i                            : std_logic_vector(15 downto 0);
+    ch2_sta_val_i                            : std_logic_vector(15 downto 0);
+    ch3_sta_val_i                            : std_logic_vector(15 downto 0);
+    ch4_sta_val_i                            : std_logic_vector(15 downto 0);
+    multi_depth_i                            : std_logic_vector(31 downto 0);
+    end record;
+  
+  constant c_fmc_adc_100ms_csr_in_registers_init_value: t_fmc_adc_100ms_csr_in_registers := (
+    sta_fsm_i => (others => '0'),
+    sta_serdes_pll_i => '0',
+    sta_serdes_synced_i => '0',
+    sta_acq_cfg_i => '0',
+    shots_cnt_val_i => (others => '0'),
+    trig_pos_i => (others => '0'),
+    fs_freq_i => (others => '0'),
+    samples_cnt_i => (others => '0'),
+    ch1_sta_val_i => (others => '0'),
+    ch2_sta_val_i => (others => '0'),
+    ch3_sta_val_i => (others => '0'),
+    ch4_sta_val_i => (others => '0'),
+    multi_depth_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_fmc_adc_100ms_csr_out_registers is record
+      ctl_fsm_cmd_o                            : std_logic_vector(1 downto 0);
+      ctl_fsm_cmd_wr_o                         : std_logic;
+      ctl_fmc_clk_oe_o                         : std_logic;
+      ctl_offset_dac_clr_n_o                   : std_logic;
+      ctl_man_bitslip_o                        : std_logic;
+      ctl_test_data_en_o                       : std_logic;
+      ctl_trig_led_o                           : std_logic;
+      ctl_acq_led_o                            : std_logic;
+      trig_cfg_hw_trig_sel_o                   : std_logic_vector(1 downto 0);
+      trig_cfg_hw_trig_pol_o                   : std_logic;
+      trig_cfg_hw_trig_en_o                    : std_logic;
+      trig_cfg_sw_trig_en_o                    : std_logic;
+      trig_cfg_int_trig_sel_o                  : std_logic_vector(1 downto 0);
+      trig_cfg_int_trig_test_en_o              : std_logic;
+      trig_cfg_int_trig_thres_filt_o           : std_logic_vector(7 downto 0);
+      trig_cfg_int_trig_thres_o                : std_logic_vector(15 downto 0);
+      trig_dly_o                               : std_logic_vector(31 downto 0);
+      sw_trig_o                                : std_logic_vector(31 downto 0);
+      sw_trig_wr_o                             : std_logic;
+      shots_nb_o                               : std_logic_vector(15 downto 0);
+      sr_undersample_o                         : std_logic_vector(31 downto 0);
+      pre_samples_o                            : std_logic_vector(31 downto 0);
+      post_samples_o                           : std_logic_vector(31 downto 0);
+      ch1_ctl_ssr_o                            : std_logic_vector(6 downto 0);
+      ch1_gain_val_o                           : std_logic_vector(15 downto 0);
+      ch1_offset_val_o                         : std_logic_vector(15 downto 0);
+      ch1_sat_val_o                            : std_logic_vector(14 downto 0);
+      ch2_ctl_ssr_o                            : std_logic_vector(6 downto 0);
+      ch2_gain_val_o                           : std_logic_vector(15 downto 0);
+      ch2_offset_val_o                         : std_logic_vector(15 downto 0);
+      ch2_sat_val_o                            : std_logic_vector(14 downto 0);
+      ch3_ctl_ssr_o                            : std_logic_vector(6 downto 0);
+      ch3_gain_val_o                           : std_logic_vector(15 downto 0);
+      ch3_offset_val_o                         : std_logic_vector(15 downto 0);
+      ch3_sat_val_o                            : std_logic_vector(14 downto 0);
+      ch4_ctl_ssr_o                            : std_logic_vector(6 downto 0);
+      ch4_gain_val_o                           : std_logic_vector(15 downto 0);
+      ch4_offset_val_o                         : std_logic_vector(15 downto 0);
+      ch4_sat_val_o                            : std_logic_vector(14 downto 0);
+      end record;
+    
+    constant c_fmc_adc_100ms_csr_out_registers_init_value: t_fmc_adc_100ms_csr_out_registers := (
+      ctl_fsm_cmd_o => (others => '0'),
+      ctl_fsm_cmd_wr_o => '0',
+      ctl_fmc_clk_oe_o => '0',
+      ctl_offset_dac_clr_n_o => '0',
+      ctl_man_bitslip_o => '0',
+      ctl_test_data_en_o => '0',
+      ctl_trig_led_o => '0',
+      ctl_acq_led_o => '0',
+      trig_cfg_hw_trig_sel_o => (others => '0'),
+      trig_cfg_hw_trig_pol_o => '0',
+      trig_cfg_hw_trig_en_o => '0',
+      trig_cfg_sw_trig_en_o => '0',
+      trig_cfg_int_trig_sel_o => (others => '0'),
+      trig_cfg_int_trig_test_en_o => '0',
+      trig_cfg_int_trig_thres_filt_o => (others => '0'),
+      trig_cfg_int_trig_thres_o => (others => '0'),
+      trig_dly_o => (others => '0'),
+      sw_trig_o => (others => '0'),
+      sw_trig_wr_o => '0',
+      shots_nb_o => (others => '0'),
+      sr_undersample_o => (others => '0'),
+      pre_samples_o => (others => '0'),
+      post_samples_o => (others => '0'),
+      ch1_ctl_ssr_o => (others => '0'),
+      ch1_gain_val_o => (others => '0'),
+      ch1_offset_val_o => (others => '0'),
+      ch1_sat_val_o => (others => '0'),
+      ch2_ctl_ssr_o => (others => '0'),
+      ch2_gain_val_o => (others => '0'),
+      ch2_offset_val_o => (others => '0'),
+      ch2_sat_val_o => (others => '0'),
+      ch3_ctl_ssr_o => (others => '0'),
+      ch3_gain_val_o => (others => '0'),
+      ch3_offset_val_o => (others => '0'),
+      ch3_sat_val_o => (others => '0'),
+      ch4_ctl_ssr_o => (others => '0'),
+      ch4_gain_val_o => (others => '0'),
+      ch4_offset_val_o => (others => '0'),
+      ch4_sat_val_o => (others => '0')
+      );
+    function "or" (left, right: t_fmc_adc_100ms_csr_in_registers) return t_fmc_adc_100ms_csr_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body fmc_adc_100ms_csr_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_fmc_adc_100ms_csr_in_registers) return t_fmc_adc_100ms_csr_in_registers is
+variable tmp: t_fmc_adc_100ms_csr_in_registers;
+begin
+tmp.sta_fsm_i := f_x_to_zero(left.sta_fsm_i) or f_x_to_zero(right.sta_fsm_i);
+tmp.sta_serdes_pll_i := f_x_to_zero(left.sta_serdes_pll_i) or f_x_to_zero(right.sta_serdes_pll_i);
+tmp.sta_serdes_synced_i := f_x_to_zero(left.sta_serdes_synced_i) or f_x_to_zero(right.sta_serdes_synced_i);
+tmp.sta_acq_cfg_i := f_x_to_zero(left.sta_acq_cfg_i) or f_x_to_zero(right.sta_acq_cfg_i);
+tmp.shots_cnt_val_i := f_x_to_zero(left.shots_cnt_val_i) or f_x_to_zero(right.shots_cnt_val_i);
+tmp.trig_pos_i := f_x_to_zero(left.trig_pos_i) or f_x_to_zero(right.trig_pos_i);
+tmp.fs_freq_i := f_x_to_zero(left.fs_freq_i) or f_x_to_zero(right.fs_freq_i);
+tmp.samples_cnt_i := f_x_to_zero(left.samples_cnt_i) or f_x_to_zero(right.samples_cnt_i);
+tmp.ch1_sta_val_i := f_x_to_zero(left.ch1_sta_val_i) or f_x_to_zero(right.ch1_sta_val_i);
+tmp.ch2_sta_val_i := f_x_to_zero(left.ch2_sta_val_i) or f_x_to_zero(right.ch2_sta_val_i);
+tmp.ch3_sta_val_i := f_x_to_zero(left.ch3_sta_val_i) or f_x_to_zero(right.ch3_sta_val_i);
+tmp.ch4_sta_val_i := f_x_to_zero(left.ch4_sta_val_i) or f_x_to_zero(right.ch4_sta_val_i);
+tmp.multi_depth_i := f_x_to_zero(left.multi_depth_i) or f_x_to_zero(right.multi_depth_i);
+return tmp;
+end function;
+end package body;
--- a/hdl/adc/rtl/fmc_adc_eic.vhd
+++ b/hdl/adc/rtl/fmc_adc_eic.vhd
 ---------------------------------------------------------------------------------------
-- Title          : Wishbone slave core for Fmc-adc enhanced interrupt controller
+-- Title          : Wishbone slave core for Fmc-adc embedded interrupt controller
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/fmc_adc_eic.vhd
 -- Author         : auto-generated by wbgen2 from fmc_adc_eic.wb
-- Created        : Wed Dec  4 09:44:26 2013
+-- Created        : Thu Jun 16 17:04:12 2016
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_eic.wb

--- a/hdl/adc/wb_gen/Makefile
+++ b/hdl/adc/wb_gen/Makefile
@@ -2,8 +2,10 @@ WBGEN2=$(shell which wbgen2)
 RTL=../rtl/
 TEX=../../../doc/manual/

+all: fmc_adc_100Ms_csr fmc_adc_eic
+
 fmc_adc_100Ms_csr:
-	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
+	$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
 	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb

 fmc_adc_eic:

--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
--- a/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
+++ b/hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
 peripheral {
  name = "FMC ADC 100MS/s core registers";
  description = "Wishbone slave for FMC ADC 100MS/s core";
-  hdl_entity = "fmc_adc_100Ms_csr";
+  hdl_entity = "fmc_adc_100ms_csr";

-  prefix = "fmc_adc_core";
+  prefix = "fmc_adc_100ms_csr";

  reg {
    name = "Control register";

--- a/hdl/adc/wb_gen/fmc_adc_eic.h
+++ b/hdl/adc/wb_gen/fmc_adc_eic.h
@@ -3,7 +3,7 @@

  * File           : fmc_adc_eic.h
  * Author         : auto-generated by wbgen2 from fmc_adc_eic.wb
-  * Created        : Wed Jan 22 11:18:26 2014
+  * Created        : Thu Jun 16 17:04:12 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_eic.wb
@@ -14,7 +14,11 @@
 #ifndef __WBGEN2_REGDEFS_FMC_ADC_EIC_WB
 #define __WBGEN2_REGDEFS_FMC_ADC_EIC_WB

+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
 #include <inttypes.h>
+#endif

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))

--- a/hdl/ip_cores/timetag_core/rtl/Manifest.py
+++ b/hdl/ip_cores/timetag_core/rtl/Manifest.py
 files = [
    "timetag_core_regs.vhd",
+    "timetag_core_regs_wbgen2_pkg.vhd",
    "timetag_core.vhd",
    "timetag_core_pkg.vhd"]
--- a/hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
+++ b/hdl/ip_cores/timetag_core/rtl/timetag_core.vhd
@@ -8,7 +8,7 @@
 --            : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-11-18
-- Last update: 2016-06-15
+-- Last update: 2016-06-16
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
 -- Description: Implements a UTC seconds counter and a 125MHz system clock
@@ -37,6 +37,7 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.all;
 use IEEE.NUMERIC_STD.all;
 use work.timetag_core_pkg.all;
+use work.timetag_core_wbgen2_pkg.all;

 entity timetag_core is
  port (
@@ -83,41 +84,19 @@ architecture rtl of timetag_core is
  ------------------------------------------------------------------------------
  component timetag_core_regs is
    port (
-      rst_n_i                                    : in  std_logic;
-      clk_sys_i                                  : in  std_logic;
-      wb_adr_i                                   : in  std_logic_vector(4 downto 0);
-      wb_dat_i                                   : in  std_logic_vector(31 downto 0);
-      wb_dat_o                                   : out std_logic_vector(31 downto 0);
-      wb_cyc_i                                   : in  std_logic;
-      wb_sel_i                                   : in  std_logic_vector(3 downto 0);
-      wb_stb_i                                   : in  std_logic;
-      wb_we_i                                    : in  std_logic;
-      wb_ack_o                                   : out std_logic;
-      wb_stall_o                                 : out std_logic;
-      timetag_core_seconds_upper_o               : out std_logic_vector(7 downto 0);
-      timetag_core_seconds_upper_i               : in  std_logic_vector(7 downto 0);
-      timetag_core_seconds_upper_load_o          : out std_logic;
-      timetag_core_seconds_lower_o               : out std_logic_vector(31 downto 0);
-      timetag_core_seconds_lower_i               : in  std_logic_vector(31 downto 0);
-      timetag_core_seconds_lower_load_o          : out std_logic;
-      timetag_core_coarse_o                      : out std_logic_vector(27 downto 0);
-      timetag_core_coarse_i                      : in  std_logic_vector(27 downto 0);
-      timetag_core_coarse_load_o                 : out std_logic;
-      timetag_core_time_trig_seconds_upper_o     : out std_logic_vector(7 downto 0);
-      timetag_core_time_trig_seconds_lower_o     : out std_logic_vector(31 downto 0);
-      timetag_core_time_trig_coarse_o            : out std_logic_vector(27 downto 0);
-      timetag_core_trig_tag_seconds_upper_i      : in  std_logic_vector(7 downto 0);
-      timetag_core_trig_tag_seconds_lower_i      : in  std_logic_vector(31 downto 0);
-      timetag_core_trig_tag_coarse_i             : in  std_logic_vector(27 downto 0);
-      timetag_core_acq_start_tag_seconds_upper_i : in  std_logic_vector(7 downto 0);
-      timetag_core_acq_start_tag_seconds_lower_i : in  std_logic_vector(31 downto 0);
-      timetag_core_acq_start_tag_coarse_i        : in  std_logic_vector(27 downto 0);
-      timetag_core_acq_stop_tag_seconds_upper_i  : in  std_logic_vector(7 downto 0);
-      timetag_core_acq_stop_tag_seconds_lower_i  : in  std_logic_vector(31 downto 0);
-      timetag_core_acq_stop_tag_coarse_i         : in  std_logic_vector(27 downto 0);
-      timetag_core_acq_end_tag_seconds_upper_i   : in  std_logic_vector(7 downto 0);
-      timetag_core_acq_end_tag_seconds_lower_i   : in  std_logic_vector(31 downto 0);
-      timetag_core_acq_end_tag_coarse_i          : in  std_logic_vector(27 downto 0));
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(4 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      regs_i     : in  t_timetag_core_in_registers;
+      regs_o     : out t_timetag_core_out_registers);
  end component timetag_core_regs;

  ------------------------------------------------------------------------------
@@ -141,6 +120,9 @@ architecture rtl of timetag_core is

  signal wr_enabled : std_logic := '0';

+  signal regin  : t_timetag_core_in_registers;
+  signal regout : t_timetag_core_out_registers;
+
 begin

  -- logic to detect if WR is enabled and timecode is valid
@@ -151,41 +133,42 @@ begin
  ------------------------------------------------------------------------------
  cmp_timetag_core_regs : timetag_core_regs
    port map (
-      rst_n_i                                    => rst_n_i,
-      clk_sys_i                                  => clk_i,
-      wb_adr_i                                   => wb_adr_i,
-      wb_dat_i                                   => wb_dat_i,
-      wb_dat_o                                   => wb_dat_o,
-      wb_cyc_i                                   => wb_cyc_i,
-      wb_sel_i                                   => wb_sel_i,
-      wb_stb_i                                   => wb_stb_i,
-      wb_we_i                                    => wb_we_i,
-      wb_ack_o                                   => wb_ack_o,
-      wb_stall_o                                 => open,
-      timetag_core_seconds_upper_o               => timetag_seconds_load_value(39 downto 32),
-      timetag_core_seconds_upper_i               => timetag_seconds(39 downto 32),
-      timetag_core_seconds_upper_load_o          => timetag_seconds_load_en(1),
-      timetag_core_seconds_lower_o               => timetag_seconds_load_value(31 downto 0),
-      timetag_core_seconds_lower_i               => timetag_seconds(31 downto 0),
-      timetag_core_seconds_lower_load_o          => timetag_seconds_load_en(0),
-      timetag_core_coarse_o                      => timetag_coarse_load_value,
-      timetag_core_coarse_i                      => timetag_coarse,
-      timetag_core_coarse_load_o                 => timetag_coarse_load_en,
-      timetag_core_time_trig_seconds_upper_o     => time_trigger.seconds(39 downto 32),
-      timetag_core_time_trig_seconds_lower_o     => time_trigger.seconds(31 downto 0),
-      timetag_core_time_trig_coarse_o            => time_trigger.coarse,
-      timetag_core_trig_tag_seconds_upper_i      => trig_tag.seconds(39 downto 32),
-      timetag_core_trig_tag_seconds_lower_i      => trig_tag.seconds(31 downto 0),
-      timetag_core_trig_tag_coarse_i             => trig_tag.coarse,
-      timetag_core_acq_start_tag_seconds_upper_i => acq_start_tag.seconds(39 downto 32),
-      timetag_core_acq_start_tag_seconds_lower_i => acq_start_tag.seconds(31 downto 0),
-      timetag_core_acq_start_tag_coarse_i        => acq_start_tag.coarse,
-      timetag_core_acq_stop_tag_seconds_upper_i  => acq_stop_tag.seconds(39 downto 32),
-      timetag_core_acq_stop_tag_seconds_lower_i  => acq_stop_tag.seconds(31 downto 0),
-      timetag_core_acq_stop_tag_coarse_i         => acq_stop_tag.coarse,
-      timetag_core_acq_end_tag_seconds_upper_i   => acq_end_tag.seconds(39 downto 32),
-      timetag_core_acq_end_tag_seconds_lower_i   => acq_end_tag.seconds(31 downto 0),
-      timetag_core_acq_end_tag_coarse_i          => acq_end_tag.coarse);
+      rst_n_i    => rst_n_i,
+      clk_sys_i  => clk_i,
+      wb_adr_i   => wb_adr_i,
+      wb_dat_i   => wb_dat_i,
+      wb_dat_o   => wb_dat_o,
+      wb_cyc_i   => wb_cyc_i,
+      wb_sel_i   => wb_sel_i,
+      wb_stb_i   => wb_stb_i,
+      wb_we_i    => wb_we_i,
+      wb_ack_o   => wb_ack_o,
+      wb_stall_o => open,
+      regs_i     => regin,
+      regs_o     => regout);
+
+  regin.seconds_upper_i               <= timetag_seconds(39 downto 32);
+  regin.seconds_lower_i               <= timetag_seconds(31 downto 0);
+  regin.coarse_i                      <= timetag_coarse;
+  regin.trig_tag_seconds_upper_i      <= trig_tag.seconds(39 downto 32);
+  regin.trig_tag_seconds_lower_i      <= trig_tag.seconds(31 downto 0);
+  regin.trig_tag_coarse_i             <= trig_tag.coarse;
+  regin.acq_start_tag_seconds_upper_i <= acq_start_tag.seconds(39 downto 32);
+  regin.acq_start_tag_seconds_lower_i <= acq_start_tag.seconds(31 downto 0);
+  regin.acq_start_tag_coarse_i        <= acq_start_tag.coarse;
+  regin.acq_stop_tag_seconds_upper_i  <= acq_stop_tag.seconds(39 downto 32);
+  regin.acq_stop_tag_seconds_lower_i  <= acq_stop_tag.seconds(31 downto 0);
+  regin.acq_stop_tag_coarse_i         <= acq_stop_tag.coarse;
+  regin.acq_end_tag_seconds_upper_i   <= acq_end_tag.seconds(39 downto 32);
+  regin.acq_end_tag_seconds_lower_i   <= acq_end_tag.seconds(31 downto 0);
+  regin.acq_end_tag_coarse_i          <= acq_end_tag.coarse;
+
+  timetag_seconds_load_en    <= regout.seconds_upper_load_o & regout.seconds_lower_load_o;
+  timetag_seconds_load_value <= regout.seconds_upper_o & regout.seconds_lower_o;
+  timetag_coarse_load_value  <= regout.coarse_o;
+  timetag_coarse_load_en     <= regout.coarse_load_o;
+  time_trigger.seconds       <= regout.time_trig_seconds_upper_o & regout.time_trig_seconds_lower_o;
+  time_trigger.coarse        <= regout.time_trig_coarse_o;

  ------------------------------------------------------------------------------
  -- UTC seconds counter
@@ -232,7 +215,7 @@ begin
  end process p_timetag_coarse_cnt;

  timetag_coarse <= wr_tm_cycles_i when wr_enabled = '1' else std_logic_vector(timetag_coarse_cnt);
-  
+
  ------------------------------------------------------------------------------
  -- Time trigger signal generation
  ------------------------------------------------------------------------------

--- a/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd
+++ b/hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd
--- a/hdl/ip_cores/timetag_core/rtl/timetag_core_regs_wbgen2_pkg.vhd
+++ b/hdl/ip_cores/timetag_core/rtl/timetag_core_regs_wbgen2_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Time-tagging core registers
+---------------------------------------------------------------------------------------
+-- File           : ../rtl/timetag_core_regs_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from timetag_core_regs.wb
+-- Created        : Thu Jun 16 17:23:36 2016
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package timetag_core_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_timetag_core_in_registers is record
+    seconds_upper_i                          : std_logic_vector(7 downto 0);
+    seconds_lower_i                          : std_logic_vector(31 downto 0);
+    coarse_i                                 : std_logic_vector(27 downto 0);
+    trig_tag_seconds_upper_i                 : std_logic_vector(7 downto 0);
+    trig_tag_seconds_lower_i                 : std_logic_vector(31 downto 0);
+    trig_tag_coarse_i                        : std_logic_vector(27 downto 0);
+    acq_start_tag_seconds_upper_i            : std_logic_vector(7 downto 0);
+    acq_start_tag_seconds_lower_i            : std_logic_vector(31 downto 0);
+    acq_start_tag_coarse_i                   : std_logic_vector(27 downto 0);
+    acq_stop_tag_seconds_upper_i             : std_logic_vector(7 downto 0);
+    acq_stop_tag_seconds_lower_i             : std_logic_vector(31 downto 0);
+    acq_stop_tag_coarse_i                    : std_logic_vector(27 downto 0);
+    acq_end_tag_seconds_upper_i              : std_logic_vector(7 downto 0);
+    acq_end_tag_seconds_lower_i              : std_logic_vector(31 downto 0);
+    acq_end_tag_coarse_i                     : std_logic_vector(27 downto 0);
+    end record;
+  
+  constant c_timetag_core_in_registers_init_value: t_timetag_core_in_registers := (
+    seconds_upper_i => (others => '0'),
+    seconds_lower_i => (others => '0'),
+    coarse_i => (others => '0'),
+    trig_tag_seconds_upper_i => (others => '0'),
+    trig_tag_seconds_lower_i => (others => '0'),
+    trig_tag_coarse_i => (others => '0'),
+    acq_start_tag_seconds_upper_i => (others => '0'),
+    acq_start_tag_seconds_lower_i => (others => '0'),
+    acq_start_tag_coarse_i => (others => '0'),
+    acq_stop_tag_seconds_upper_i => (others => '0'),
+    acq_stop_tag_seconds_lower_i => (others => '0'),
+    acq_stop_tag_coarse_i => (others => '0'),
+    acq_end_tag_seconds_upper_i => (others => '0'),
+    acq_end_tag_seconds_lower_i => (others => '0'),
+    acq_end_tag_coarse_i => (others => '0')
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_timetag_core_out_registers is record
+      seconds_upper_o                          : std_logic_vector(7 downto 0);
+      seconds_upper_load_o                     : std_logic;
+      seconds_lower_o                          : std_logic_vector(31 downto 0);
+      seconds_lower_load_o                     : std_logic;
+      coarse_o                                 : std_logic_vector(27 downto 0);
+      coarse_load_o                            : std_logic;
+      time_trig_seconds_upper_o                : std_logic_vector(7 downto 0);
+      time_trig_seconds_lower_o                : std_logic_vector(31 downto 0);
+      time_trig_coarse_o                       : std_logic_vector(27 downto 0);
+      end record;
+    
+    constant c_timetag_core_out_registers_init_value: t_timetag_core_out_registers := (
+      seconds_upper_o => (others => '0'),
+      seconds_upper_load_o => '0',
+      seconds_lower_o => (others => '0'),
+      seconds_lower_load_o => '0',
+      coarse_o => (others => '0'),
+      coarse_load_o => '0',
+      time_trig_seconds_upper_o => (others => '0'),
+      time_trig_seconds_lower_o => (others => '0'),
+      time_trig_coarse_o => (others => '0')
+      );
+    function "or" (left, right: t_timetag_core_in_registers) return t_timetag_core_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body timetag_core_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_timetag_core_in_registers) return t_timetag_core_in_registers is
+variable tmp: t_timetag_core_in_registers;
+begin
+tmp.seconds_upper_i := f_x_to_zero(left.seconds_upper_i) or f_x_to_zero(right.seconds_upper_i);
+tmp.seconds_lower_i := f_x_to_zero(left.seconds_lower_i) or f_x_to_zero(right.seconds_lower_i);
+tmp.coarse_i := f_x_to_zero(left.coarse_i) or f_x_to_zero(right.coarse_i);
+tmp.trig_tag_seconds_upper_i := f_x_to_zero(left.trig_tag_seconds_upper_i) or f_x_to_zero(right.trig_tag_seconds_upper_i);
+tmp.trig_tag_seconds_lower_i := f_x_to_zero(left.trig_tag_seconds_lower_i) or f_x_to_zero(right.trig_tag_seconds_lower_i);
+tmp.trig_tag_coarse_i := f_x_to_zero(left.trig_tag_coarse_i) or f_x_to_zero(right.trig_tag_coarse_i);
+tmp.acq_start_tag_seconds_upper_i := f_x_to_zero(left.acq_start_tag_seconds_upper_i) or f_x_to_zero(right.acq_start_tag_seconds_upper_i);
+tmp.acq_start_tag_seconds_lower_i := f_x_to_zero(left.acq_start_tag_seconds_lower_i) or f_x_to_zero(right.acq_start_tag_seconds_lower_i);
+tmp.acq_start_tag_coarse_i := f_x_to_zero(left.acq_start_tag_coarse_i) or f_x_to_zero(right.acq_start_tag_coarse_i);
+tmp.acq_stop_tag_seconds_upper_i := f_x_to_zero(left.acq_stop_tag_seconds_upper_i) or f_x_to_zero(right.acq_stop_tag_seconds_upper_i);
+tmp.acq_stop_tag_seconds_lower_i := f_x_to_zero(left.acq_stop_tag_seconds_lower_i) or f_x_to_zero(right.acq_stop_tag_seconds_lower_i);
+tmp.acq_stop_tag_coarse_i := f_x_to_zero(left.acq_stop_tag_coarse_i) or f_x_to_zero(right.acq_stop_tag_coarse_i);
+tmp.acq_end_tag_seconds_upper_i := f_x_to_zero(left.acq_end_tag_seconds_upper_i) or f_x_to_zero(right.acq_end_tag_seconds_upper_i);
+tmp.acq_end_tag_seconds_lower_i := f_x_to_zero(left.acq_end_tag_seconds_lower_i) or f_x_to_zero(right.acq_end_tag_seconds_lower_i);
+tmp.acq_end_tag_coarse_i := f_x_to_zero(left.acq_end_tag_coarse_i) or f_x_to_zero(right.acq_end_tag_coarse_i);
+return tmp;
+end function;
+end package body;
--- a/hdl/ip_cores/timetag_core/wb_gen/Makefile
+++ b/hdl/ip_cores/timetag_core/wb_gen/Makefile
@@ -3,5 +3,5 @@ RTL=../rtl/
 TEX=../../../../doc/manual/

 timetag_core_regs:
-	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
+	$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
 	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
--- a/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h
+++ b/hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h
@@ -3,7 +3,7 @@

  * File           : timetag_core_regs.h
  * Author         : auto-generated by wbgen2 from timetag_core_regs.wb
-  * Created        : Wed Jun 15 15:54:40 2016
+  * Created        : Thu Jun 16 17:23:36 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
@@ -14,7 +14,11 @@
 #ifndef __WBGEN2_REGDEFS_TIMETAG_CORE_REGS_WB
 #define __WBGEN2_REGDEFS_TIMETAG_CORE_REGS_WB

+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
 #include <inttypes.h>
+#endif

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))

--- a/hdl/spec/rtl/Manifest.py
+++ b/hdl/spec/rtl/Manifest.py
 files = [
    "spec_top_fmc_adc_100Ms.vhd",
    "carrier_csr.vhd",
+    "carrier_csr_wbgen2_pkg.vhd",
    "dma_eic.vhd",
    "sdb_meta_pkg.vhd"]
--- a/hdl/spec/rtl/carrier_csr.vhd
+++ b/hdl/spec/rtl/carrier_csr.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/carrier_csr.vhd
 -- Author         : auto-generated by wbgen2 from carrier_csr.wb
-- Created        : Thu Jun  9 13:40:05 2016
+-- Created        : Thu Jun 16 16:45:19 2016
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
@@ -14,6 +14,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

+use work.carrier_csr_wbgen2_pkg.all;
+
+
 entity carrier_csr is
  port (
    rst_n_i                                  : in     std_logic;
@@ -27,30 +30,8 @@ entity carrier_csr is
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
-    carrier_csr_carrier_pcb_rev_i            : in     std_logic_vector(3 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
-    carrier_csr_carrier_reserved_i           : in     std_logic_vector(11 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
-    carrier_csr_carrier_type_i               : in     std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC presence' in reg: 'Status'
-    carrier_csr_stat_fmc_pres_i              : in     std_logic;
-- Port for BIT field: 'GN4142 core P2L PLL status' in reg: 'Status'
-    carrier_csr_stat_p2l_pll_lck_i           : in     std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
-    carrier_csr_stat_sys_pll_lck_i           : in     std_logic;
-- Port for BIT field: 'DDR3 calibration status' in reg: 'Status'
-    carrier_csr_stat_ddr3_cal_done_i         : in     std_logic;
-- Port for BIT field: 'Green LED' in reg: 'Control'
-    carrier_csr_ctrl_led_green_o             : out    std_logic;
-- Port for BIT field: 'Red LED' in reg: 'Control'
-    carrier_csr_ctrl_led_red_o               : out    std_logic;
-- Port for BIT field: 'DAC clear' in reg: 'Control'
-    carrier_csr_ctrl_dac_clr_n_o             : out    std_logic;
-- Port for BIT field: 'White Rabbit enable' in reg: 'Control'
-    carrier_csr_ctrl_wrabbit_en_o            : out    std_logic;
-- Port for BIT field: 'State of the reset line' in reg: 'Reset Register'
-    carrier_csr_rst_fmc0_o                   : out    std_logic
+    regs_i                                   : in     t_carrier_csr_in_registers;
+    regs_o                                   : out    t_carrier_csr_out_registers
  );
 end carrier_csr;

@@ -108,18 +89,18 @@ begin
          when "00" => 
            if (wb_we_i = '1') then
            end if;
-            rddata_reg(3 downto 0) <= carrier_csr_carrier_pcb_rev_i;
-            rddata_reg(15 downto 4) <= carrier_csr_carrier_reserved_i;
-            rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
+            rddata_reg(3 downto 0) <= regs_i.carrier_pcb_rev_i;
+            rddata_reg(15 downto 4) <= regs_i.carrier_reserved_i;
+            rddata_reg(31 downto 16) <= regs_i.carrier_type_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01" => 
            if (wb_we_i = '1') then
            end if;
-            rddata_reg(0) <= carrier_csr_stat_fmc_pres_i;
-            rddata_reg(1) <= carrier_csr_stat_p2l_pll_lck_i;
-            rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
-            rddata_reg(3) <= carrier_csr_stat_ddr3_cal_done_i;
+            rddata_reg(0) <= regs_i.stat_fmc_pres_i;
+            rddata_reg(1) <= regs_i.stat_p2l_pll_lck_i;
+            rddata_reg(2) <= regs_i.stat_sys_pll_lck_i;
+            rddata_reg(3) <= regs_i.stat_ddr3_cal_done_i;
            rddata_reg(4) <= 'X';
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
@@ -250,15 +231,15 @@ begin
 -- System clock PLL status
 -- DDR3 calibration status
 -- Green LED
-  carrier_csr_ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
+  regs_o.ctrl_led_green_o <= carrier_csr_ctrl_led_green_int;
 -- Red LED
-  carrier_csr_ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
+  regs_o.ctrl_led_red_o <= carrier_csr_ctrl_led_red_int;
 -- DAC clear
-  carrier_csr_ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
+  regs_o.ctrl_dac_clr_n_o <= carrier_csr_ctrl_dac_clr_n_int;
 -- White Rabbit enable
-  carrier_csr_ctrl_wrabbit_en_o <= carrier_csr_ctrl_wrabbit_en_int;
+  regs_o.ctrl_wrabbit_en_o <= carrier_csr_ctrl_wrabbit_en_int;
 -- State of the reset line
-  carrier_csr_rst_fmc0_o <= carrier_csr_rst_fmc0_int;
+  regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
 -- ACK signal generation. Just pass the LSB of ACK counter.

--- a/hdl/spec/rtl/carrier_csr_wbgen2_pkg.vhd
+++ b/hdl/spec/rtl/carrier_csr_wbgen2_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for Carrier control and status registers
+---------------------------------------------------------------------------------------
+-- File           : ../rtl/carrier_csr_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from carrier_csr.wb
+-- Created        : Thu Jun 16 16:45:19 2016
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package carrier_csr_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_carrier_csr_in_registers is record
+    carrier_pcb_rev_i                        : std_logic_vector(3 downto 0);
+    carrier_reserved_i                       : std_logic_vector(11 downto 0);
+    carrier_type_i                           : std_logic_vector(15 downto 0);
+    stat_fmc_pres_i                          : std_logic;
+    stat_p2l_pll_lck_i                       : std_logic;
+    stat_sys_pll_lck_i                       : std_logic;
+    stat_ddr3_cal_done_i                     : std_logic;
+    end record;
+  
+  constant c_carrier_csr_in_registers_init_value: t_carrier_csr_in_registers := (
+    carrier_pcb_rev_i => (others => '0'),
+    carrier_reserved_i => (others => '0'),
+    carrier_type_i => (others => '0'),
+    stat_fmc_pres_i => '0',
+    stat_p2l_pll_lck_i => '0',
+    stat_sys_pll_lck_i => '0',
+    stat_ddr3_cal_done_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_carrier_csr_out_registers is record
+      ctrl_led_green_o                         : std_logic;
+      ctrl_led_red_o                           : std_logic;
+      ctrl_dac_clr_n_o                         : std_logic;
+      ctrl_wrabbit_en_o                        : std_logic;
+      rst_fmc0_o                               : std_logic;
+      end record;
+    
+    constant c_carrier_csr_out_registers_init_value: t_carrier_csr_out_registers := (
+      ctrl_led_green_o => '0',
+      ctrl_led_red_o => '0',
+      ctrl_dac_clr_n_o => '0',
+      ctrl_wrabbit_en_o => '0',
+      rst_fmc0_o => '0'
+      );
+    function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body carrier_csr_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers is
+variable tmp: t_carrier_csr_in_registers;
+begin
+tmp.carrier_pcb_rev_i := f_x_to_zero(left.carrier_pcb_rev_i) or f_x_to_zero(right.carrier_pcb_rev_i);
+tmp.carrier_reserved_i := f_x_to_zero(left.carrier_reserved_i) or f_x_to_zero(right.carrier_reserved_i);
+tmp.carrier_type_i := f_x_to_zero(left.carrier_type_i) or f_x_to_zero(right.carrier_type_i);
+tmp.stat_fmc_pres_i := f_x_to_zero(left.stat_fmc_pres_i) or f_x_to_zero(right.stat_fmc_pres_i);
+tmp.stat_p2l_pll_lck_i := f_x_to_zero(left.stat_p2l_pll_lck_i) or f_x_to_zero(right.stat_p2l_pll_lck_i);
+tmp.stat_sys_pll_lck_i := f_x_to_zero(left.stat_sys_pll_lck_i) or f_x_to_zero(right.stat_sys_pll_lck_i);
+tmp.stat_ddr3_cal_done_i := f_x_to_zero(left.stat_ddr3_cal_done_i) or f_x_to_zero(right.stat_ddr3_cal_done_i);
+return tmp;
+end function;
+end package body;
--- a/hdl/spec/rtl/dma_eic.vhd
+++ b/hdl/spec/rtl/dma_eic.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/dma_eic.vhd
 -- Author         : auto-generated by wbgen2 from dma_eic.wb
-- Created        : Wed Dec  4 09:51:41 2013
+-- Created        : Thu Jun 16 16:45:19 2016
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb

--- a/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
+++ b/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
@@ -8,7 +8,7 @@
 --            : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2011-02-24
-- Last update: 2016-06-09
+-- Last update: 2016-06-16
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
 -- Description: Top entity of FMC ADC 100Ms/s design for Simple PCIe FMC
@@ -53,6 +53,7 @@ use work.wishbone_pkg.all;
 use work.fmc_adc_mezzanine_pkg.all;
 use work.sdb_meta_pkg.all;
 use work.timetag_core_pkg.all;
+use work.carrier_csr_wbgen2_pkg.all;


 entity spec_top_fmc_adc_100Ms is
@@ -184,29 +185,19 @@ architecture rtl of spec_top_fmc_adc_100Ms is
  ------------------------------------------------------------------------------
  component carrier_csr is
    port (
-      rst_n_i                          : in  std_logic;
-      clk_sys_i                        : in  std_logic;
-      wb_adr_i                         : in  std_logic_vector(1 downto 0);
-      wb_dat_i                         : in  std_logic_vector(31 downto 0);
-      wb_dat_o                         : out std_logic_vector(31 downto 0);
-      wb_cyc_i                         : in  std_logic;
-      wb_sel_i                         : in  std_logic_vector(3 downto 0);
-      wb_stb_i                         : in  std_logic;
-      wb_we_i                          : in  std_logic;
-      wb_ack_o                         : out std_logic;
-      wb_stall_o                       : out std_logic;
-      carrier_csr_carrier_pcb_rev_i    : in  std_logic_vector(3 downto 0);
-      carrier_csr_carrier_reserved_i   : in  std_logic_vector(11 downto 0);
-      carrier_csr_carrier_type_i       : in  std_logic_vector(15 downto 0);
-      carrier_csr_stat_fmc_pres_i      : in  std_logic;
-      carrier_csr_stat_p2l_pll_lck_i   : in  std_logic;
-      carrier_csr_stat_sys_pll_lck_i   : in  std_logic;
-      carrier_csr_stat_ddr3_cal_done_i : in  std_logic;
-      carrier_csr_ctrl_led_green_o     : out std_logic;
-      carrier_csr_ctrl_led_red_o       : out std_logic;
-      carrier_csr_ctrl_dac_clr_n_o     : out std_logic;
-      carrier_csr_ctrl_wrabbit_en_o    : out std_logic;
-      carrier_csr_rst_fmc0_o           : out std_logic);
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(1 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      regs_i     : in  t_carrier_csr_in_registers;
+      regs_o     : out t_carrier_csr_out_registers);
  end component carrier_csr;

  component dma_eic
@@ -450,6 +441,10 @@ architecture rtl of spec_top_fmc_adc_100Ms is
  -- White Rabbit
  signal wrabbit_en : std_logic;

+  -- IO for CSR registers
+  signal csr_regin  : t_carrier_csr_in_registers;
+  signal csr_regout : t_carrier_csr_out_registers;
+
 begin


@@ -710,30 +705,32 @@ begin
  ------------------------------------------------------------------------------
  cmp_carrier_csr : carrier_csr
    port map(
-      rst_n_i                          => sys_rst_125_n,
-      clk_sys_i                        => sys_clk_125,
-      wb_adr_i                         => cnx_master_out(c_WB_SLAVE_SPEC_CSR).adr(3 downto 2),  -- cnx_master_out.adr is byte address
-      wb_dat_i                         => cnx_master_out(c_WB_SLAVE_SPEC_CSR).dat,
-      wb_dat_o                         => cnx_master_in(c_WB_SLAVE_SPEC_CSR).dat,
-      wb_cyc_i                         => cnx_master_out(c_WB_SLAVE_SPEC_CSR).cyc,
-      wb_sel_i                         => cnx_master_out(c_WB_SLAVE_SPEC_CSR).sel,
-      wb_stb_i                         => cnx_master_out(c_WB_SLAVE_SPEC_CSR).stb,
-      wb_we_i                          => cnx_master_out(c_WB_SLAVE_SPEC_CSR).we,
-      wb_ack_o                         => cnx_master_in(c_WB_SLAVE_SPEC_CSR).ack,
-      wb_stall_o                       => open,
-      carrier_csr_carrier_pcb_rev_i    => pcb_ver_i,
-      carrier_csr_carrier_reserved_i   => X"000",
-      carrier_csr_carrier_type_i       => c_CARRIER_TYPE,
-      carrier_csr_stat_fmc_pres_i      => fmc0_prsnt_m2c_n_i,
-      carrier_csr_stat_p2l_pll_lck_i   => p2l_pll_locked,
-      carrier_csr_stat_sys_pll_lck_i   => sys_clk_pll_locked,
-      carrier_csr_stat_ddr3_cal_done_i => ddr3_calib_done,
-      carrier_csr_ctrl_led_green_o     => led_green,
-      carrier_csr_ctrl_led_red_o       => led_red,
-      carrier_csr_ctrl_dac_clr_n_o     => open,
-      carrier_csr_ctrl_wrabbit_en_o    => wrabbit_en,
-      carrier_csr_rst_fmc0_o           => sw_rst_fmc0
-      );
+      rst_n_i    => sys_rst_125_n,
+      clk_sys_i  => sys_clk_125,
+      wb_adr_i   => cnx_master_out(c_WB_SLAVE_SPEC_CSR).adr(3 downto 2),  -- cnx_master_out.adr is byte address
+      wb_dat_i   => cnx_master_out(c_WB_SLAVE_SPEC_CSR).dat,
+      wb_dat_o   => cnx_master_in(c_WB_SLAVE_SPEC_CSR).dat,
+      wb_cyc_i   => cnx_master_out(c_WB_SLAVE_SPEC_CSR).cyc,
+      wb_sel_i   => cnx_master_out(c_WB_SLAVE_SPEC_CSR).sel,
+      wb_stb_i   => cnx_master_out(c_WB_SLAVE_SPEC_CSR).stb,
+      wb_we_i    => cnx_master_out(c_WB_SLAVE_SPEC_CSR).we,
+      wb_ack_o   => cnx_master_in(c_WB_SLAVE_SPEC_CSR).ack,
+      wb_stall_o => open,
+      regs_i     => csr_regin,
+      regs_o     => csr_regout);
+
+  csr_regin.carrier_pcb_rev_i    <= pcb_ver_i;
+  csr_regin.carrier_reserved_i   <= X"000";
+  csr_regin.carrier_type_i       <= c_CARRIER_TYPE;
+  csr_regin.stat_fmc_pres_i      <= fmc0_prsnt_m2c_n_i;
+  csr_regin.stat_p2l_pll_lck_i   <= p2l_pll_locked;
+  csr_regin.stat_sys_pll_lck_i   <= sys_clk_pll_locked;
+  csr_regin.stat_ddr3_cal_done_i <= ddr3_calib_done;
+
+  led_green   <= csr_regout.ctrl_led_green_o;
+  led_red     <= csr_regout.ctrl_led_red_o;
+  wrabbit_en  <= csr_regout.ctrl_wrabbit_en_o;
+  sw_rst_fmc0 <= csr_regout.rst_fmc0_o;

  -- Unused wishbone signals
  cnx_master_in(c_WB_SLAVE_SPEC_CSR).err   <= '0';

--- a/hdl/spec/wb_gen/Makefile
+++ b/hdl/spec/wb_gen/Makefile
@@ -2,8 +2,10 @@ WBGEN2=$(shell which wbgen2)
 RTL=../rtl/
 TEX=../../../doc/manual/spec/

+all: carrier_csr dma_eic
+
 carrier_csr:
-	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
+	$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
 	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb

 dma_eic:

--- a/hdl/spec/wb_gen/carrier_csr.h
+++ b/hdl/spec/wb_gen/carrier_csr.h
@@ -3,7 +3,7 @@

  * File           : carrier_csr.h
  * Author         : auto-generated by wbgen2 from carrier_csr.wb
-  * Created        : Thu Jun  9 13:40:05 2016
+  * Created        : Thu Jun 16 16:45:19 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
@@ -14,7 +14,11 @@
 #ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
 #define __WBGEN2_REGDEFS_CARRIER_CSR_WB

+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
 #include <inttypes.h>
+#endif

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))

--- a/hdl/spec/wb_gen/dma_eic.h
+++ b/hdl/spec/wb_gen/dma_eic.h
@@ -3,7 +3,7 @@

  * File           : dma_eic.h
  * Author         : auto-generated by wbgen2 from dma_eic.wb
-  * Created        : Wed Dec  4 09:51:41 2013
+  * Created        : Thu Jun 16 16:45:19 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE dma_eic.wb
@@ -14,7 +14,11 @@
 #ifndef __WBGEN2_REGDEFS_DMA_EIC_WB
 #define __WBGEN2_REGDEFS_DMA_EIC_WB

+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
 #include <inttypes.h>
+#endif

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))

--- a/hdl/svec/rtl/Manifest.py
+++ b/hdl/svec/rtl/Manifest.py
 files = [
    "svec_top_fmc_adc_100Ms.vhd",
    "carrier_csr.vhd",
+    "carrier_csr_wbgen2_pkg.vhd",
    "sdb_meta_pkg.vhd"]
--- a/hdl/svec/rtl/carrier_csr.vhd
+++ b/hdl/svec/rtl/carrier_csr.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/carrier_csr.vhd
 -- Author         : auto-generated by wbgen2 from carrier_csr.wb
-- Created        : Thu Jun  9 13:46:23 2016
+-- Created        : Thu Jun 16 17:11:57 2016
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
@@ -14,6 +14,9 @@ library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;

+use work.carrier_csr_wbgen2_pkg.all;
+
+
 entity carrier_csr is
  port (
    rst_n_i                                  : in     std_logic;
@@ -27,30 +30,8 @@ entity carrier_csr is
    wb_we_i                                  : in     std_logic;
    wb_ack_o                                 : out    std_logic;
    wb_stall_o                               : out    std_logic;
-- Port for std_logic_vector field: 'PCB revision' in reg: 'Carrier type and PCB version'
-    carrier_csr_carrier_pcb_rev_i            : in     std_logic_vector(4 downto 0);
-- Port for std_logic_vector field: 'Reserved register' in reg: 'Carrier type and PCB version'
-    carrier_csr_carrier_reserved_i           : in     std_logic_vector(10 downto 0);
-- Port for std_logic_vector field: 'Carrier type' in reg: 'Carrier type and PCB version'
-    carrier_csr_carrier_type_i               : in     std_logic_vector(15 downto 0);
-- Port for BIT field: 'FMC 1 presence' in reg: 'Status'
-    carrier_csr_stat_fmc0_pres_i             : in     std_logic;
-- Port for BIT field: 'FMC 2 presence' in reg: 'Status'
-    carrier_csr_stat_fmc1_pres_i             : in     std_logic;
-- Port for BIT field: 'System clock PLL status' in reg: 'Status'
-    carrier_csr_stat_sys_pll_lck_i           : in     std_logic;
-- Port for BIT field: 'DDR3 bank 4 calibration status' in reg: 'Status'
-    carrier_csr_stat_ddr0_cal_done_i         : in     std_logic;
-- Port for BIT field: 'DDR3 bank 5 calibration status' in reg: 'Status'
-    carrier_csr_stat_ddr1_cal_done_i         : in     std_logic;
-- Port for std_logic_vector field: 'Front panel LED manual control' in reg: 'Control'
-    carrier_csr_ctrl_fp_leds_man_o           : out    std_logic_vector(15 downto 0);
-- Port for BIT field: 'White Rabbit enable' in reg: 'Control'
-    carrier_csr_ctrl_wrabbit_en_o            : out    std_logic;
-- Port for BIT field: 'State of the FMC 1 reset line' in reg: 'Reset Register'
-    carrier_csr_rst_fmc0_o                   : out    std_logic;
-- Port for BIT field: 'State of the FMC 2 reset line' in reg: 'Reset Register'
-    carrier_csr_rst_fmc1_o                   : out    std_logic
+    regs_i                                   : in     t_carrier_csr_in_registers;
+    regs_o                                   : out    t_carrier_csr_out_registers
  );
 end carrier_csr;

@@ -106,19 +87,19 @@ begin
          when "00" => 
            if (wb_we_i = '1') then
            end if;
-            rddata_reg(4 downto 0) <= carrier_csr_carrier_pcb_rev_i;
-            rddata_reg(15 downto 5) <= carrier_csr_carrier_reserved_i;
-            rddata_reg(31 downto 16) <= carrier_csr_carrier_type_i;
+            rddata_reg(4 downto 0) <= regs_i.carrier_pcb_rev_i;
+            rddata_reg(15 downto 5) <= regs_i.carrier_reserved_i;
+            rddata_reg(31 downto 16) <= regs_i.carrier_type_i;
            ack_sreg(0) <= '1';
            ack_in_progress <= '1';
          when "01" => 
            if (wb_we_i = '1') then
            end if;
-            rddata_reg(0) <= carrier_csr_stat_fmc0_pres_i;
-            rddata_reg(1) <= carrier_csr_stat_fmc1_pres_i;
-            rddata_reg(2) <= carrier_csr_stat_sys_pll_lck_i;
-            rddata_reg(3) <= carrier_csr_stat_ddr0_cal_done_i;
-            rddata_reg(4) <= carrier_csr_stat_ddr1_cal_done_i;
+            rddata_reg(0) <= regs_i.stat_fmc0_pres_i;
+            rddata_reg(1) <= regs_i.stat_fmc1_pres_i;
+            rddata_reg(2) <= regs_i.stat_sys_pll_lck_i;
+            rddata_reg(3) <= regs_i.stat_ddr0_cal_done_i;
+            rddata_reg(4) <= regs_i.stat_ddr1_cal_done_i;
            rddata_reg(5) <= 'X';
            rddata_reg(6) <= 'X';
            rddata_reg(7) <= 'X';
@@ -233,13 +214,13 @@ begin
 -- DDR3 bank 4 calibration status
 -- DDR3 bank 5 calibration status
 -- Front panel LED manual control
-  carrier_csr_ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
+  regs_o.ctrl_fp_leds_man_o <= carrier_csr_ctrl_fp_leds_man_int;
 -- White Rabbit enable
-  carrier_csr_ctrl_wrabbit_en_o <= carrier_csr_ctrl_wrabbit_en_int;
+  regs_o.ctrl_wrabbit_en_o <= carrier_csr_ctrl_wrabbit_en_int;
 -- State of the FMC 1 reset line
-  carrier_csr_rst_fmc0_o <= carrier_csr_rst_fmc0_int;
+  regs_o.rst_fmc0_o <= carrier_csr_rst_fmc0_int;
 -- State of the FMC 2 reset line
-  carrier_csr_rst_fmc1_o <= carrier_csr_rst_fmc1_int;
+  regs_o.rst_fmc1_o <= carrier_csr_rst_fmc1_int;
  rwaddr_reg <= wb_adr_i;
  wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
 -- ACK signal generation. Just pass the LSB of ACK counter.

--- a/hdl/svec/rtl/carrier_csr_wbgen2_pkg.vhd
+++ b/hdl/svec/rtl/carrier_csr_wbgen2_pkg.vhd
+---------------------------------------------------------------------------------------
+-- Title          : Wishbone slave core for SVEC carrier control and status registers
+---------------------------------------------------------------------------------------
+-- File           : ../rtl/carrier_csr_wbgen2_pkg.vhd
+-- Author         : auto-generated by wbgen2 from carrier_csr.wb
+-- Created        : Thu Jun 16 17:11:57 2016
+-- Standard       : VHDL'87
+---------------------------------------------------------------------------------------
+-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
+-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
+---------------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package carrier_csr_wbgen2_pkg is
+  
+  
+  -- Input registers (user design -> WB slave)
+  
+  type t_carrier_csr_in_registers is record
+    carrier_pcb_rev_i                        : std_logic_vector(4 downto 0);
+    carrier_reserved_i                       : std_logic_vector(10 downto 0);
+    carrier_type_i                           : std_logic_vector(15 downto 0);
+    stat_fmc0_pres_i                         : std_logic;
+    stat_fmc1_pres_i                         : std_logic;
+    stat_sys_pll_lck_i                       : std_logic;
+    stat_ddr0_cal_done_i                     : std_logic;
+    stat_ddr1_cal_done_i                     : std_logic;
+    end record;
+  
+  constant c_carrier_csr_in_registers_init_value: t_carrier_csr_in_registers := (
+    carrier_pcb_rev_i => (others => '0'),
+    carrier_reserved_i => (others => '0'),
+    carrier_type_i => (others => '0'),
+    stat_fmc0_pres_i => '0',
+    stat_fmc1_pres_i => '0',
+    stat_sys_pll_lck_i => '0',
+    stat_ddr0_cal_done_i => '0',
+    stat_ddr1_cal_done_i => '0'
+    );
+    
+    -- Output registers (WB slave -> user design)
+    
+    type t_carrier_csr_out_registers is record
+      ctrl_fp_leds_man_o                       : std_logic_vector(15 downto 0);
+      ctrl_wrabbit_en_o                        : std_logic;
+      rst_fmc0_o                               : std_logic;
+      rst_fmc1_o                               : std_logic;
+      end record;
+    
+    constant c_carrier_csr_out_registers_init_value: t_carrier_csr_out_registers := (
+      ctrl_fp_leds_man_o => (others => '0'),
+      ctrl_wrabbit_en_o => '0',
+      rst_fmc0_o => '0',
+      rst_fmc1_o => '0'
+      );
+    function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers;
+    function f_x_to_zero (x:std_logic) return std_logic;
+    function f_x_to_zero (x:std_logic_vector) return std_logic_vector;
+end package;
+
+package body carrier_csr_wbgen2_pkg is
+function f_x_to_zero (x:std_logic) return std_logic is
+begin
+if x = '1' then
+return '1';
+else
+return '0';
+end if;
+end function;
+function f_x_to_zero (x:std_logic_vector) return std_logic_vector is
+variable tmp: std_logic_vector(x'length-1 downto 0);
+begin
+for i in 0 to x'length-1 loop
+if(x(i) = 'X' or x(i) = 'U') then
+tmp(i):= '0';
+else
+tmp(i):=x(i);
+end if; 
+end loop; 
+return tmp;
+end function;
+function "or" (left, right: t_carrier_csr_in_registers) return t_carrier_csr_in_registers is
+variable tmp: t_carrier_csr_in_registers;
+begin
+tmp.carrier_pcb_rev_i := f_x_to_zero(left.carrier_pcb_rev_i) or f_x_to_zero(right.carrier_pcb_rev_i);
+tmp.carrier_reserved_i := f_x_to_zero(left.carrier_reserved_i) or f_x_to_zero(right.carrier_reserved_i);
+tmp.carrier_type_i := f_x_to_zero(left.carrier_type_i) or f_x_to_zero(right.carrier_type_i);
+tmp.stat_fmc0_pres_i := f_x_to_zero(left.stat_fmc0_pres_i) or f_x_to_zero(right.stat_fmc0_pres_i);
+tmp.stat_fmc1_pres_i := f_x_to_zero(left.stat_fmc1_pres_i) or f_x_to_zero(right.stat_fmc1_pres_i);
+tmp.stat_sys_pll_lck_i := f_x_to_zero(left.stat_sys_pll_lck_i) or f_x_to_zero(right.stat_sys_pll_lck_i);
+tmp.stat_ddr0_cal_done_i := f_x_to_zero(left.stat_ddr0_cal_done_i) or f_x_to_zero(right.stat_ddr0_cal_done_i);
+tmp.stat_ddr1_cal_done_i := f_x_to_zero(left.stat_ddr1_cal_done_i) or f_x_to_zero(right.stat_ddr1_cal_done_i);
+return tmp;
+end function;
+end package body;
--- a/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
+++ b/hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
@@ -8,7 +8,7 @@
 --            : Dimitrios Lampridis  <dimitrios.lampridis@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2013-07-04
-- Last update: 2016-06-09
+-- Last update: 2016-06-16
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
 -- Description: Top entity of FMC ADC 100Ms/s design for Simple VME FMC
@@ -52,6 +52,7 @@ use work.fmc_adc_mezzanine_pkg.all;
 use work.sdb_meta_pkg.all;
 use work.xvme64x_core_pkg.all;
 use work.timetag_core_pkg.all;
+use work.carrier_csr_wbgen2_pkg.all;


 entity svec_top_fmc_adc_100Ms is
@@ -263,29 +264,19 @@ architecture rtl of svec_top_fmc_adc_100Ms is
  ------------------------------------------------------------------------------
  component carrier_csr is
    port (
-      rst_n_i                          : in  std_logic;
-      clk_sys_i                        : in  std_logic;
-      wb_adr_i                         : in  std_logic_vector(1 downto 0);
-      wb_dat_i                         : in  std_logic_vector(31 downto 0);
-      wb_dat_o                         : out std_logic_vector(31 downto 0);
-      wb_cyc_i                         : in  std_logic;
-      wb_sel_i                         : in  std_logic_vector(3 downto 0);
-      wb_stb_i                         : in  std_logic;
-      wb_we_i                          : in  std_logic;
-      wb_ack_o                         : out std_logic;
-      wb_stall_o                       : out std_logic;
-      carrier_csr_carrier_pcb_rev_i    : in  std_logic_vector(4 downto 0);
-      carrier_csr_carrier_reserved_i   : in  std_logic_vector(10 downto 0);
-      carrier_csr_carrier_type_i       : in  std_logic_vector(15 downto 0);
-      carrier_csr_stat_fmc0_pres_i     : in  std_logic;
-      carrier_csr_stat_fmc1_pres_i     : in  std_logic;
-      carrier_csr_stat_sys_pll_lck_i   : in  std_logic;
-      carrier_csr_stat_ddr0_cal_done_i : in  std_logic;
-      carrier_csr_stat_ddr1_cal_done_i : in  std_logic;
-      carrier_csr_ctrl_fp_leds_man_o   : out std_logic_vector(15 downto 0);
-      carrier_csr_ctrl_wrabbit_en_o    : out std_logic;
-      carrier_csr_rst_fmc0_o           : out std_logic;
-      carrier_csr_rst_fmc1_o           : out std_logic); 
+      rst_n_i    : in  std_logic;
+      clk_sys_i  : in  std_logic;
+      wb_adr_i   : in  std_logic_vector(1 downto 0);
+      wb_dat_i   : in  std_logic_vector(31 downto 0);
+      wb_dat_o   : out std_logic_vector(31 downto 0);
+      wb_cyc_i   : in  std_logic;
+      wb_sel_i   : in  std_logic_vector(3 downto 0);
+      wb_stb_i   : in  std_logic;
+      wb_we_i    : in  std_logic;
+      wb_ack_o   : out std_logic;
+      wb_stall_o : out std_logic;
+      regs_i     : in  t_carrier_csr_in_registers;
+      regs_o     : out t_carrier_csr_out_registers);
  end component carrier_csr;

  component fmc_adc_eic
@@ -551,6 +542,10 @@ architecture rtl of svec_top_fmc_adc_100Ms is
  -- White Rabbit
  signal wrabbit_en : std_logic;

+  -- IO for CSR registers
+  signal csr_regin  : t_carrier_csr_in_registers;
+  signal csr_regout : t_carrier_csr_out_registers;
+
 begin


@@ -821,30 +816,34 @@ begin
  ------------------------------------------------------------------------------
  cmp_carrier_csr : carrier_csr
    port map(
-      rst_n_i                          => sys_rst_125_n,
-      clk_sys_i                        => sys_clk_125,
-      wb_adr_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).adr(3 downto 2),  -- cnx_master_out.adr is byte address
-      wb_dat_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).dat,
-      wb_dat_o                         => cnx_master_in(c_WB_SLAVE_SVEC_CSR).dat,
-      wb_cyc_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).cyc,
-      wb_sel_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).sel,
-      wb_stb_i                         => cnx_master_out(c_WB_SLAVE_SVEC_CSR).stb,
-      wb_we_i                          => cnx_master_out(c_WB_SLAVE_SVEC_CSR).we,
-      wb_ack_o                         => cnx_master_in(c_WB_SLAVE_SVEC_CSR).ack,
-      wb_stall_o                       => open,
-      carrier_csr_carrier_pcb_rev_i    => pcbrev_i,
-      carrier_csr_carrier_reserved_i   => (others => '0'),
-      carrier_csr_carrier_type_i       => c_CARRIER_TYPE,
-      carrier_csr_stat_fmc0_pres_i     => fmc0_prsnt_m2c_n_i,
-      carrier_csr_stat_fmc1_pres_i     => fmc1_prsnt_m2c_n_i,
-      carrier_csr_stat_sys_pll_lck_i   => sys_clk_pll_locked,
-      carrier_csr_stat_ddr0_cal_done_i => ddr0_calib_done,
-      carrier_csr_stat_ddr1_cal_done_i => ddr1_calib_done,
-      carrier_csr_ctrl_fp_leds_man_o   => led_state_man,
-      carrier_csr_ctrl_wrabbit_en_o    => wrabbit_en,
-      carrier_csr_rst_fmc0_o           => sw_rst_fmc0,
-      carrier_csr_rst_fmc1_o           => sw_rst_fmc1
-      );
+      rst_n_i    => sys_rst_125_n,
+      clk_sys_i  => sys_clk_125,
+      wb_adr_i   => cnx_master_out(c_WB_SLAVE_SVEC_CSR).adr(3 downto 2),  -- cnx_master_out.adr is byte address
+      wb_dat_i   => cnx_master_out(c_WB_SLAVE_SVEC_CSR).dat,
+      wb_dat_o   => cnx_master_in(c_WB_SLAVE_SVEC_CSR).dat,
+      wb_cyc_i   => cnx_master_out(c_WB_SLAVE_SVEC_CSR).cyc,
+      wb_sel_i   => cnx_master_out(c_WB_SLAVE_SVEC_CSR).sel,
+      wb_stb_i   => cnx_master_out(c_WB_SLAVE_SVEC_CSR).stb,
+      wb_we_i    => cnx_master_out(c_WB_SLAVE_SVEC_CSR).we,
+      wb_ack_o   => cnx_master_in(c_WB_SLAVE_SVEC_CSR).ack,
+      wb_stall_o => open,
+      regs_i     => csr_regin,
+      regs_o     => csr_regout);
+
+  csr_regin.carrier_pcb_rev_i    <= pcbrev_i;
+  csr_regin.carrier_reserved_i   <= (others => '0');
+  csr_regin.carrier_type_i       <= c_CARRIER_TYPE;
+  csr_regin.stat_fmc0_pres_i     <= fmc0_prsnt_m2c_n_i;
+  csr_regin.stat_fmc1_pres_i     <= fmc1_prsnt_m2c_n_i;
+  csr_regin.stat_sys_pll_lck_i   <= sys_clk_pll_locked;
+  csr_regin.stat_ddr0_cal_done_i <= ddr0_calib_done;
+  csr_regin.stat_ddr1_cal_done_i <= ddr1_calib_done;
+
+  led_state_man <= csr_regout.ctrl_fp_leds_man_o;
+  wrabbit_en    <= csr_regout.ctrl_wrabbit_en_o;
+  sw_rst_fmc0   <= csr_regout.rst_fmc0_o;
+  sw_rst_fmc1   <= csr_regout.rst_fmc1_o;
+

  -- Unused wishbone signals
  cnx_master_in(c_WB_SLAVE_SVEC_CSR).err   <= '0';

--- a/hdl/svec/wb_gen/Makefile
+++ b/hdl/svec/wb_gen/Makefile
 WBGEN2=$(shell which wbgen2)
 RTL=../rtl/
-TEX=../../../doc/manual//svec/
+TEX=../../../doc/manual/svec/

 carrier_csr:
-	$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
+	$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
 	$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
--- a/hdl/svec/wb_gen/carrier_csr.h
+++ b/hdl/svec/wb_gen/carrier_csr.h
@@ -3,7 +3,7 @@

  * File           : carrier_csr.h
  * Author         : auto-generated by wbgen2 from carrier_csr.wb
-  * Created        : Thu Jun  9 13:46:23 2016
+  * Created        : Thu Jun 16 17:11:57 2016
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
@@ -14,7 +14,11 @@
 #ifndef __WBGEN2_REGDEFS_CARRIER_CSR_WB
 #define __WBGEN2_REGDEFS_CARRIER_CSR_WB

+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
 #include <inttypes.h>
+#endif

 #if defined( __GNUC__)
 #define PACKED __attribute__ ((packed))