sim: Add svec simulation files.

7f9b4cef · Matthieu Cattin · 3f5a3b23 · 7f9b4cef · 7f9b4cef · 7f9b4cef
Commit 7f9b4cef authored Jul 19, 2013 by Matthieu Cattin
19 changed files
--- a/hdl/svec/sim/2048Mb_ddr3/Manifest.py
+++ b/hdl/svec/sim/2048Mb_ddr3/Manifest.py
+files = ["ddr3.v"]
+
+vlog_opt = "+define+sg15E +define+x16"
--- a/hdl/svec/sim/2048Mb_ddr3/ddr3.svh
+++ b/hdl/svec/sim/2048Mb_ddr3/ddr3.svh
+
+`define DECLARE_DDR(__nb) \
+    logic        ddr``__nb``_we_n; \
+    wire  [1:0]  ddr``__nb``_dqs_p; \
+    wire  [1:0]  ddr``__nb``_dqs_n; \
+    wire  [1:0]  ddr``__nb``_dm; \
+    logic        ddr``__nb``_reset_n; \
+    logic        ddr``__nb``_ras_n; \
+    logic        ddr``__nb``_odt; \
+    logic        ddr``__nb``_cke; \
+    logic        ddr``__nb``_ck_p; \
+    logic        ddr``__nb``_ck_n; \
+    logic        ddr``__nb``_cas_n; \
+    wire  [15:0] ddr``__nb``_dq; \
+    logic [2:0]  ddr``__nb``_ba; \
+    logic [13:0] ddr``__nb``_a; \
+    wire         ddr``__nb``_zio; \
+    wire         ddr``__nb``_rzq; \
+    ddr3 cmp_ddr``__nb`` ( \
+        .rst_n(ddr``__nb``_reset_n), \
+        .ck(ddr``__nb``_ck_p), \
+        .ck_n(ddr``__nb``_ck_n), \
+        .cke(ddr``__nb``_cke), \
+        .cs_n(1'b0), \
+        .ras_n(ddr``__nb``_ras_n), \
+        .cas_n(ddr``__nb``_cas_n), \
+        .we_n(ddr``__nb``_we_n), \
+        .dm_tdqs(ddr``__nb``_dm), \
+        .ba(ddr``__nb``_ba), \
+        .addr(ddr``__nb``_a), \
+        .dq(ddr``__nb``_dq), \
+        .dqs(ddr``__nb``_dqs_p), \
+        .dqs_n(ddr``__nb``_dqs_n), \
+        .odt(ddr``__nb``_odt) \
+        );
+
+
+`define WIRE_DDR(__nb) \
+    .ddr``__nb``_we_n_o(ddr``__nb``_we_n), \
+    .ddr``__nb``_udqs_p_b(ddr``__nb``_dqs_p[1]), \
+    .ddr``__nb``_udqs_n_b(ddr``__nb``_dqs_n[1]), \
+    .ddr``__nb``_udm_o(ddr``__nb``_dm[1]), \
+    .ddr``__nb``_reset_n_o(ddr``__nb``_reset_n), \
+    .ddr``__nb``_ras_n_o(ddr``__nb``_ras_n), \
+    .ddr``__nb``_odt_o(ddr``__nb``_odt), \
+    .ddr``__nb``_ldqs_p_b(ddr``__nb``_dqs_p[0]), \
+    .ddr``__nb``_ldqs_n_b(ddr``__nb``_dqs_n[0]), \
+    .ddr``__nb``_ldm_o(ddr``__nb``_dm[0]), \
+    .ddr``__nb``_cke_o(ddr``__nb``_cke), \
+    .ddr``__nb``_ck_p_o(ddr``__nb``_ck_p), \
+    .ddr``__nb``_ck_n_o(ddr``__nb``_ck_n), \
+    .ddr``__nb``_cas_n_o(ddr``__nb``_cas_n), \
+    .ddr``__nb``_dq_b(ddr``__nb``_dq), \
+    .ddr``__nb``_ba_o(ddr``__nb``_ba), \
+    .ddr``__nb``_a_o(ddr``__nb``_a), \
+    .ddr``__nb``_zio_b(ddr``__nb``_zio), \
+    .ddr``__nb``_rzq_b(ddr``__nb``_rzq),
\ No newline at end of file
--- a/hdl/svec/sim/2048Mb_ddr3/ddr3.v
+++ b/hdl/svec/sim/2048Mb_ddr3/ddr3.v
--- a/hdl/svec/sim/2048Mb_ddr3/ddr3_mcp.v
+++ b/hdl/svec/sim/2048Mb_ddr3/ddr3_mcp.v
+/****************************************************************************************
+*
+*    File Name:  ddr3_mcp.v
+*
+* Dependencies:  ddr3.v, ddr3_parameters.vh
+*
+*  Description:  Micron SDRAM DDR3 (Double Data Rate 3) multi-chip package model
+*
+*   Disclaimer   This software code and all associated documentation, comments or other 
+*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+*                limitation of liability for consequential or incidental damages, the 
+*                above limitation may not apply to you.
+*
+*                Copyright 2003 Micron Technology, Inc. All rights reserved.
+*
+****************************************************************************************/
+ `timescale 1ps / 1ps
+
+module ddr3_mcp (
+    rst_n,
+    ck,
+    ck_n,
+    cke,
+    cs_n,
+    ras_n,
+    cas_n,
+    we_n,
+    dm_tdqs,
+    ba,
+    addr,
+    dq,
+    dqs,
+    dqs_n,
+    tdqs_n,
+    odt
+);
+
+    `include "ddr3_parameters.vh"
+
+    // Declare Ports
+    input   rst_n;
+    input   ck;
+    input   ck_n;
+    input   [CS_BITS-1:0]   cke;
+    input   [CS_BITS-1:0]   cs_n;
+    input   ras_n;
+    input   cas_n;
+    input   we_n;
+    inout   [DM_BITS-1:0]   dm_tdqs;
+    input   [BA_BITS-1:0]   ba;
+    input   [ADDR_BITS-1:0] addr;
+    inout   [DQ_BITS-1:0]   dq;
+    inout   [DQS_BITS-1:0]  dqs;
+    inout   [DQS_BITS-1:0]  dqs_n;
+    output  [DQS_BITS-1:0]  tdqs_n;
+    input   [CS_BITS-1:0]   odt;
+
+    wire [RANKS-1:0] cke_mcp = cke;
+    wire [RANKS-1:0] cs_n_mcp = cs_n;
+    wire [RANKS-1:0] odt_mcp = odt;
+
+    ddr3 rank [RANKS-1:0] (
+        rst_n,
+        ck, 
+        ck_n,
+        cke_mcp, 
+        cs_n_mcp,
+        ras_n, 
+        cas_n, 
+        we_n, 
+        dm_tdqs, 
+        ba, 
+        addr, 
+        dq, 
+        dqs,
+        dqs_n,
+        tdqs_n,
+        odt_mcp
+    );
+
+endmodule
--- a/hdl/svec/sim/2048Mb_ddr3/ddr3_module.v
+++ b/hdl/svec/sim/2048Mb_ddr3/ddr3_module.v
--- a/hdl/svec/sim/2048Mb_ddr3/ddr3_parameters.vh
+++ b/hdl/svec/sim/2048Mb_ddr3/ddr3_parameters.vh
--- a/hdl/svec/sim/2048Mb_ddr3/readme.txt
+++ b/hdl/svec/sim/2048Mb_ddr3/readme.txt
+Disclaimer of Warranty:
+-----------------------
+This software code and all associated documentation, comments or other 
+information (collectively "Software") is provided "AS IS" without 
+warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+DAMAGES. Because some jurisdictions prohibit the exclusion or 
+limitation of liability for consequential or incidental damages, the 
+above limitation may not apply to you.
+
+Copyright 2003 Micron Technology, Inc. All rights reserved.
+
+Getting Started:
+----------------
+Unzip the included files to a folder.
+Compile ddr3.v and tb.v in a verilog simulator.
+Simulate the top level test bench tb.
+Or, if you are using the ModelSim simulator, type "do tb.do" at the prompt.
+
+File Descriptions:
+------------------
+ddr3.v              -ddr3 model
+ddr3_mcp.v          -structural wrapper for ddr3 - multi-chip package model
+ddr3_module.v       -structural wrapper for ddr3 - module model
+ddr3_parameters.vh  -file that contains all parameters used by the model
+readme.txt          -this file
+tb.v                -ddr3 model test bench
+subtest.vh          -example test included by the test bench.
+tb.do               -compiles and runs the ddr3 model and test bench
+
+Defining the Speed Grade:
+-------------------------
+The verilog compiler directive "`define" may be used to choose between 
+multiple speed grades supported by the ddr3 model.  Allowable speed 
+grades are listed in the ddr3_parameters.vh file and begin with the 
+letters "sg".  The speed grade is used to select a set of timing 
+parameters for the ddr3 model.  The following are examples of defining 
+the speed grade.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+sg25 ddr3.v
+    VCS         vcs +define+sg25 ddr3.v
+    NC-Verilog  ncverilog +define+sg25 ddr3.v
+
+Defining the Organization:
+--------------------------
+The verilog compiler directive "`define" may be used to choose between 
+multiple organizations supported by the ddr3 model.  Valid 
+organizations include "x4", "x8", and x16, and are listed in the 
+ddr3_parameters.vh file.  The organization is used to select the amount 
+of memory and the port sizes of the ddr3 model.  The following are
+examples of defining the organization.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+x8 ddr3.v
+    NC-Verilog  ncverilog +define+x8 ddr3.v
+    VCS         vcs +define+x8 ddr3.v
+
+All combinations of speed grade and organization are considered valid 
+by the ddr3 model even though a Micron part may not exist for every 
+combination.
+
+Allocating Memory:
+------------------
+An associative array has been implemented to reduce the amount of 
+static memory allocated by the ddr3 model.  Each entry in the 
+associative array is a burst length of eight in size.  The number of 
+entries in the associative array is controlled by the MEM_BITS 
+parameter, and is equal to 2^MEM_BITS.  For example, if the MEM_BITS 
+parameter is equal to 10, the associative array will be large enough 
+to store 1024 writes of burst length 8 to unique addresses.  The 
+following are examples of setting the MEM_BITS parameter to 8.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vsim -GMEM_BITS=8 ddr3
+    NC-Verilog  ncverilog +defparam+ddr3.MEM_BITS=8 ddr3.v
+    VCS         vcs -pvalue+MEM_BITS=8 ddr3.v
+
+It is possible to allocate memory for every address supported by the 
+ddr3 model by using the verilog compiler directive "`define MAX_MEM".
+This procedure will improve simulation performance at the expense of 
+system memory.  The following are examples of allocating memory for
+every address.
+
+    Simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+MAX_MEM ddr3.v
+    NC-Verilog  ncverilog +define+MAX_MEM ddr3.v
+    VCS         vcs +define+MAX_MEM ddr3.v
+
+**********************************************************************
+The following information is provided to assist the modeling engineer 
+in creating multi-chip package (mcp) models.  ddr3_mcp.v is a 
+structural wrapper that instantiates ddr3 models.  This wrapper can be 
+used to create single, dual, or quad rank mcp models.  From the 
+perspective of the model, the only item that needs to be defined is the 
+number of ranks.
+**********************************************************************
+
+Defining the Number of Ranks in a multi-chip package:
+----------------------------------------------------
+The verilog compiler directive "`define" may be used to choose between 
+single, dual, and quad rank mcp configurations.  The default is single 
+rank if nothing is defined.  Dual rank configuration can be selected by 
+defining "DUAL_RANK" when the ddr3_mcp is compiled.  Quad rank 
+configuration can be selected by defining "QUAD_RANK" when the ddr3_mcp 
+is compiled.  The following are examples of defining a dual rank mcp 
+configuration.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+DUAL_RANK ddr3.v ddr3_mcp.v
+    NC-Verilog  ncverilog +define+DUAL_RANK ddr3.v ddr3_mcp.v
+    VCS         vcs +define+DUAL_RANK ddr3.v ddr3_mcp.v
+
+**********************************************************************
+The following information is provided to assist the modeling engineer 
+in creating DIMM models.  ddr3_module.v is a structural wrapper that 
+instantiates ddr3 models.  This wrapper can be used to create UDIMM, 
+RDIMM or SODIMM models.  Other form factors are not supported 
+(MiniDIMM, VLP DIMM, etc.).  From the perspective of the model, the 
+items that need to be defined are the number of ranks, the module 
+type, and the presence of ECC.  All combinations of ranks, module 
+type, and ECC are considered valid by the ddr3_module model even 
+though a Micron part may not exist for every combination.
+**********************************************************************
+
+Defining the Number of Ranks on a module:
+----------------------------------------
+The verilog compiler directive "`define" may be used to choose between 
+single, dual, and quad rank module configurations.  The default is single 
+rank if nothing is defined.  Dual rank configuration can be selected by 
+defining "DUAL_RANK" when the ddr3_module is compiled.  Quad rank 
+configuration can be selected by defining "QUAD_RANK" when the ddr3_module 
+is compiled.  The following are examples of defining a dual rank module 
+configuration.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+DUAL_RANK ddr3.v ddr3_module.v
+    NC-Verilog  ncverilog +define+DUAL_RANK ddr3.v ddr3_module.v
+    VCS         vcs +define+DUAL_RANK ddr3.v ddr3_module.v
+
+Defining the Module Type:
+-----------------------------------
+The verilog compiler directive "`define" may be used to choose between 
+UDIMM, RDIMM, and SODIMM module configurations.  The default is 
+unregistered (UDIMM) if nothing is defined.  SODIMM configuration can be 
+selected by defining "SODIMM" when the ddr3_module is compiled.  Registered 
+configuration can be selected by defining "RDIMM" when the ddr3_module is 
+compiled.  The following are examples of defining a registered module 
+configuration.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+RDIMM ddr3.v ddr3_module.v
+    NC-Verilog  ncverilog +define+RDIMM ddr3.v ddr3_module.v
+    VCS         vcs +define+RDIMM ddr3.v ddr3_module.v
+
+Defining the ECC for a module:
+-----------------------------
+The verilog compiler directive "`define" may be used to choose between 
+ECC and nonECC module configurations.  The default is nonECC if nothing 
+is defined.  ECC configuration can be selected by defining "ECC" when 
+the ddr3_module is compiled.  The following are examples of defining an
+ECC module configuration.
+
+    simulator   command line
+    ---------   ------------
+    ModelSim    vlog +define+ECC ddr3.v ddr3_module.v
+    NC-Verilog  ncverilog +define+ECC ddr3.v ddr3_module.v
+    VCS         vcs +define+ECC ddr3.v ddr3_module.v
--- a/hdl/svec/sim/2048Mb_ddr3/subtest.vh
+++ b/hdl/svec/sim/2048Mb_ddr3/subtest.vh
--- a/hdl/svec/sim/2048Mb_ddr3/tb.do
+++ b/hdl/svec/sim/2048Mb_ddr3/tb.do
+#########################################################################################
+#
+#   Disclaimer   This software code and all associated documentation, comments or other 
+#  of Warranty:  information (collectively "Software") is provided "AS IS" without 
+#                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
+#                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
+#                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
+#                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
+#                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
+#                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
+#                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
+#                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
+#                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
+#                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
+#                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
+#                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
+#                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
+#                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
+#                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
+#                DAMAGES. Because some jurisdictions prohibit the exclusion or 
+#                limitation of liability for consequential or incidental damages, the 
+#                above limitation may not apply to you.
+#
+#                Copyright 2003 Micron Technology, Inc. All rights reserved.
+#
+#########################################################################################
+
+vlog -novopt ddr3.v tb.v
+vsim -novopt tb
+add wave -p sdramddr3/*
+run -all
--- a/hdl/svec/sim/2048Mb_ddr3/tb.v
+++ b/hdl/svec/sim/2048Mb_ddr3/tb.v
--- a/hdl/svec/sim/testbench/Makefile
+++ b/hdl/svec/sim/testbench/Makefile
--- a/hdl/svec/sim/testbench/Manifest.py
+++ b/hdl/svec/sim/testbench/Manifest.py
+action = "simulation"
+target = "xilinx"
+
+vlog_opt="+incdir+../vme64x_bfm +incdir+../2048Mb_ddr3"
+
+files = [ "main.sv",
+          "../../../ip_cores/adc_sync_fifo.vhd",
+          "../../../ip_cores/multishot_dpram.vhd",
+          "../../../ip_cores/wb_ddr_fifo.vhd",
+          "../../../ip_cores/adc_serdes.vhd",
+          "../../../ip_cores/monostable/monostable_rtl.vhd",
+          "../../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd",
+          "../../../ip_cores/utils/utils_pkg.vhd"]
+
+modules = { "local" :  [ "../../rtl",
+                         "../2048Mb_ddr3",
+                         "../../../adc/rtl",
+                         "../../../ip_cores/timetag_core/rtl"],
+            "git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git::sdb_extension",
+                      "git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::svec_bank4_64b_32b_bank5_64b_32b",
+                      "git://ohwr.org/hdl-core-lib/vme64x-core.git::master"]}
+
+fetchto="../../../ip_cores"
--- a/hdl/svec/sim/testbench/fmc.svh
+++ b/hdl/svec/sim/testbench/fmc.svh
+
+`define DECLARE_FMC(__nb) \
+    logic       adc``__nb``_ext_trigger_p; \
+    logic       adc``__nb``_ext_trigger_n; \
+    logic       adc``__nb``_dco_p; \
+    logic       adc``__nb``_dco_n; \
+    logic       adc``__nb``_fr_p; \
+    logic       adc``__nb``_fr_n; \
+    logic [3:0] adc``__nb``_outa_p; \
+    logic [3:0] adc``__nb``_outa_n; \
+    logic [3:0] adc``__nb``_outb_p; \
+    logic [3:0] adc``__nb``_outb_n; \
+    logic       adc``__nb``_spi_din; \
+    logic       adc``__nb``_spi_dout; \
+    logic       adc``__nb``_spi_sck; \
+    logic       adc``__nb``_spi_cs_adc_n; \
+    logic       adc``__nb``_spi_cs_dac1_n; \
+    logic       adc``__nb``_spi_cs_dac2_n; \
+    logic       adc``__nb``_spi_cs_dac3_n; \
+    logic       adc``__nb``_spi_cs_dac4_n; \
+    logic       adc``__nb``_gpio_dac_clr_n; \
+    logic       adc``__nb``_gpio_led_acq; \
+    logic       adc``__nb``_gpio_led_trig; \
+    logic [6:0] adc``__nb``_gpio_ssr_ch1; \
+    logic [6:0] adc``__nb``_gpio_ssr_ch2; \
+    logic [6:0] adc``__nb``_gpio_ssr_ch3; \
+    logic [6:0] adc``__nb``_gpio_ssr_ch4; \
+    logic       adc``__nb``_gpio_si570_oe; \
+    wire        adc``__nb``_si570_scl; \
+    wire        adc``__nb``_si570_sda; \
+    wire        adc``__nb``_one_wire; \
+    logic       fmc``__nb``_prsnt_m2c_n; \
+    wire        fmc``__nb``_scl; \
+    wire        fmc``__nb``_sda;
+
+
+`define WIRE_FMC(__nb) \
+      .adc``__nb``_ext_trigger_p_i(adc``__nb``_ext_trigger_p), \
+      .adc``__nb``_ext_trigger_n_i(adc``__nb``_ext_trigger_n), \
+      .adc``__nb``_dco_p_i(adc``__nb``_dco_p), \
+      .adc``__nb``_dco_n_i(adc``__nb``_dco_n), \
+      .adc``__nb``_fr_p_i(adc``__nb``_fr_p), \
+      .adc``__nb``_fr_n_i(adc``__nb``_fr_n), \
+      .adc``__nb``_outa_p_i(adc``__nb``_outa_p), \
+      .adc``__nb``_outa_n_i(adc``__nb``_outa_n), \
+      .adc``__nb``_outb_p_i(adc``__nb``_outb_p), \
+      .adc``__nb``_outb_n_i(adc``__nb``_outb_n), \
+      .adc``__nb``_spi_din_i(adc``__nb``_spi_din), \
+      .adc``__nb``_spi_dout_o(adc``__nb``_spi_dout), \
+      .adc``__nb``_spi_sck_o(adc``__nb``_spi_sck), \
+      .adc``__nb``_spi_cs_adc_n_o(adc``__nb``_spi_cs_adc_n), \
+      .adc``__nb``_spi_cs_dac1_n_o(adc``__nb``_spi_cs_dac1_n), \
+      .adc``__nb``_spi_cs_dac2_n_o(adc``__nb``_spi_cs_dac2_n), \
+      .adc``__nb``_spi_cs_dac3_n_o(adc``__nb``_spi_cs_dac3_n), \
+      .adc``__nb``_spi_cs_dac4_n_o(adc``__nb``_spi_cs_dac4_n), \
+      .adc``__nb``_gpio_dac_clr_n_o(adc``__nb``_gpio_dac_clr_n), \
+      .adc``__nb``_gpio_led_acq_o(adc``__nb``_gpio_led_acq), \
+      .adc``__nb``_gpio_led_trig_o(adc``__nb``_gpio_led_trig), \
+      .adc``__nb``_gpio_ssr_ch1_o(adc``__nb``_gpio_ssr_ch1), \
+      .adc``__nb``_gpio_ssr_ch2_o(adc``__nb``_gpio_ssr_ch2), \
+      .adc``__nb``_gpio_ssr_ch3_o(adc``__nb``_gpio_ssr_ch3), \
+      .adc``__nb``_gpio_ssr_ch4_o(adc``__nb``_gpio_ssr_ch4), \
+      .adc``__nb``_gpio_si570_oe_o(adc``__nb``_gpio_si570_oe), \
+      .adc``__nb``_si570_scl_b(adc``__nb``_si570_scl), \
+      .adc``__nb``_si570_sda_b(adc``__nb``_si570_sda), \
+      .adc``__nb``_one_wire_b(adc``__nb``_one_wire), \
+      .fmc``__nb``_prsnt_m2c_n_i(fmc``__nb``_prsnt_m2c_n), \
+      .fmc``__nb``_scl_b(fmc``__nb``_scl), \
+      .fmc``__nb``_sda_b(fmc``__nb``_sda),
\ No newline at end of file
--- a/hdl/svec/sim/testbench/main.sv
+++ b/hdl/svec/sim/testbench/main.sv
+`include "vme64x_bfm.svh"
+`include "svec_vme_buffers.svh"
+`include "fmc.svh"
+`include "ddr3.svh"
+
+module main;
+
+   reg rst_n = 0;
+   reg clk_20m = 0;
+
+   always #25ns clk_20m <= ~clk_20m;
+
+   initial begin
+      repeat(20) @(posedge clk_20m);
+      rst_n = 1;
+   end
+
+   IVME64X VME(rst_n);
+
+   `DECLARE_VME_BUFFERS(VME.slave);
+
+   `DECLARE_DDR(0);
+   `DECLARE_DDR(1);
+
+   `DECLARE_FMC(0);
+   `DECLARE_FMC(1);
+
+   logic [1:0] fp_led_line_oen;
+   logic [1:0] fp_led_line;
+   logic [3:0] fp_led_column;
+   wire        carrier_scl;
+   wire        carrier_sda;
+   wire        carrier_one_wire;
+
+   svec_top_fmc_adc_100Ms
+     #(
+       .g_SIMULATION("TRUE"),
+       .g_CALIB_SOFT_IP("FALSE")
+       )
+   DUT
+     (
+      .clk_20m_vcxo_i(clk_20m),
+      .rst_n_i(rst_n),
+
+      .fp_led_line_oen_o(fp_led_line_oen),
+      .fp_led_line_o(fp_led_line),
+      .fp_led_column_o(fp_led_column),
+      .carrier_scl_b(carrier_scl),
+      .carrier_sda_b(carrier_sda),
+      .pcbrev_i(5'b00001),
+      .carrier_one_wire_b(carrier_one_wire),
+
+      `WIRE_DDR(0)
+      `WIRE_DDR(1)
+
+      `WIRE_FMC(0)
+      `WIRE_FMC(1)
+
+      `WIRE_VME_PINS(8) // slot number in parameter
+      );
+
+   task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
+      uint64_t rv;
+
+      /* map func0 to 0x80000000, A32 */
+
+      acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
+      acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
+      acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
+      acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
+
+
+      acc.set_default_modifiers(A32 | D32 | SINGLE);
+   endtask // init_vme64x_core
+
+
+   initial begin
+      uint64_t d;
+      uint32_t wr_data;
+
+      int i, result;
+
+      CBusAccessor_VME64x acc = new(VME.master);
+
+
+      #20us;
+      init_vme64x_core(acc);
+
+
+      acc.write('h2200, 'h0, A32|SINGLE|D32);
+      for(i=0; i<5; i++)
+        begin
+           acc.read('h2100, d, A32|SINGLE|D32);
+           $display("Read %d: 0x%x\n", i, d);
+        end
+
+      acc.write('h2200, 'h0, A32|SINGLE|D32);
+      for(i=0; i<2; i++)
+        begin
+           wr_data = i;
+           acc.write('h2100, wr_data, A32|SINGLE|D32);
+           $display("Write %d: 0x%x\n", i, wr_data);
+        end
+
+      acc.write('h2200, 'h0, A32|SINGLE|D32);
+      for(i=0; i<5; i++)
+        begin
+           acc.read('h2100, d, A32|SINGLE|D32);
+           $display("Read %d: 0x%x\n", i, d);
+        end
+
+   end
+
+
+endmodule // main
+
+
+
--- a/hdl/svec/sim/testbench/svec.do
+++ b/hdl/svec/sim/testbench/svec.do
+vsim -novopt -t 1ps main
+log -r /*
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+#view wave
+#view transcript
+do wave.do
+radix -hexadecimal
+
+run 40 us
+
+
+
--- a/hdl/svec/sim/testbench/wave.do
+++ b/hdl/svec/sim/testbench/wave.do
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /main/DUT/sys_clk_62_5
+add wave -noupdate /main/DUT/sys_clk_125
+add wave -noupdate /main/DUT/sys_rst_n
+add wave -noupdate -divider {wb vme}
+add wave -noupdate /main/DUT/cnx_slave_in(0).cyc
+add wave -noupdate /main/DUT/cnx_slave_in(0).stb
+add wave -noupdate /main/DUT/cnx_slave_in(0).we
+add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_in(0).adr
+add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_in(0).dat
+add wave -noupdate /main/DUT/cnx_slave_out(0).ack
+add wave -noupdate /main/DUT/cnx_slave_out(0).stall
+add wave -noupdate -radix hexadecimal /main/DUT/cnx_slave_out(0).dat
+add wave -noupdate -divider {wb ddr0 addr}
+add wave -noupdate /main/DUT/cnx_master_out(6).cyc
+add wave -noupdate /main/DUT/cnx_master_out(6).stb
+add wave -noupdate /main/DUT/cnx_master_out(6).we
+add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out(6).adr
+add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out(6).dat
+add wave -noupdate /main/DUT/cnx_master_in(6).ack
+add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_in(6).dat
+add wave -noupdate -radix hexadecimal /main/DUT/ddr0_addr_cnt
+add wave -noupdate -divider {wb ddr0 data}
+add wave -noupdate /main/DUT/cnx_master_out(5).cyc
+add wave -noupdate /main/DUT/cnx_master_out(5).stb
+add wave -noupdate /main/DUT/cnx_master_out(5).we
+add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out(5).adr
+add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_out(5).dat
+add wave -noupdate /main/DUT/cnx_master_in(5).ack
+add wave -noupdate -radix hexadecimal /main/DUT/cnx_master_in(5).dat
+add wave -noupdate /main/DUT/ddr0_wb_cyc_d
+add wave -noupdate /main/DUT/ddr0_wb_cyc_fe
+add wave -noupdate -divider {ddr0 ctrl wb1}
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_we_f_edge
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_stb_f_edge
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_cyc_r_edge
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_cyc_f_edge
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_stall_o
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_data_o
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_data_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_addr_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/wb_addr_d
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_underrun_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_mask_o
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_mask
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_full_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_en
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_empty_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_data
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_wr_count_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_overflow_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_full_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_error_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_en
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_empty_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_data_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_rd_count_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_instr
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_full_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_en_r_edge
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_en
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_empty_i
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_byte_addr
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_cmd_bl
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/ddr_burst_cnt
+add wave -noupdate -radix hexadecimal /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wb_1/addr_shift
+add wave -noupdate /main/DUT/cmp_ddr_ctrl_bank4/cmp_ddr3_ctrl_wrapper/gen_svec_bank4_64b_32b/cmp_ddr3_ctrl/memc4_wrapper_inst/memc4_mcb_raw_wrapper_inst/MCB_SYSRST
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {29753000 ps} 0}
+configure wave -namecolwidth 454
+configure wave -valuecolwidth 100
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {29677041 ps} {30055236 ps}
--- a/hdl/svec/sim/vme64x_bfm/components/sn74vmeh22501.v
+++ b/hdl/svec/sim/vme64x_bfm/components/sn74vmeh22501.v
+`timescale 1ns/1ns 
+
+module sn74vmeh22501 (
+    input   oeab1,
+            oeby1_n,
+            a1,
+    output  y1,
+    inout   b1,
+
+    input   oeab2,
+            oeby2_n,
+            a2,
+    output  y2,
+    inout   b2,
+
+    input   oe_n,
+    input   dir,    
+            clkab,
+            le,
+            clkba,
+    inout   [1:8] a3,
+    inout   [1:8] b3);
+
+assign b1   = oeab1   ? a1      : 1'bz;
+assign y1   = oeby1_n ? 1'bz    : b1;
+
+assign b2   = oeab2   ? a2      : 1'bz;
+assign y2   = oeby2_n ? 1'bz    : b2;
+
+reg [1:8] b3LFF;
+always @(posedge clkab) if (~le) b3LFF <= #1 a3;
+always @* if (le) b3LFF = a3;
+assign b3   = (~oe_n && dir) ? b3LFF : 8'hz;
+
+reg [1:8] a3LFF;
+always @(posedge clkba) if (~le) a3LFF <= #1 b3;
+always @* if (le) a3LFF = b3;
+assign a3   = (~oe_n && ~dir) ? a3LFF : 8'hz;
+
+endmodule
+
--- a/hdl/svec/sim/vme64x_bfm/svec_vme_buffers.svh
+++ b/hdl/svec/sim/vme64x_bfm/svec_vme_buffers.svh
+`include "components/sn74vmeh22501.v"
+
+`include "vme64x_bfm.svh"
+
+module bidir_buf(
+    a,
+    b,
+    dir, /* 0: a->b, 1: b->a */
+    oe_n );
+
+   parameter g_width = 1;
+
+   inout [g_width-1:0] a,b;
+   input               dir, oe_n;
+
+   assign b = (!dir && !oe_n) ? a : 'bz;
+   assign a = (dir && !oe_n) ? b : 'bz;
+endmodule // bidir_buf
+
+
+
+
+module svec_vme_buffers (
+    output       VME_AS_n_o,
+    output       VME_RST_n_o,
+    output       VME_WRITE_n_o,
+    output [5:0] VME_AM_o,
+    output [1:0] VME_DS_n_o,
+    output [5:0] VME_GA_o,
+    input        VME_BERR_i,
+    input        VME_DTACK_n_i,
+    input        VME_RETRY_n_i,
+    input        VME_RETRY_OE_i,
+    inout        VME_LWORD_n_b,
+    inout [31:1] VME_ADDR_b,
+    inout [31:0] VME_DATA_b,
+    output       VME_BBSY_n_o,
+    input [6:0]  VME_IRQ_n_i,
+    output       VME_IACKIN_n_o,
+    input        VME_IACKOUT_n_i,
+    output        VME_IACK_n_o,
+    input        VME_DTACK_OE_i,
+    input        VME_DATA_DIR_i,
+    input        VME_DATA_OE_N_i,
+    input        VME_ADDR_DIR_i,
+    input        VME_ADDR_OE_N_i,
+
+    IVME64X.slave slave
+    );
+
+   pullup(slave.as_n);
+   pullup(slave.rst_n);
+   pullup(slave.irq_n[0]);
+   pullup(slave.irq_n[1]);
+   pullup(slave.irq_n[2]);
+   pullup(slave.irq_n[3]);
+   pullup(slave.irq_n[4]);
+   pullup(slave.irq_n[5]);
+   pullup(slave.irq_n[6]);
+   pullup(slave.iack_n);
+   pullup(slave.dtack_n);
+   pullup(slave.retry_n);
+   pullup(slave.ds_n[1]);
+   pullup(slave.ds_n[0]);
+   pullup(slave.lword_n);
+   pullup(slave.berr_n);
+   pullup(slave.write_n);
+   pulldown(slave.bbsy_n);
+   pullup(slave.iackin_n);
+
+   assign VME_RST_n_o = slave.rst_n;
+
+   assign VME_AS_n_o     = slave.as_n;
+   assign VME_GA_o     = slave.ga;
+   assign VME_WRITE_n_o  = slave.write_n;
+   assign VME_AM_o = slave.am;
+   assign VME_DS_n_o = slave.ds_n;
+   assign VME_BBSY_n_o = slave.bbsy_n;
+   assign VME_IACKIN_n_o = slave.iackin_n;
+   assign VME_IACK_n_o = slave.iack_n;
+
+   bidir_buf #(1)  b0 (slave.lword_n, VME_LWORD_n_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
+   bidir_buf #(31) b1 (slave.addr, VME_ADDR_b, VME_ADDR_DIR_i, VME_ADDR_OE_N_i);
+   bidir_buf #(33) b2 (slave.data, VME_DATA_b, VME_DATA_DIR_i, VME_DATA_OE_N_i);
+
+   pulldown(VME_BERR_i);
+   pulldown(VME_ADDR_DIR_i);
+   pulldown(VME_ADDR_OE_N_i);
+   pulldown(VME_DATA_DIR_i);
+   pulldown(VME_DATA_OE_N_i);
+
+
+   assign slave.dtack_n = VME_DTACK_n_i;
+   assign slave.berr_n = ~VME_BERR_i;
+   assign slave.retry_n = VME_RETRY_n_i;
+endmodule
+
+
+`define DECLARE_VME_BUFFERS(iface) \
+    wire VME_AS_n;\
+    wire VME_RST_n;\
+    wire VME_WRITE_n;\
+    wire [5:0] VME_AM;\
+    wire [1:0] VME_DS_n;\
+    wire VME_BERR;\
+    wire VME_DTACK_n;\
+    wire VME_RETRY_n;\
+    wire VME_RETRY_OE;\
+    wire VME_LWORD_n;\
+    wire [31:1]VME_ADDR;\
+    wire [31:0]VME_DATA;\
+    wire VME_BBSY_n;\
+    wire [6:0]VME_IRQ_n;\
+    wire VME_IACKIN_n,VME_IACK_n;\
+    wire VME_IACKOUT_n;\
+    wire VME_DTACK_OE;\
+    wire VME_DATA_DIR;\
+    wire VME_DATA_OE_N;\
+    wire VME_ADDR_DIR;\
+    wire VME_ADDR_OE_N;\
+    svec_vme_buffers U_VME_Bufs ( \
+    .VME_AS_n_o(VME_AS_n),\
+    .VME_RST_n_o(VME_RST_n),\
+    .VME_WRITE_n_o(VME_WRITE_n),\
+    .VME_AM_o(VME_AM),\
+    .VME_DS_n_o(VME_DS_n),\
+    .VME_BERR_i(VME_BERR),\
+    .VME_DTACK_n_i(VME_DTACK_n),\
+    .VME_RETRY_n_i(VME_RETRY_n),\
+    .VME_RETRY_OE_i(VME_RETRY_OE),\
+    .VME_LWORD_n_b(VME_LWORD_n),\
+    .VME_ADDR_b(VME_ADDR),\
+    .VME_DATA_b(VME_DATA),\
+    .VME_IRQ_n_i(VME_IRQ_n),\
+    .VME_IACK_n_o(VME_IACK_n),\
+    .VME_IACKIN_n_o(VME_IACKIN_n),\
+    .VME_IACKOUT_n_i(VME_IACKOUT_n),\
+    .VME_DTACK_OE_i(VME_DTACK_OE),\
+    .VME_DATA_DIR_i(VME_DATA_DIR),\
+    .VME_DATA_OE_N_i(VME_DATA_OE_N),\
+    .VME_ADDR_DIR_i(VME_ADDR_DIR),\
+    .VME_ADDR_OE_N_i(VME_ADDR_OE_N),\
+    .slave(iface)\
+    );
+
+function automatic bit[5:0] _gen_ga(int slot);
+     bit[4:0] slot_id = slot;
+     return {^slot_id, ~slot_id};
+endfunction // _gen_ga
+
+
+
+`define WIRE_VME_PINS(slot_id) \
+    .vme_as_n_i(VME_AS_n),\
+    .vme_sysreset_n_i(VME_RST_n),\
+    .vme_write_n_i(VME_WRITE_n),\
+    .vme_am_i(VME_AM),\
+    .vme_ds_n_i(VME_DS_n),\
+    .vme_ga_i(_gen_ga(slot_id)),\
+    .vme_berr_o(VME_BERR),\
+    .vme_dtack_n_o(VME_DTACK_n),\
+    .vme_retry_n_o(VME_RETRY_n),\
+    .vme_retry_oe_o(VME_RETRY_OE),\
+    .vme_lword_n_b(VME_LWORD_n),\
+    .vme_addr_b(VME_ADDR),\
+    .vme_data_b(VME_DATA),\
+    .vme_irq_n_o(VME_IRQ_n),\
+    .vme_iack_n_i(VME_IACK_n),\
+    .vme_iackin_n_i(VME_IACKIN_n),\
+    .vme_iackout_n_o(VME_IACKOUT_n),\
+    .vme_dtack_oe_o(VME_DTACK_OE),\
+    .vme_data_dir_o(VME_DATA_DIR),\
+    .vme_data_oe_n_o(VME_DATA_OE_N),\
+    .vme_addr_dir_o(VME_ADDR_DIR),\
+    .vme_addr_oe_n_o(VME_ADDR_OE_N)
--- a/hdl/svec/sim/vme64x_bfm/vme64x_bfm.svh
+++ b/hdl/svec/sim/vme64x_bfm/vme64x_bfm.svh