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FMC ADC 100M 14b 4cha - Gateware
Commit 802eda5c authored by Tristan Gingold's avatar Tristan Gingold Committed by Dimitris Lampridis
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testbench: add trigout test.

parent bdbd4607
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Showing with 82 additions and 5 deletions
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ 802eda5c
......@@ -1794,7 +1794,7 @@ begin
gen_trigout_sync : for i in trigout_triggers'range generate
cmp_trigout_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
clk_i => sys_clk_i,
rst_n_i => '1',
data_i => trigout_fs_triggers(i),
synced_o => open,
......@@ -1810,7 +1810,7 @@ begin
generic map (
g_data_width => t_trigout_data'length,
g_size => 16,
g_show_ahead => FALSE,
g_show_ahead => TRUE,
g_with_empty => TRUE,
g_with_full => TRUE,
g_with_almost_empty => FALSE,
......
hdl/rtl/fmc_adc_alt_trigout.vhd
View file @ 802eda5c
......@@ -163,6 +163,7 @@ begin
ts_cycles_rd_o <= '0';
if rd_int = '1' and rd_ack1_int = '0' then
rd_ack1_int <= '1';
reg_rdat_int <= (others => '0');
case wb_i.adr(4 downto 3) is
when "00" =>
case wb_i.adr(2 downto 2) is
......
hdl/rtl/wb_gen/Makefile
View file @ 802eda5c
......@@ -18,4 +18,4 @@ fmc_adc_alt_trigin:
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd --gen-consts=$(SIM)/$@.v -i $@.cheby
fmc_adc_alt_trigout:
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd -i $@.cheby
$(CHEBY) --gen-hdl=$(RTL)/$@.vhd --gen-consts=$(SIM)/$@.v -i $@.cheby
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ 802eda5c
......@@ -4,6 +4,7 @@
`include "fmc_adc_100Ms_csr.v"
`include "timetag_core_regs.v"
`include "fmc_adc_alt_trigin.v"
`include "fmc_adc_alt_trigout.v"
`define SDB_ADDR 'h0000
`define CSR_BASE 'h1000
......@@ -36,6 +37,7 @@ module main;
IVHDWishboneMaster Host ( clk_sys, rst_n );
IVHDWishboneMaster Trigin ( clk_sys, rst_n );
IVHDWishboneMaster Trigout ( clk_sys, rst_n );
wire t_wishbone_slave_data64_out dummy_wb64_out =
'{ack: 1'b1, err: 1'b0, rty: 1'b0, stall: 1'b0, dat: 64'bx};
......@@ -59,6 +61,8 @@ module main;
.acq_cfg_ok_o (),
.wb_trigin_slave_i (Trigin.out),
.wb_trigin_slave_o (Trigin.in),
.wb_trigout_slave_i (Trigout.out),
.wb_trigout_slave_o (Trigout.in),
.ext_trigger_p_i (ext_trig),
.ext_trigger_n_i (~ext_trig),
.adc_dco_p_i (adc0_dco),
......@@ -162,7 +166,7 @@ module main;
initial begin
CWishboneAccessor acc, trigin_acc;
CWishboneAccessor acc, trigin_acc, trigout_acc;
uint64_t val, expected;
$timeformat (-6, 3, "us", 10);
......@@ -172,13 +176,17 @@ module main;
trigin_acc = Trigin.get_accessor();
trigout_acc = Trigout.get_accessor();
#1us;
// Check SDB
expected = 'h5344422d;
acc.read(`SDB_ADDR, val);
if (val != expected)
$fatal (1, "Unable to detect SDB header at offset 0x%8x.", `SDB_ADDR);
// Check status after reset
expected = 'h19;
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
if (val != expected)
......@@ -221,6 +229,21 @@ module main;
$fatal (1, "ADC status error (got 0x%8x, expected 0x%8x).", val, expected);
end
// Check trigout status
trigout_acc.read(`ADDR_ALT_TRIGOUT_STATUS, val);
val &= `ALT_TRIGOUT_TS_PRESENT;
expected = 0;
if (val != expected)
$fatal (1, "trigout status error (got 0x%8x, expected 0x%8x).",
val, expected);
// Save all triggers in trigout fifo.
trigout_acc.write(`ADDR_ALT_TRIGOUT_CTRL, ( `ALT_TRIGOUT_CH1_ENABLE
| `ALT_TRIGOUT_CH2_ENABLE
| `ALT_TRIGOUT_CH3_ENABLE
| `ALT_TRIGOUT_CH4_ENABLE
| `ALT_TRIGOUT_EXT_ENABLE));
#1us;
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_SECONDS_UPPER, 'h00000032); // timetag core seconds high
......@@ -331,7 +354,7 @@ module main;
// set time trigger
trigin_acc.write(`ADDR_ALT_TRIGIN_SECONDS + 0, 'h00000032);
trigin_acc.write(`ADDR_ALT_TRIGIN_SECONDS + 4, 'h00005a34);
trigin_acc.write(`ADDR_ALT_TRIGIN_CYCLES + 0, 'h00001000);
trigin_acc.write(`ADDR_ALT_TRIGIN_CYCLES, 'h00001000);
trigin_acc.write(`ADDR_ALT_TRIGIN_CTRL, `ALT_TRIGIN_CTRL_ENABLE);
trigin_acc.read(`ADDR_ALT_TRIGIN_CTRL, val);
......@@ -368,6 +391,23 @@ module main;
$display("<%t> END ACQ 5", $realtime);
$display("<%t> read trigout fifo", $realtime);
while (1) begin
uint64_t sec_hi, sec_lo, cycs;
trigout_acc.read(`ADDR_ALT_TRIGOUT_STATUS, val);
if (!(val & `ALT_TRIGOUT_TS_PRESENT))
break;
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_MASK_SEC + 0, sec_hi);
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_MASK_SEC + 4, sec_lo);
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_CYCLES, cycs);
$display("trigout TS: 0x%16x 0x%8x",
((sec_hi << 32) | sec_lo), cycs);
end;
#1us;
/* -----\/----- EXCLUDED -----\/-----
......
hdl/testbench/include/fmc_adc_alt_trigout.v 0 → 100644
View file @ 802eda5c
`define ADDR_ALT_TRIGOUT_STATUS 'h0
`define ALT_TRIGOUT_WR_ENABLE_OFFSET 0
`define ALT_TRIGOUT_WR_ENABLE 'h1
`define ALT_TRIGOUT_WR_LINK_OFFSET 1
`define ALT_TRIGOUT_WR_LINK 'h2
`define ALT_TRIGOUT_WR_VALID_OFFSET 2
`define ALT_TRIGOUT_WR_VALID 'h4
`define ALT_TRIGOUT_TS_PRESENT_OFFSET 8
`define ALT_TRIGOUT_TS_PRESENT 'h100
`define ADDR_ALT_TRIGOUT_CTRL 'h4
`define ALT_TRIGOUT_CH1_ENABLE_OFFSET 0
`define ALT_TRIGOUT_CH1_ENABLE 'h1
`define ALT_TRIGOUT_CH2_ENABLE_OFFSET 1
`define ALT_TRIGOUT_CH2_ENABLE 'h2
`define ALT_TRIGOUT_CH3_ENABLE_OFFSET 2
`define ALT_TRIGOUT_CH3_ENABLE 'h4
`define ALT_TRIGOUT_CH4_ENABLE_OFFSET 3
`define ALT_TRIGOUT_CH4_ENABLE 'h8
`define ALT_TRIGOUT_EXT_ENABLE_OFFSET 8
`define ALT_TRIGOUT_EXT_ENABLE 'h100
`define ADDR_ALT_TRIGOUT_TS_MASK_SEC 'h8
`define ALT_TRIGOUT_TS_SEC_OFFSET 0
`define ALT_TRIGOUT_TS_SEC 'hffffffffff
`define ALT_TRIGOUT_CH1_MASK_OFFSET 48
`define ALT_TRIGOUT_CH1_MASK 'h1000000000000
`define ALT_TRIGOUT_CH2_MASK_OFFSET 49
`define ALT_TRIGOUT_CH2_MASK 'h2000000000000
`define ALT_TRIGOUT_CH3_MASK_OFFSET 50
`define ALT_TRIGOUT_CH3_MASK 'h4000000000000
`define ALT_TRIGOUT_CH4_MASK_OFFSET 51
`define ALT_TRIGOUT_CH4_MASK 'h8000000000000
`define ALT_TRIGOUT_EXT_MASK_OFFSET 56
`define ALT_TRIGOUT_EXT_MASK 'h100000000000000
`define ADDR_ALT_TRIGOUT_TS_CYCLES 'h10
`define ALT_TRIGOUT_CYCLES_OFFSET 0
`define ALT_TRIGOUT_CYCLES 'hfffffff
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