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FMC ADC 100M 14b 4cha - Gateware
Commit 87b4eb87 authored by Matthieu Cattin's avatar Matthieu Cattin
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Update ucf and project files for crossbar with sdb.

parent bd260e57
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Showing with 125 additions and 652 deletions
hdl/spec/spec_top_fmc_adc_100Ms.ucf
View file @ 87b4eb87
......@@ -546,8 +546,8 @@ NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
INST "cmp_fmc_spi/Wrapped_SPI/shift/s_out" IOB=FALSE;
INST "cmp_fmc_spi/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
INST "cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/shift/s_out" IOB=FALSE;
INST "cmp_fmc_spi/U_Wrapped_SPI/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
#===============================================================================
......
hdl/spec/syn/spec_fmc_adc_100Ms.xise
View file @ 87b4eb87
......@@ -78,7 +78,6 @@
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -147,9 +146,6 @@
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -172,7 +168,6 @@
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -211,13 +206,11 @@
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_timesim.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_synthesis.v" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="spec_top_fmc_adc_100Ms_translate.v" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
......@@ -277,7 +270,6 @@
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
......@@ -309,7 +301,6 @@
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
......@@ -332,16 +323,13 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-11-08T18:12:50" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="1F4F849093C7768961E521CF8EC93589" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-11-19T16:51:55" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="494C936A59B24A26716C2B8E1771F2A1" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<libraries>
<library xil_pn:name="blk_mem_gen_v4_1"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</libraries>
<libraries/>
<files>
<file xil_pn:name="../spec_top_fmc_adc_100Ms.ucf" xil_pn:type="FILE_UCF">
......@@ -389,880 +377,365 @@
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/fmc_adc_100Ms_csr.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../adc/rtl/offset_gain_s.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_arbiter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/l2p_dma_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_decode32.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/p2l_dma_master.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="23"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/wbmaster32.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/common/rtl/dummy_ctrl_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="25"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/common/rtl/dummy_stat_regs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="26"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/common/rtl/wb_addr_decoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="27"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gencores_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="28"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_crc_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="29"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_moving_average.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="30"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_extend_pulse.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="31"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_delay_gen.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_rr_arbiter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="32"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_pi_controller.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_prio_encoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="33"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_reset.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_word_packer.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="34"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_serial_dac.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="35"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_sync_ffs.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="36"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_arbitrated_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="37"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/inferred_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="38"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_frequency_meter.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/inferred_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="39"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_dual_clock_ram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="40"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/common/gc_wfifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="41"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="42"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="43"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic_shiftreg_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="44"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="45"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="46"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_sameclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/generic/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="47"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_dpram_dualclock.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/wb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="48"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/generic_spram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_async_bridge/xwb_async_bridge.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="49"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_async_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="50"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/xilinx/spartan6/generic_sync_fifo.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="51"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_onewire_master/sockit_owm.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="52"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_bit_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="53"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_byte_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="54"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_getinit_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/i2c_master_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="55"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_min_area_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/wb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="56"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_bindec.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_i2c_master/xwb_i2c_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="57"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_mux.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_bus_fanout/xwb_bus_fanout.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="58"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dpram/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="59"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s6_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="60"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="61"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3adsp_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/wb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="62"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_simple_timer/xwb_tics.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="63"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3a_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_rx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="64"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_async_tx.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="65"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v6_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/uart_baud_gen.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="66"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="67"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v5_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/simple_uart_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="68"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/wb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="69"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_v4_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_uart/xwb_simple_uart.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="70"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/vic_prio_enc.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="71"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_wrapper_s3_init.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="72"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_prim_width.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="73"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_generic_cstr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="74"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_encoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="75"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_ecc_decoder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="76"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_input_block.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="77"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_output_block.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="78"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_top.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="79"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/blk_mem_gen_v4_1/blk_mem_gen_v4_1_xst.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="80"/>
<library xil_pn:name="blk_mem_gen_v4_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="81"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_defaults.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="82"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/fifo_generator_v6_1_xst_comp.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="83"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/input_blk.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="84"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/output_blk.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="85"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_wrapper.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="86"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/shft_ram.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="87"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dmem.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="88"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/memory.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="89"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/compare.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="90"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="91"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_bin_cntr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="92"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/updn_cntr.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="93"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_as.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="94"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_status_flags_ss.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="95"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_as.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="96"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_pe_ss.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="97"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_handshaking_flags.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="98"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_as.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="99"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_dc_fwft_ext_as.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="100"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="101"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/dc_ss_fwft.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="102"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/rd_fwft.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="103"/>
<library xil_pn:name="fifo_generator_v6_1"/>
</file>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/genrams/coregen_ip/fifo_generator_v6_1/wr_pf_as.vhd" xil_pn:type="FILE_VHDL">
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<library xil_pn:name="fifo_generator_v6_1"/>
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<library xil_pn:name="fifo_generator_v6_1"/>
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<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_slave_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="165"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/wb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="166"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_vic/xwb_vic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="167"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_clgen.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="168"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_shift.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="169"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/spi_top.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="170"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="171"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_spi/xwb_spi.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="172"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="173"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="174"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="175"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/xwb_lm32.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="176"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/generated/lm32_allprofiles.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="177"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_mc_arithmetic.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="178"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/jtag_cores.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="179"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_adder.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="180"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_addsub.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="181"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_dp_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="182"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_logic_op.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="183"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_ram.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="184"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/src/lm32_shifter.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="185"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/lm32_multiplier.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="186"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6/jtag_tap.v" xil_pn:type="FILE_VERILOG">
<association xil_pn:name="Implementation" xil_pn:seqID="187"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_slave_adapter/wb_slave_adapter.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="188"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/wb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="189"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xwb_xilinx_fpga_loader.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="190"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_registers_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="191"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_xilinx_fpga_loader/xloader_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="192"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_clock_crossing/xwb_clock_crossing.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="193"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wb_dma/xwb_dma.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="194"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_dpssram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="195"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_eic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="196"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_async.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="197"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_fifo_sync.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="198"/>
</file>
<file xil_pn:name="../ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="199"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="200"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wb.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="201"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="202"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_wrapper_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="203"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/rtl/ddr3_ctrl_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="204"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="205"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="206"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="207"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="208"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="209"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="210"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="211"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_32b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="212"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/ddr3_ctrl_spec_bank3_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="213"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="214"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="215"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="216"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="217"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="218"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="219"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/spec/ip_cores/ddr3_ctrl_spec_bank3_64b_32b/user_design/rtl/memc3_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="220"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/ddr3_ctrl_svec_bank4_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="221"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="222"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="223"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="224"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="225"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="226"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/memc4_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="227"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_32b_32b/user_design/rtl/memc4_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="228"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/ddr3_ctrl_svec_bank4_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="229"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="230"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="231"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="232"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="233"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="234"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="235"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank4_64b_32b/user_design/rtl/memc4_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="236"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/ddr3_ctrl_svec_bank5_32b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="237"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="238"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="239"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="240"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="241"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="242"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/memc5_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="243"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_32b_32b/user_design/rtl/memc5_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="244"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/ddr3_ctrl_svec_bank5_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="245"/>
</file>
<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="246"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="247"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_infrastructure.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/svec/ip_cores/ddr3_ctrl_svec_bank5_64b_32b/user_design/rtl/memc5_wrapper.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/ddr3_ctrl_vfc_bank1_32b_32b.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="257"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="258"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/memc1_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="259"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_32b_32b/user_design/rtl/memc1_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="260"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/ddr3_ctrl_vfc_bank1_64b_32b.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="261"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/iodrp_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="262"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/iodrp_mcb_controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="263"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/mcb_raw_wrapper.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/mcb_soft_calibration_top.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/mcb_soft_calibration.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="266"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/memc1_infrastructure.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="267"/>
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<file xil_pn:name="../ip_cores/ddr3-sp6-core/trunk/hdl/vfc/ip_cores/ddr3_ctrl_vfc_bank1_64b_32b/user_design/rtl/memc1_wrapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="268"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="269"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/gn4124_core_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="270"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/l2p_ser.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="271"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/p2l_des.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="272"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_clk_pll_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="273"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_1_to_n_data_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="274"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_diff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="275"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/serdes_n_to_1_s2_se.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="276"/>
</file>
<file xil_pn:name="../ip_cores/gn4124-core/trunk/hdl/gn4124core/rtl/spartan6/pulse_sync_rtl.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="Implementation" xil_pn:seqID="277"/>
</file>
</files>
......
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