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FMC ADC 100M 14b 4cha - Gateware
Commit 8f1bbe69 authored by mcattin's avatar mcattin
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coding adc core 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@39 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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hdl/spec/ip_cores/.lso 0 → 100644
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fifo_generator_v6_2
hdl/spec/ip_cores/_xmsgs/ngcbuild.xmsgs 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
hdl/spec/ip_cores/_xmsgs/pn_parser.xmsgs 0 → 100644
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/tmp/_cg/adc_sync_fifo.vhd&quot; into library work</arg>
</msg>
</messages>
hdl/spec/ip_cores/_xmsgs/xst.xmsgs 0 → 100644
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hdl/spec/ip_cores/adc_serdes.asy 0 → 100644
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Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 adc_serdes
RECTANGLE Normal 32 32 672 960
LINE Wide 0 112 32 112
PIN 0 112 LEFT 36
PINATTR PinName data_in_from_pins_p[8:0]
PINATTR Polarity IN
LINE Wide 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName data_in_from_pins_n[8:0]
PINATTR Polarity IN
LINE Normal 0 464 32 464
PIN 0 464 LEFT 36
PINATTR PinName clk_in
PINATTR Polarity IN
LINE Normal 0 560 32 560
PIN 0 560 LEFT 36
PINATTR PinName clk_div_in
PINATTR Polarity IN
LINE Normal 0 656 32 656
PIN 0 656 LEFT 36
PINATTR PinName clk_reset
PINATTR Polarity IN
LINE Normal 0 688 32 688
PIN 0 688 LEFT 36
PINATTR PinName io_reset
PINATTR Polarity IN
LINE Normal 0 720 32 720
PIN 0 720 LEFT 36
PINATTR PinName bitslip
PINATTR Polarity IN
LINE Normal 0 816 32 816
PIN 0 816 LEFT 36
PINATTR PinName locked_in
PINATTR Polarity IN
LINE Wide 704 80 672 80
PIN 704 80 RIGHT 36
PINATTR PinName data_in_to_device[71:0]
PINATTR Polarity OUT
LINE Normal 704 912 672 912
PIN 704 912 RIGHT 36
PINATTR PinName locked_out
PINATTR Polarity OUT
hdl/spec/ip_cores/adc_serdes.ejp 0 → 100644
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Encore.Project.FlowVendor = Foundation_ISE
Encore.Project.VhdlSim = true
Encore.Project.VerilogSim = false
Encore.Project.XDevice = xc6slx45t
Encore.Project.XDeviceFamily = spartan6
Encore.Project.XSpeedGrade = -3
Encore.Project.XPackage = fgg484
component_name = adc_serdes
c_device_family = spartan6
c_notes = None
c_bus_dir = INPUTS
c_bus_sig_type = DIFF
c_bus_io_std = LVDS_25
c_use_serialization = 1
c_serialization_factor = 8
c_use_phase_detector = 0
c_enable_bitslip = 1
c_enable_train = 0
c_train_constant = 0
c_system_data_width = 9
c_bus_in_delay = NONE
c_v6_bus_in_delay = NONE
c_bus_in_tap = 0
c_v6_bus_in_tap = 0
c_bus_tap_reset = FROM_ZERO
c_bus_tap_wrap = STAY_AT_LIMIT
c_bus_out_delay = NONE
c_v6_bus_out_delay = NONE
c_bus_out_tap = 0
c_v6_bus_out_tap = 0
c_clk_sig_type = SINGLE
c_clk_io_std = LVCMOS25
c_v6_clk_sig_type = DIFF
c_v6_clk_io_std = LVCMOS18
c_clk_buf = BUFPLL
c_v6_clk_buf = BUFIO
c_active_edge = RISING
c_v6_active_edge = NOT_APP
c_interface_type = RETIMED
c_v6_interface_type = NETWORKING
c_ddr_alignment = C0
c_v6_ddr_alignment = SAME_EDGE_PIPELINED
c_v6_oddr_alignment = SAME_EDGE
c_clk_delay = NONE
c_clk_tap = 0
c_clk_tap_reset = FROM_ZERO
c_clk_tap_wrap = STAY_AT_LIMIT
ComponentName = adc_serdes
hdl/spec/ip_cores/adc_serdes.gise 0 → 100644
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<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="adc_serdes.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="adc_serdes.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="adc_serdes.vho" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/spec/ip_cores/adc_serdes.ucf 0 → 100755
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# file: adc_serdes.ucf
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# Add the IOB Constraints here
hdl/spec/ip_cores/adc_serdes.vhd 0 → 100755
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hdl/spec/ip_cores/adc_serdes.vho 0 → 100755
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-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component adc_serdes
generic
(-- width of the data for the system
sys_w : integer := 9;
-- width of the data for the device
dev_w : integer := 72);
port
(
-- From the system into the device
DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0);
DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0);
DATA_IN_TO_DEVICE : out std_logic_vector(dev_w-1 downto 0);
BITSLIP : in std_logic;
-- Clock and reset signals
CLK_IN : in std_logic; -- Fast clock from PLL/MMCM
CLK_DIV_IN : in std_logic; -- Slow clock from PLL/MMCM
LOCKED_IN : in std_logic;
LOCKED_OUT : out std_logic;
CLK_RESET : in std_logic; -- Reset signal for Clock circuit
IO_RESET : in std_logic); -- Reset signal for IO circuit
end component;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
None
your_instance_name : adc_serdes
port map
(
-- From the system into the device
DATA_IN_FROM_PINS_P => DATA_IN_FROM_PINS_P,
DATA_IN_FROM_PINS_N => DATA_IN_FROM_PINS_N,
DATA_IN_TO_DEVICE => DATA_IN_TO_DEVICE,
BITSLIP => BITSLIP,
-- Clock and reset signals
CLK_IN => CLK_IN,
CLK_DIV_IN => CLK_DIV_IN,
LOCKED_IN => LOCKED_IN,
LOCKED_OUT => LOCKED_OUT,
CLK_RESET => CLK_RESET,
IO_RESET => IO_RESET);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
hdl/spec/ip_cores/adc_serdes.xco 0 → 100644
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##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Tue Mar 1 09:29:12 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT SelectIO_Interface_Wizard family Xilinx,_Inc. 1.4
# END Select
# BEGIN Parameters
CSET active_edge=RISING
CSET bus_dir=INPUTS
CSET bus_in_delay=NONE
CSET bus_in_tap=0
CSET bus_io_std=LVDS_25
CSET bus_out_delay=NONE
CSET bus_out_tap=0
CSET bus_sig_type=DIFF
CSET bus_tap_reset=NOT_APP
CSET bus_tap_wrap=NOT_APP
CSET clk_buf=BUFPLL
CSET clk_delay=NONE
CSET clk_io_std=LVCMOS25
CSET clk_sig_type=SINGLE
CSET clk_tap=0
CSET component_name=adc_serdes
CSET ddr_alignment=C0
CSET enable_bitslip=true
CSET enable_train=false
CSET interface_type=RETIMED
CSET notes=None
CSET serialization_factor=8
CSET system_data_width=9
CSET train_constant=0
CSET use_phase_detector=false
CSET use_serialization=true
CSET v6_active_edge=SDR
CSET v6_bus_in_delay=NONE
CSET v6_bus_in_tap=0
CSET v6_bus_out_delay=NONE
CSET v6_bus_out_tap=0
CSET v6_clk_buf=BUFIO
CSET v6_clk_io_std=LVCMOS18
CSET v6_clk_sig_type=DIFF
CSET v6_ddr_alignment=SAME_EDGE_PIPELINED
CSET v6_interface_type=NETWORKING
CSET v6_oddr_alignment=SAME_EDGE
# END Parameters
GENERATE
# CRC: 1002624d
hdl/spec/ip_cores/adc_serdes.xise 0 → 100644
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hdl/spec/ip_cores/adc_serdes/example_design/adc_serdes_exdes.vhd 0 → 100755
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-- file: adc_serdes_exdes.vhd
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------------------------
-- SelectIO wizard example design
------------------------------------------------------------------------------
-- This example design instantiates the IO circuitry
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
library unisim;
use unisim.vcomponents.all;
entity adc_serdes_exdes is
generic (
-- Clock -> q modeling delay
TCQ : time := 100 ps;
-- width of the data for the system
sys_w : integer := 9;
-- width of the data for the device
dev_w : integer := 72;
-- width of the address for the memory
add_w : integer := 10;
-- depth of the memory
add_l : integer := 1024);
port (
-- Memory interface
ADDRESS_USER : in std_logic_vector(add_w-1 downto 0);
DATA_IN_USER : in std_logic_vector(dev_w-1 downto 0);
DATA_OUT_USER : out std_logic_vector(dev_w-1 downto 0);
ENABLE_USER : in std_logic;
WRITE_USER : in std_logic;
ENABLE_DEVICE : in std_logic;
-- From the system into the device
DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0);
DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0);
CLK_IN : in std_logic;
BITSLIP : in std_logic;
CLK_RESET : in std_logic;
IO_RESET : in std_logic);
end adc_serdes_exdes;
architecture xilinx of adc_serdes_exdes is
component adc_serdes is
generic
(-- width of the data for the system
sys_w : integer := 9;
-- width of the data for the device
dev_w : integer := 72);
port
(
-- From the system into the device
DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0);
DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0);
DATA_IN_TO_DEVICE : out std_logic_vector(dev_w-1 downto 0);
BITSLIP : in std_logic;
-- Clock and reset signals
CLK_IN : in std_logic; -- Fast clock from PLL/MMCM
CLK_DIV_IN : in std_logic; -- Slow clock from PLL/MMCM
LOCKED_IN : in std_logic;
LOCKED_OUT : out std_logic;
CLK_RESET : in std_logic; -- Reset signal for Clock circuit
IO_RESET : in std_logic); -- Reset signal for IO circuit
end component;
constant num_serial_bits : integer := dev_w/sys_w;
-- connection between ram and io circuit
signal DATA_IN_TO_DEVICE : std_logic_vector(dev_w-1 downto 0);
signal write_device : std_logic := '1';
signal address_device : std_logic_vector(add_w-1 downto 0) := (others=>'0');
type ram_type is array (0 to add_l-1) of std_logic_vector(dev_w-1 downto 0);
shared variable ram_array : ram_type;
signal clkfbout : std_logic;
signal clk_in_pll : std_logic;
signal LOCKED_IN : std_logic;
signal LOCKED_OUT : std_logic;
signal clk_div_in_int : std_logic;
signal CLK_DIV_IN : std_logic;
begin
-- set up the fabric PLL_BASE to drive the BUFPLL
pll_base_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 4,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 4,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 4*num_serial_bits,
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 10.0,
REF_JITTER => 0.010)
port map (
-- Output clocks
CLKFBOUT => clkfbout,
CLKOUT0 => clk_in_pll,
CLKOUT1 => clk_div_in_int,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
-- Status and control signals
LOCKED => LOCKED_IN,
RST => CLK_RESET,
-- Input clock control
CLKFBIN => clkfbout,
CLKIN => CLK_IN);
clkd_buf : BUFG
port map (
O => CLK_DIV_IN,
I => clk_div_in_int);
-- Infer a dual port memory
process (CLK_DIV_IN) begin
if (CLK_DIV_IN = '1' and CLK_DIV_IN'event) then
if (ENABLE_USER = '1') then
if (WRITE_USER = '1') then
ram_array(conv_integer(ADDRESS_USER)) := DATA_IN_USER;
end if;
DATA_OUT_USER <= ram_array(conv_integer(ADDRESS_USER)) after TCQ;
end if;
end if;
end process;
process (CLK_DIV_IN) begin
if (CLK_DIV_IN = '1' and CLK_DIV_IN'event) then
if (ENABLE_DEVICE = '1') then
if (write_device = '1') then
ram_array(conv_integer(address_device)) := DATA_IN_TO_DEVICE;
end if;
end if;
end if;
end process;
-- auto-increment access into the RAM on the IO side
process (CLK_DIV_IN) begin
if (CLK_DIV_IN = '1' and CLK_DIV_IN'event) then
if (IO_RESET = '1') then
address_device <= (others=>'0') after TCQ;
elsif (ENABLE_DEVICE = '1') then
address_device <= address_device + 1 after TCQ;
end if;
end if;
end process;
-- Instantiate the IO design
io_inst : adc_serdes
port map
(
-- From the system into the device
DATA_IN_FROM_PINS_P => DATA_IN_FROM_PINS_P,
DATA_IN_FROM_PINS_N => DATA_IN_FROM_PINS_N,
DATA_IN_TO_DEVICE => DATA_IN_TO_DEVICE,
BITSLIP => BITSLIP,
CLK_IN => clk_in_pll,
CLK_DIV_IN => CLK_DIV_IN,
LOCKED_IN => LOCKED_IN,
LOCKED_OUT => LOCKED_OUT,
CLK_RESET => CLK_RESET,
IO_RESET => IO_RESET);
end xilinx;
hdl/spec/ip_cores/adc_serdes/implement/implement.bat 0 → 100755
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REM file: implement.bat
REM -----------------------------------------------------------------------------
REM Script to synthesize and implement the RTL provided for the clocking wizard
REM -----------------------------------------------------------------------------
REM Clean up the results directory
rmdir /S /Q results
mkdir results
REM Copy unisim_comp.v file to results directory
copy %XILINX%\verilog\src\iSE\unisim_comp.v .\results\
REM Synthesize the Verilog Wrapper Files
echo 'Synthesizing SelectIO Wizard design with XST'
xst -ifn xst.scr
copy adc_serdes_exdes.ngc results\
REM Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
copy ..\..\adc_serdes.ucf results\
cd results
echo 'Running ngdbuild'
ngdbuild -uc adc_serdes.ucf adc_serdes_exdes
echo 'Running map'
map -timing adc_serdes_exdes -o mapped.ncd
echo 'Running par'
par -w mapped.ncd routed mapped.pcf
echo 'Running trce'
trce -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen'
bitgen -w routed.ncd routed.bit mapped.pcf
echo 'Running netgen to create gate level model for the clocking wizard example design'
netgen -ofmt vhdl -sim -tm adc_serdes_exdes -w routed.ncd routed.vhd
cd ..
hdl/spec/ip_cores/adc_serdes/implement/implement.sh 0 → 100755
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#!/bin/sh
# file: implement.sh
#-----------------------------------------------------------------------------
# Script to synthesize and implement the RTL provided for the clocking wizard
#-----------------------------------------------------------------------------
# Clean up the results directory
rm -rf results
mkdir results
# Copy unisim_comp.v file to results directory
cp $XILINX/verilog/src/iSE/unisim_comp.v ./results/
# Synthesize the Verilog Wrapper Files
echo 'Synthesizing SelectIO Wizard design with XST'
xst -ifn xst.scr
cp adc_serdes_exdes.ngc results/
# Copy the constraints files generated by Coregen
echo 'Copying files from constraints directory to results directory'
cp ../../adc_serdes.ucf results/
cd results
echo 'Running ngdbuild'
ngdbuild -uc adc_serdes.ucf adc_serdes_exdes
echo 'Running map'
map -timing adc_serdes_exdes -o mapped.ncd
echo 'Running par'
par -w mapped.ncd routed mapped.pcf
echo 'Running trce'
trce -e 10 routed -o routed mapped.pcf
echo 'Running design through bitgen'
bitgen -w routed.ncd routed.bit mapped.pcf
echo 'Running netgen to create gate level model for the clocking wizard example design'
netgen -ofmt vhdl -sim -tm adc_serdes_exdes -w routed.ncd routed.vhd
cd ..
hdl/spec/ip_cores/adc_serdes/implement/xst.prj 0 → 100755
View file @ 8f1bbe69
vhdl work ../../adc_serdes.vhd
vhdl work ../example_design/adc_serdes_exdes.vhd
hdl/spec/ip_cores/adc_serdes/implement/xst.scr 0 → 100755
View file @ 8f1bbe69
run
-ifmt MIXED
-top adc_serdes_exdes
-p xc6slx45t-fgg484-3
-ifn xst.prj
-ofn adc_serdes_exdes
-keep_hierarchy soft
-equivalent_register_removal no
-max_fanout 65535
hdl/spec/ip_cores/adc_serdes/selectio_wiz_readme.txt 0 → 100644
View file @ 8f1bbe69
Core name: Xilinx LogiCORE SelectIO Wizard
Version: SelectIO Wizard v1.4
Release Date: July 23, 2010
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this
core, please go to:
http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP SelectIO Wizard v1.4
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/design_resources/conn_central/solution_kits/wizards/
2. NEW FEATURES
- ISE 12.2 software support
- Virtex-6 device family support
3. SUPPORTED DEVICES
The following device families are supported by the core for this release.
Virtex-6 XC CXT/LXT/SXT/HXT
Virtex-6 XQ LXT/SXT
Virtex-6 -1L XC LXT/SXT
Spartan-6 XC LX/LXT
Spartan-6 XA
Spartan-6 XQ LX/LXT
Spartan-6 -1L XC LX
4. RESOLVED ISSUES
- Incorrect Interface Type attribute setting:
Selecting "Networking Pipelined" option did not set the
attribute correctly (AR 35073).
5. KNOWN ISSUES
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/23/2010 Xilinx, Inc. 1.4 ISE 12.2 support
04/19/2010 Xilinx, Inc. 1.3 ISE 12.1 support
12/02/2009 Xilinx, Inc. 1.2 ISE 11.4 support
09/16/2009 Xilinx, Inc. 1.1 ISE 11.3 support
================================================================================
8. Legal Disclaimer
(c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
hdl/spec/ip_cores/adc_serdes/simulation/adc_serdes_tb.vhd 0 → 100755
View file @ 8f1bbe69
-- file: adc_serdes_tb.vhd
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
------------------------------------------------------------------------------
-- SelectIO wizard demonstration testbench
------------------------------------------------------------------------------
-- This demonstration testbench instantiates the example design for the
-- SelectIO wizard.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
library std;
use std.textio.all;
library work;
use work.all;
entity adc_serdes_tb is
end adc_serdes_tb;
architecture test of adc_serdes_tb is
component adc_serdes_exdes
generic (
-- Clock -> q modeling delay
TCQ : time := 100 ps;
-- width of the data for the system
sys_w : integer := 9;
-- width of the data for the device
dev_w : integer := 72;
-- width of the address for the memory
add_w : integer := 10;
-- depth of the memory
add_l : integer := 1024);
port (
-- Memory interface
ADDRESS_USER : in std_logic_vector(add_w-1 downto 0);
DATA_IN_USER : in std_logic_vector(dev_w-1 downto 0);
DATA_OUT_USER : out std_logic_vector(dev_w-1 downto 0);
ENABLE_USER : in std_logic;
WRITE_USER : in std_logic;
ENABLE_DEVICE : in std_logic;
-- From the system into the device
DATA_IN_FROM_PINS_P : in std_logic_vector(sys_w-1 downto 0);
DATA_IN_FROM_PINS_N : in std_logic_vector(sys_w-1 downto 0);
CLK_IN : in std_logic;
BITSLIP : in std_logic;
CLK_RESET : in std_logic;
IO_RESET : in std_logic);
end component;
constant TCQ : time := 100 ps;
constant clk_per : time := 10 ns; -- 100 MHz clk
constant sys_w : integer := 9;
constant dev_w : integer := 72;
constant add_w : integer := 10;
constant num_serial_bits : integer := dev_w/sys_w;
constant data_rate : integer := 1;
signal ADDRESS_USER : std_logic_vector(add_w-1 downto 0) := (others => '0');
signal DATA_IN_USER : std_logic_vector(dev_w-1 downto 0) := (others => '0');
signal DATA_OUT_USER : std_logic_vector(dev_w-1 downto 0);
signal ENABLE_USER : std_logic;
signal WRITE_USER : std_logic;
signal ENABLE_DEVICE : std_logic;
-- From the system into the device
signal DATA_IN_FROM_PINS : std_logic_vector(sys_w-1 downto 0);
signal DATA_IN_FROM_PINS_P : std_logic_vector(sys_w-1 downto 0);
signal DATA_IN_FROM_PINS_N : std_logic_vector(sys_w-1 downto 0);
signal CLK_IN : std_logic := '0';
signal BITSLIP : std_logic := '0';
signal CLK_RESET : std_logic;
signal IO_RESET : std_logic;
begin
-- Any aliases
DATA_IN_FROM_PINS_P <= DATA_IN_FROM_PINS;
DATA_IN_FROM_PINS_N <= not (DATA_IN_FROM_PINS);
-- clock generator- 100 MHz simulation clock
--------------------------------------------
process begin
wait for (clk_per/2);
CLK_IN <= not CLK_IN;
end process;
-- Test sequence
process begin
DATA_IN_FROM_PINS <= (others => '0');
-- reset the logic
CLK_RESET <= '1';
IO_RESET <= '1';
CLK_RESET <= '0';
wait for (18*clk_per);
WRITE_USER <= '0';
ENABLE_USER <= '0';
-- start up the io
IO_RESET <= '0';
wait for (8*clk_per);
ENABLE_DEVICE <= '1';
-- Drive data onto the pins
DATA_IN_FROM_PINS <= (others => '0');
for ii in 0 to 255 loop
ADDRESS_USER <= conv_std_logic_vector(ii, add_w);
wait for 0 ns;
DATA_IN_FROM_PINS <= conv_std_logic_vector(ii, sys_w) ;
wait for (clk_per/data_rate);
end loop;
report "Simulation Stopped." severity failure;
wait;
end process;
-- Instantiation of the example design
dut : adc_serdes_exdes
generic map
(TCQ => 100 ps,
sys_w => 9,
dev_w => 72,
add_w => 10)
port map
(--Memory interface
ADDRESS_USER => ADDRESS_USER,
DATA_IN_USER => DATA_IN_USER,
DATA_OUT_USER => DATA_OUT_USER,
ENABLE_USER => ENABLE_USER,
WRITE_USER => WRITE_USER,
ENABLE_DEVICE => ENABLE_DEVICE,
-- From the system into the device
DATA_IN_FROM_PINS_P => DATA_IN_FROM_PINS_P,
DATA_IN_FROM_PINS_N => DATA_IN_FROM_PINS_N,
CLK_IN => CLK_IN,
BITSLIP => BITSLIP,
CLK_RESET => CLK_RESET,
IO_RESET => IO_RESET);
end test;
hdl/spec/ip_cores/adc_serdes/simulation/functional/simcmds.tcl 0 → 100755
View file @ 8f1bbe69
# file: simcmds.tcl
# create the simulation script
vcd dumpfile isim.vcd
vcd dumpvars -m /adc_serdes_tb -l 0
run 50000ns
quit
hdl/spec/ip_cores/adc_serdes/simulation/functional/simulate_isim.bat 0 → 100755
View file @ 8f1bbe69
REM file: simulate_isim.bat
REM (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
REM
REM This file contains confidential and proprietary information
REM of Xilinx, Inc. and is protected under U.S. and
REM international copyright and other intellectual property
REM laws.
REM
REM DISCLAIMER
REM This disclaimer is not a license and does not grant any
REM rights to the materials distributed herewith. Except as
REM otherwise provided in a valid license issued to you by
REM Xilinx, and to the maximum extent permitted by applicable
REM law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
REM WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
REM AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
REM BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
REM INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
REM (2) Xilinx shall not be liable (whether in contract or tort,
REM including negligence, or under any other theory of
REM liability) for any loss or damage of any kind or nature
REM related to, arising under or in connection with these
REM materials, including for any direct, or any indirect,
REM special, incidental, or consequential loss or damage
REM (including loss of data, profits, goodwill, or any type of
REM loss or damage suffered as a result of any action brought
REM by a third party) even if such damage or loss was
REM reasonably foreseeable or Xilinx had been advised of the
REM possibility of the same.
REM
REM CRITICAL APPLICATIONS
REM Xilinx products are not designed or intended to be fail-
REM safe, or for use in any application requiring fail-safe
REM performance, such as life-support or safety devices or
REM systems, Class III medical devices, nuclear facilities,
REM applications related to the deployment of airbags, or any
REM other applications that could lead to death, personal
REM injury, or severe property or environmental damage
REM (individually and collectively, "Critical
REM Applications"). Customer assumes the sole risk and
REM liability of any use of Xilinx products in Critical
REM Applications, subject only to applicable laws and
REM regulations governing limitations on product liability.
REM
REM THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
REM PART OF THIS FILE AT ALL TIMES.
vhpcomp -work work ..\..\..\adc_serdes.vhd
vhpcomp -work work ..\..\example_design/adc_serdes_exdes.vhd
vhpcomp -work work ..\adc_serdes_tb.vhd
REM compile the project
fuse work.adc_serdes_tb -L unisim -o adc_serdes_isim.exe
REM run the simulation script
.\adc_serdes_isim.exe -gui -tclbatch simcmds.tcl
hdl/spec/ip_cores/adc_serdes/simulation/functional/simulate_isim.sh 0 → 100755
View file @ 8f1bbe69
# file: simulate_isim.sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# create the project
vhpcomp -work work ../../../adc_serdes.vhd
vhpcomp -work work ../../example_design/adc_serdes_exdes.vhd
vhpcomp -work work ../adc_serdes_tb.vhd
# compile the project
fuse work.adc_serdes_tb -L unisim -o adc_serdes_isim.exe
# run the simulation script
./adc_serdes_isim.exe -gui -tclbatch simcmds.tcl
hdl/spec/ip_cores/adc_serdes/simulation/functional/simulate_mti.do 0 → 100755
View file @ 8f1bbe69
# file: simulate_mti.do
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# set up the working directory
set work work
vlib work
# compile all of the files
vcom -work work ../../../adc_serdes.vhd
vcom -work work ../../example_design/adc_serdes_exdes.vhd
vcom -work work ../adc_serdes_tb.vhd
# run the simulation
vsim -voptargs="+acc" -L secureip -L unisim work.adc_serdes_tb
do wave.do
log -r /*
run 50000ns
hdl/spec/ip_cores/adc_serdes/simulation/functional/simulate_ncsim.sh 0 → 100755
View file @ 8f1bbe69
#/bin/sh
# file: simulate_ncsim.sh
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
# set up the working directory
mkdir work
# compile all of the files
ncvhdl -v93 -work work ../../../adc_serdes.vhd
ncvhdl -v93 -work work ../../example_design/adc_serdes_exdes.vhd
ncvhdl -v93 -work work ../adc_serdes_tb.vhd
# elaborate and run the simulation
ncelab -work work -access +wc work.adc_serdes_tb
ncsim -input "@database -open -shm nc; probe -create -database nc -all -depth all; run 50000ns; exit" work.adc_serdes_tb
hdl/spec/ip_cores/adc_serdes/simulation/functional/wave.do 0 → 100755
View file @ 8f1bbe69
# file: wave.do
# (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
#
# This file contains confidential and proprietary information
# of Xilinx, Inc. and is protected under U.S. and
# international copyright and other intellectual property
# laws.
#
# DISCLAIMER
# This disclaimer is not a license and does not grant any
# rights to the materials distributed herewith. Except as
# otherwise provided in a valid license issued to you by
# Xilinx, and to the maximum extent permitted by applicable
# law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
# WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
# AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
# BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
# INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
# (2) Xilinx shall not be liable (whether in contract or tort,
# including negligence, or under any other theory of
# liability) for any loss or damage of any kind or nature
# related to, arising under or in connection with these
# materials, including for any direct, or any indirect,
# special, incidental, or consequential loss or damage
# (including loss of data, profits, goodwill, or any type of
# loss or damage suffered as a result of any action brought
# by a third party) even if such damage or loss was
# reasonably foreseeable or Xilinx had been advised of the
# possibility of the same.
#
# CRITICAL APPLICATIONS
# Xilinx products are not designed or intended to be fail-
# safe, or for use in any application requiring fail-safe
# performance, such as life-support or safety devices or
# systems, Class III medical devices, nuclear facilities,
# applications related to the deployment of airbags, or any
# other applications that could lead to death, personal
# injury, or severe property or environmental damage
# (individually and collectively, "Critical
# Applications"). Customer assumes the sole risk and
# liability of any use of Xilinx products in Critical
# Applications, subject only to applicable laws and
# regulations governing limitations on product liability.
#
# THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
# PART OF THIS FILE AT ALL TIMES.
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Literal -radix unsigned /adc_serdes_tb/dut/sys_w
add wave -noupdate -format Literal -radix unsigned /adc_serdes_tb/dut/dev_w
add wave -noupdate -format Logic /adc_serdes_tb/IO_RESET
add wave -noupdate -format Logic /adc_serdes_tb/CLK_RESET
add wave -noupdate -format Logic /adc_serdes_tb/CLK_IN
add wave -noupdate -format Logic /adc_serdes_tb/dut/CLK_DIV_IN
add wave -noupdate -format Logic /adc_serdes_tb/ENABLE_USER
add wave -noupdate -format Logic /adc_serdes_tb/WRITE_USER
add wave -noupdate -format Logic /adc_serdes_tb/ENABLE_DEVICE
add wave -noupdate -format Literal /adc_serdes_tb/DATA_OUT_USER
add wave -noupdate -format Literal /adc_serdes_tb/DATA_IN_USER
add wave -noupdate -format Literal /adc_serdes_tb/DATA_IN_FROM_PINS_P
add wave -noupdate -format Literal /adc_serdes_tb/DATA_IN_FROM_PINS_N
add wave -noupdate -format Literal /adc_serdes_tb/dut/io_inst/iserdes_q
add wave -noupdate -format Literal /adc_serdes_tb/dut/DATA_IN_TO_DEVICE
add wave -noupdate -format Literal /adc_serdes_tb/ADDRESS_USER
add wave -noupdate -format Logic /adc_serdes_tb/dut/WRITE_USER
add wave -noupdate -format Logic /adc_serdes_tb/dut/write_device
add wave -noupdate -format Logic /adc_serdes_tb/dut/BITSLIP
add wave -noupdate -format Logic /adc_serdes_tb/dut/IO_RESET
add wave -noupdate -format Logic /adc_serdes_tb/dut/ENABLE_USER
add wave -noupdate -format Logic /adc_serdes_tb/dut/ENABLE_DEVICE
add wave -noupdate -format Literal /adc_serdes_tb/dut/ADDRESS_USER
add wave -noupdate -format Literal /adc_serdes_tb/dut/address_device
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {370825 ps} 0}
configure wave -namecolwidth 230
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {3169444 ps}
hdl/spec/ip_cores/adc_serdes_flist.txt 0 → 100644
View file @ 8f1bbe69
# Output products list for <adc_serdes>
_xmsgs/pn_parser.xmsgs
adc_serdes/doc/selectio_wiz_ds746.pdf
adc_serdes/doc/selectio_wiz_gsg700.pdf
adc_serdes/example_design/adc_serdes_exdes.vhd
adc_serdes/implement/implement.bat
adc_serdes/implement/implement.sh
adc_serdes/implement/synplify.prj
adc_serdes/implement/xst.prj
adc_serdes/implement/xst.scr
adc_serdes/selectio_wiz_readme.txt
adc_serdes/simulation/adc_serdes_tb.vhd
adc_serdes/simulation/functional/simcmds.tcl
adc_serdes/simulation/functional/simulate_isim.bat
adc_serdes/simulation/functional/simulate_isim.sh
adc_serdes/simulation/functional/simulate_mti.do
adc_serdes/simulation/functional/simulate_ncsim.sh
adc_serdes/simulation/functional/simulate_vcs.sh
adc_serdes/simulation/functional/ucli_commands.key
adc_serdes/simulation/functional/vcs_session.tcl
adc_serdes/simulation/functional/wave.do
adc_serdes.asy
adc_serdes.ejp
adc_serdes.gise
adc_serdes.ucf
adc_serdes.vhd
adc_serdes.vho
adc_serdes.xco
adc_serdes.xise
adc_serdes_flist.txt
adc_serdes_xmdf.tcl
hdl/spec/ip_cores/adc_serdes_xmdf.tcl 0 → 100644
View file @ 8f1bbe69
# The package naming convention is <core_name>_xmdf
package provide adc_serdes_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::adc_serdes_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::adc_serdes_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name adc_serdes
}
# ::adc_serdes_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::adc_serdes_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/doc/selectio_wiz_ds746.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/doc/selectio_wiz_gsg700.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/example_design/adc_serdes_exdes.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/implement/implement.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/implement/implement.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/implement/synplify.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/implement/xst.prj
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/implement/xst.scr
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/selectio_wiz_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/adc_serdes_tb.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/functional/simcmds.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/functional/simulate_isim.bat
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/functional/simulate_isim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/functional/simulate_mti.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/functional/simulate_ncsim.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/functional/simulate_vcs.sh
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/functional/ucli_commands.key
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/functional/vcs_session.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes/simulation/functional/wave.do
utilities_xmdf::xmdfSetData $instance FileSet $fcount type Ignore
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes.ejp
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes.ucf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ucf
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_serdes_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module adc_serdes
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
hdl/spec/ip_cores/adc_sync_fifo.asy 0 → 100644
View file @ 8f1bbe69
Version 4
SymbolType BLOCK
TEXT 32 32 LEFT 4 adc_sync_fifo
RECTANGLE Normal 32 32 544 768
LINE Wide 0 80 32 80
PIN 0 80 LEFT 36
PINATTR PinName din[64:0]
PINATTR Polarity IN
LINE Normal 0 144 32 144
PIN 0 144 LEFT 36
PINATTR PinName wr_en
PINATTR Polarity IN
LINE Normal 0 176 32 176
PIN 0 176 LEFT 36
PINATTR PinName wr_clk
PINATTR Polarity IN
LINE Normal 0 240 32 240
PIN 0 240 LEFT 36
PINATTR PinName rd_en
PINATTR Polarity IN
LINE Normal 0 272 32 272
PIN 0 272 LEFT 36
PINATTR PinName rd_clk
PINATTR Polarity IN
LINE Normal 144 800 144 768
PIN 144 800 BOTTOM 36
PINATTR PinName rst
PINATTR Polarity IN
LINE Wide 576 80 544 80
PIN 576 80 RIGHT 36
PINATTR PinName dout[64:0]
PINATTR Polarity OUT
LINE Normal 576 208 544 208
PIN 576 208 RIGHT 36
PINATTR PinName full
PINATTR Polarity OUT
LINE Normal 576 432 544 432
PIN 576 432 RIGHT 36
PINATTR PinName empty
PINATTR Polarity OUT
LINE Normal 576 528 544 528
PIN 576 528 RIGHT 36
PINATTR PinName valid
PINATTR Polarity OUT
hdl/spec/ip_cores/adc_sync_fifo.gise 0 → 100644
View file @ 8f1bbe69
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<!-- -->
<!-- For tool use only. Do not edit. -->
<!-- -->
<!-- ProjectNavigator created generated project file. -->
<!-- For use in tracking generated file and other information -->
<!-- allowing preservation of process status. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="adc_sync_fifo.xise"/>
<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_ASY" xil_pn:name="adc_sync_fifo.asy" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="adc_sync_fifo.sym" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_VHO" xil_pn:name="adc_sync_fifo.vho" xil_pn:origination="imported"/>
<file xil_pn:fileType="FILE_USERDOC" xil_pn:name="fifo_generator_readme.txt" xil_pn:origination="imported"/>
</files>
<transforms xmlns="http://www.xilinx.com/XMLSchema"/>
</generated_project>
hdl/spec/ip_cores/adc_sync_fifo.ngc 0 → 100644
View file @ 8f1bbe69
This diff is collapsed.
hdl/spec/ip_cores/adc_sync_fifo.sym 0 → 100644
View file @ 8f1bbe69
<?xml version="1.0" encoding="UTF-8"?>
<symbol version="7" name="adc_sync_fifo">
<symboltype>BLOCK</symboltype>
<timestamp>2011-3-4T8:36:12</timestamp>
<pin polarity="Input" x="0" y="80" name="din[64:0]" />
<pin polarity="Input" x="0" y="144" name="wr_en" />
<pin polarity="Input" x="0" y="176" name="wr_clk" />
<pin polarity="Input" x="0" y="240" name="rd_en" />
<pin polarity="Input" x="0" y="272" name="rd_clk" />
<pin polarity="Input" x="144" y="800" name="rst" />
<pin polarity="Output" x="576" y="80" name="dout[64:0]" />
<pin polarity="Output" x="576" y="208" name="full" />
<pin polarity="Output" x="576" y="432" name="empty" />
<pin polarity="Output" x="576" y="528" name="valid" />
<graph>
<text style="fontsize:40;fontname:Arial" x="32" y="32">adc_sync_fifo</text>
<rect width="512" x="32" y="32" height="736" />
<line x2="32" y1="80" y2="80" style="linewidth:W" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="80" type="pin din[64:0]" />
<line x2="32" y1="144" y2="144" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="144" type="pin wr_en" />
<line x2="32" y1="176" y2="176" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="176" type="pin wr_clk" />
<line x2="32" y1="240" y2="240" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="240" type="pin rd_en" />
<line x2="32" y1="272" y2="272" x1="0" />
<attrtext style="fontsize:24;fontname:Arial" attrname="PinName" x="36" y="272" type="pin rd_clk" />
<line x2="144" y1="800" y2="768" x1="144" />
<attrtext style="alignment:BCENTER;fontsize:24;fontname:Arial" attrname="PinName" x="144" y="764" type="pin rst" />
<line x2="544" y1="80" y2="80" style="linewidth:W" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="80" type="pin dout[64:0]" />
<line x2="544" y1="208" y2="208" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="208" type="pin full" />
<line x2="544" y1="432" y2="432" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="432" type="pin empty" />
<line x2="544" y1="528" y2="528" x1="576" />
<attrtext style="alignment:RIGHT;fontsize:24;fontname:Arial" attrname="PinName" x="540" y="528" type="pin valid" />
</graph>
</symbol>
hdl/spec/ip_cores/adc_sync_fifo.vhd 0 → 100644
View file @ 8f1bbe69
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file adc_sync_fifo.vhd when simulating
-- the core, adc_sync_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY adc_sync_fifo IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(64 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(64 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic);
END adc_sync_fifo;
ARCHITECTURE adc_sync_fifo_a OF adc_sync_fifo IS
-- synthesis translate_off
component wrapped_adc_sync_fifo
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(64 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(64 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_adc_sync_fifo use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 65,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "spartan6",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 65,
c_msgon_val => 1,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 12,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 1,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 13,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x72",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 1);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_adc_sync_fifo
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid);
-- synthesis translate_on
END adc_sync_fifo_a;
hdl/spec/ip_cores/adc_sync_fifo.vho 0 → 100644
View file @ 8f1bbe69
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- The following code must appear in the VHDL architecture header:
------------- Begin Cut here for COMPONENT Declaration ------ COMP_TAG
component adc_sync_fifo
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(64 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(64 downto 0);
full: OUT std_logic;
empty: OUT std_logic;
valid: OUT std_logic);
end component;
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of adc_sync_fifo: component is true;
-- COMP_TAG_END ------ End COMPONENT Declaration ------------
-- The following code must appear in the VHDL architecture
-- body. Substitute your own instance name and net names.
------------- Begin Cut here for INSTANTIATION Template ----- INST_TAG
your_instance_name : adc_sync_fifo
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty,
valid => valid);
-- INST_TAG_END ------ End INSTANTIATION Template ------------
-- You must compile the wrapper file adc_sync_fifo.vhd when simulating
-- the core, adc_sync_fifo. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
hdl/spec/ip_cores/adc_sync_fifo.xco 0 → 100644
View file @ 8f1bbe69
##############################################################
#
# Xilinx Core Generator version 12.2
# Date: Fri Mar 4 08:39:33 2011
#
##############################################################
#
# This file contains the customisation parameters for a
# Xilinx CORE Generator IP GUI. It is strongly recommended
# that you do not manually alter this file as it may cause
# unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
# END Project Options
# BEGIN Select
SELECT Fifo_Generator family Xilinx,_Inc. 6.2
# END Select
# BEGIN Parameters
CSET almost_empty_flag=false
CSET almost_full_flag=false
CSET component_name=adc_sync_fifo
CSET data_count=false
CSET data_count_width=4
CSET disable_timing_violations=false
CSET dout_reset_value=0
CSET empty_threshold_assert_value=2
CSET empty_threshold_negate_value=3
CSET enable_ecc=false
CSET enable_int_clk=false
CSET enable_reset_synchronization=true
CSET fifo_implementation=Independent_Clocks_Block_RAM
CSET full_flags_reset_value=1
CSET full_threshold_assert_value=13
CSET full_threshold_negate_value=12
CSET inject_dbit_error=false
CSET inject_sbit_error=false
CSET input_data_width=65
CSET input_depth=16
CSET output_data_width=65
CSET output_depth=16
CSET overflow_flag=false
CSET overflow_sense=Active_High
CSET performance_options=Standard_FIFO
CSET programmable_empty_type=No_Programmable_Empty_Threshold
CSET programmable_full_type=No_Programmable_Full_Threshold
CSET read_clock_frequency=1
CSET read_data_count=false
CSET read_data_count_width=4
CSET reset_pin=true
CSET reset_type=Asynchronous_Reset
CSET underflow_flag=false
CSET underflow_sense=Active_High
CSET use_dout_reset=true
CSET use_embedded_registers=false
CSET use_extra_logic=false
CSET valid_flag=true
CSET valid_sense=Active_High
CSET write_acknowledge_flag=false
CSET write_acknowledge_sense=Active_High
CSET write_clock_frequency=1
CSET write_data_count=false
CSET write_data_count_width=4
# END Parameters
GENERATE
# CRC: c9c39e35
hdl/spec/ip_cores/adc_sync_fifo.xise 0 → 100644
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This diff is collapsed.
hdl/spec/ip_cores/adc_sync_fifo_flist.txt 0 → 100644
View file @ 8f1bbe69
# Output products list for <adc_sync_fifo>
_xmsgs/pn_parser.xmsgs
adc_sync_fifo.asy
adc_sync_fifo.gise
adc_sync_fifo.ngc
adc_sync_fifo.sym
adc_sync_fifo.vhd
adc_sync_fifo.vho
adc_sync_fifo.xco
adc_sync_fifo.xise
adc_sync_fifo_flist.txt
adc_sync_fifo_xmdf.tcl
fifo_generator_readme.txt
fifo_generator_ug175.pdf
hdl/spec/ip_cores/adc_sync_fifo_xmdf.tcl 0 → 100644
View file @ 8f1bbe69
# The package naming convention is <core_name>_xmdf
package provide adc_sync_fifo_xmdf 1.0
# This includes some utilities that support common XMDF operations
package require utilities_xmdf
# Define a namespace for this package. The name of the name space
# is <core_name>_xmdf
namespace eval ::adc_sync_fifo_xmdf {
# Use this to define any statics
}
# Function called by client to rebuild the params and port arrays
# Optional when the use context does not require the param or ports
# arrays to be available.
proc ::adc_sync_fifo_xmdf::xmdfInit { instance } {
# Variable containg name of library into which module is compiled
# Recommendation: <module_name>
# Required
utilities_xmdf::xmdfSetData $instance Module Attributes Name adc_sync_fifo
}
# ::adc_sync_fifo_xmdf::xmdfInit
# Function called by client to fill in all the xmdf* data variables
# based on the current settings of the parameters
proc ::adc_sync_fifo_xmdf::xmdfApplyParams { instance } {
set fcount 0
# Array containing libraries that are assumed to exist
# Examples include unisim and xilinxcorelib
# Optional
# In this example, we assume that the unisim library will
# be magically
# available to the simulation and synthesis tool
utilities_xmdf::xmdfSetData $instance FileSet $fcount type logical_library
utilities_xmdf::xmdfSetData $instance FileSet $fcount logical_library unisim
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_sync_fifo.asy
utilities_xmdf::xmdfSetData $instance FileSet $fcount type asy
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_sync_fifo.ngc
utilities_xmdf::xmdfSetData $instance FileSet $fcount type ngc
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_sync_fifo.sym
utilities_xmdf::xmdfSetData $instance FileSet $fcount type symbol
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_sync_fifo.vhd
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_sync_fifo.vho
utilities_xmdf::xmdfSetData $instance FileSet $fcount type vhdl_template
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_sync_fifo.xco
utilities_xmdf::xmdfSetData $instance FileSet $fcount type coregen_ip
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path adc_sync_fifo_xmdf.tcl
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_readme.txt
utilities_xmdf::xmdfSetData $instance FileSet $fcount type text
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount relative_path fifo_generator_ug175.pdf
utilities_xmdf::xmdfSetData $instance FileSet $fcount type AnyView
incr fcount
utilities_xmdf::xmdfSetData $instance FileSet $fcount associated_module adc_sync_fifo
incr fcount
}
# ::gen_comp_name_xmdf::xmdfApplyParams
hdl/spec/ip_cores/coregen.cgc 0 → 100644
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This diff is collapsed.
hdl/spec/ip_cores/coregen.cgp 0 → 100644
View file @ 8f1bbe69
# Date: Mon Feb 28 16:49:11 2011
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = VHDL
SET device = xc6slx45t
SET devicefamily = spartan6
SET flowvendor = Foundation_ISE
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = fgg484
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = false
SET vhdlsim = true
SET workingdirectory = ./tmp/
# CRC: 8d93f58a
hdl/spec/ip_cores/coregen.log 0 → 100644
View file @ 8f1bbe69
Welcome to Xilinx CORE Generator.
Help system initialized.
Opening project file
/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/coregen.cgp.
Project, 'coregen', initialised from file
'/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/coregen.cgp'.
Customize and GenerateCustomizing IP...
Release 12.2 - Xilinx CORE Generator IP GUI Launcher M.63c (lin)
Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved.
Initializing IP model...
Finished initialising IP model.
Finished Customizing.
Generating IP...
Initializing IP model...
Finished initialising IP model.
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
Generating Implementation files.
Generating ISE symbol file...
Generating NGC file.
Finished Generation Stage.
Generating IP instantiation template...
Generating the VHDL instantiation template.
Finished generating IP instantiation template.
Generating metadata file...
Finished generating metadata file.
Generating metadata file...
Finished generating metadata file.
Generating ISE file...
Finished ISE file generation.
Generating FLIST file...
Finished FLIST file generation.
Preparing output directory...
Finished preparing output directory.
Launching readme viewer...
Launched readme viewer.
Moving files to output directory...
Finished moving files to output directory
Saved options for project 'coregen'.
View Data SheetLaunching datasheet viewer...
WARNING:sim:254 - Unable to launch pdf viewerERROR:sim - Failed to launch datasheet viewer.
hdl/spec/ip_cores/fifo_generator_readme.txt 0 → 100644
View file @ 8f1bbe69
Core Name: Xilinx LogiCORE FIFO Generator
Version: 6.2
Release Date: July 23, 2010
================================================================================
This document contains the following sections:
1. Introduction
2. New Features
3. Supported Devices
4. Resolved Issues
5. Known Issues
6. Technical Support
7. Core Release History
8. Legal Disclaimer
================================================================================
1. INTRODUCTION
For the most recent updates to the IP installation instructions for this core,
please go to:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
For system requirements:
http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm
This file contains release notes for the Xilinx LogiCORE IP FIFO Generator v6.2
solution. For the latest core updates, see the product page at:
http://www.xilinx.com/products/ipcenter/FIFO_Generator.htm
2. NEW FEATURES
- ISE 12.2 software support
3. SUPPORTED DEVICES
- SPARTAN-3, SPARTAN-3 XA, SPARTAN-3E SPARTAN-3E XA, SPARTAN-3A, SPARTAN-3A XA, SPARTAN-3ADSP, SPARTAN-3ADSP XA
- SPARTAN-6, SPARTAN-6 XA, SPARTAN-6L and QSPARTAN-6
- VIRTEX-4
- VIRTEX-5 and QVIRTEX-5
- VIRTEX-6, VIRTEX-6L and QVIRTEX-6
4. RESOLVED ISSUES
- In the FIFO Generator core, PROG_FULL does not assert when set to maximum threshold value.
- Version fixed: v6.2
- CR 553279
- In the FIFO Generator verilog behavioral model, PROG_EMPTY does not assert/de-assert when the threshold
value is passed through parameter.
- Version fixed: v6.2
- CR 549673
- In the FIFO Generator GUI, read width is reset to write width when the component name is change.
- Version fixed: v6.2
- CR 563827
5. KNOWN ISSUES
The following are known issues for v6.2 of this core at time of release:
- In the FIFO generator GUI, after importing an XCO file (Independent clock, distributed memory configuration)
into a Virtex-4 coregen project, if the FIFO type is changed to "Independent Clocks, Built-in FIFO" in page 1,
page 2 does not correctly offer the Read Clock Frequency and Write Clock Frequency options as it should.
- CR 467240
- AR 31379
The most recent information, including known issues, workarounds, and
resolutions for this version is provided in the IP Release Notes User Guide
located at
www.xilinx.com/support/documentation/user_guides/xtp025.pdf
6. TECHNICAL SUPPORT
To obtain technical support, create a WebCase at www.xilinx.com/support.
Questions are routed to a team with expertise using this product.
Xilinx provides technical support for use of this product when used
according to the guidelines described in the core documentation, and
cannot guarantee timing, functionality, or support of this product for
designs that do not follow specified guidelines.
7. CORE RELEASE HISTORY
Date By Version Description
================================================================================
07/23/2010 Xilinx, Inc. 6.2 ISE 12.2 support
04/19/2010 Xilinx, Inc. 6.1 ISE 12.1 support
12/02/2009 Xilinx, Inc. 5.3 rev 1 ISE 11.4 support; Spartan-6 Low Power and Automotive Spartan-6 Device support
09/16/2009 Xilinx, Inc. 5.3 Update to add 11.3; Virtex-6 Low Power and Virtex-6 HXT Device support
06/24/2009 Xilinx, Inc. 5.2 Update to add 11.2 and Virtex-6 CXT device support
04/24/2009 Xilinx, Inc. 5.1 Update to add 11.1 and Virtex-6 and Spartan-6 device support
09/19/2008 Xilinx, Inc. 4.4 Update to add 10.1 SP3 and Virtex-5 TXT device support and miscellaneous bug fixes
03/24/2008 Xilinx, Inc. 4.3 Update to add 10.1 support and miscellaneous bug fixes
10/03/2007 Xilinx, Inc. 4.2 Support for FWFT for Block RAM and Distributed RAM Common Clock FIFOs
08/08/2007 Xilinx, Inc. 4.1 Update to add 9.2i support; Revised to v4.1; ECC support for block RAM FIFO
04/02/2007 Xilinx, Inc. 3.3 Update to add 9.1i support; Revised to v3.3; Spartan-3A and Spartan-3A DSP support; ECC support
09/21/2006 Xilinx, Inc. 3.2 Revised to v3.2; Spartan-3 and Virtex-4 automotive device support
07/13/2006 Xilinx, Inc. 3.1 Update to add 8.2i support; Revised to v3.1; Virtex-5 support
01/11/2006 Xilinx, Inc. 2.3 Update to add 8.1i support; Revised to v2.3
08/31/2005 Xilinx, Inc. 2.2 Update to add 7.1i SP4 support; Revised to v2.2
04/28/2005 Xilinx, Inc. 2.1 Update to add 7.1i SP1 support; Revised to v2.1
11/04/2004 Xilinx, Inc. 2.0 Update to add 6.3i support; Revised to v2.0
05/21/2004 Xilinx, Inc. 1.1 Revised to v1.1; Virtex-4 support
04/23/2004 Xilinx, Inc. 1.0 Update to add 6.2i support; First release
================================================================================
8. Legal Disclaimer
(c) Copyright 2002 - 2010 Xilinx, Inc. All rights reserved.
This file contains confidential and proprietary information
of Xilinx, Inc. and is protected under U.S. and
international copyright and other intellectual property
laws.
DISCLAIMER
This disclaimer is not a license and does not grant any
rights to the materials distributed herewith. Except as
otherwise provided in a valid license issued to you by
Xilinx, and to the maximum extent permitted by applicable
law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
(2) Xilinx shall not be liable (whether in contract or tort,
including negligence, or under any other theory of
liability) for any loss or damage of any kind or nature
related to, arising under or in connection with these
materials, including for any direct, or any indirect,
special, incidental, or consequential loss or damage
(including loss of data, profits, goodwill, or any type of
loss or damage suffered as a result of any action brought
by a third party) even if such damage or loss was
reasonably foreseeable or Xilinx had been advised of the
possibility of the same.
CRITICAL APPLICATIONS
Xilinx products are not designed or intended to be fail-
safe, or for use in any application requiring fail-safe
performance, such as life-support or safety devices or
systems, Class III medical devices, nuclear facilities,
applications related to the deployment of airbags, or any
other applications that could lead to death, personal
injury, or severe property or environmental damage
(individually and collectively, "Critical
Applications"). Customer assumes the sole risk and
liability of any use of Xilinx products in Critical
Applications, subject only to applicable laws and
regulations governing limitations on product liability.
THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
PART OF THIS FILE AT ALL TIMES.
hdl/spec/ise_project/_xmsgs/pn_parser.xmsgs
View file @ 8f1bbe69
......@@ -8,5 +8,83 @@
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/dma_controller_wb_slave.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_pkg_s6.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/gn4124_core_s6.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_arbiter.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_dma_master.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/l2p_ser_s6.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_decode32.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_des_s6.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/p2l_dma_master.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_clk_pll_s2_diff.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_1_to_n_data_s2_se.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_diff.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/serdes_n_to_1_s2_se.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/GN4124_core/hdl/gn4124core/rtl/wbmaster32.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/ddr_controller_bank3.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/iodrp_controller.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/iodrp_mcb_controller.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/mcb_raw_wrapper.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/mcb_soft_calibration.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/mcb_soft_calibration_top.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/memc3_infrastructure.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/ip_cores/ddr_controller_bank3/user_design/rtl/memc3_wrapper.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/ddr3_ctrl_core/hdl/spec/rtl/ddr3_ctrl.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd&quot; into library work</arg>
</msg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/mcattin/projects/monostable/monostable_rtl.vhd&quot; into library work</arg>
</msg>
</messages>
hdl/spec/ise_project/iseconfig/spec_fmc_adc_100Ms.projectmgr
View file @ 8f1bbe69
......@@ -29,13 +29,13 @@
<ClosedNode>User Constraints</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem/>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000287000000010000000100000000000000000000000064ffffffff000000810000000000000001000002870000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem/>
</ItemView>
<ItemView guiview="File" >
<ClosedNodes/>
......@@ -64,12 +64,12 @@
<ClosedNode>Design Utilities</ClosedNode>
</ClosedNodes>
<SelectedItems>
<SelectedItem></SelectedItem>
<SelectedItem>Add Existing Source</SelectedItem>
</SelectedItems>
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000000000000000000287000000010000000100000000000000000000000064ffffffff000000810000000000000001000002870000000100000000</ViewHeaderState>
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
<CurrentItem></CurrentItem>
<CurrentItem>Add Existing Source</CurrentItem>
</ItemView>
</Project>
hdl/spec/ise_project/iseconfig/spec_top.xreport
View file @ 8f1bbe69
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2011-02-24T10:24:35</DateModified>
<DateModified>2011-03-04T09:29:20</DateModified>
<ModuleName>spec_top</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/mcattin/projects/spec/hdl/fmc_adc_100MHz/ise_project/iseconfig/spec_top.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/mcattin/projects/spec/hdl/fmc_adc_100MHz/ise_project</ImplementationReportsDirectory>
<SavedFilePath>/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ise_project/iseconfig/spec_top.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ise_project/</ImplementationReportsDirectory>
<DateInitialized>2011-02-24T10:24:34</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
......
hdl/spec/ise_project/spec_top_summary.html
View file @ 8f1bbe69
......@@ -75,5 +75,5 @@
</TABLE>
<br><center><b>Date Generated:</b> 02/24/2011 - 10:24:35</center>
<br><center><b>Date Generated:</b> 03/04/2011 - 09:29:20</center>
</BODY></HTML>
\ No newline at end of file
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hdl/spec/rtl/fmc_adc_100Ms_core.vhd 0 → 100644
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hdl/spec/rtl/fmc_adc_100Ms_csr.vhd 0 → 100644
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This diff is collapsed.
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
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hdl/spec/spec_top_fmc_adc_100Ms.ucf
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View file @ 8f1bbe69
WBGEN2=../../../../wbgen2/wishbone-gen/wbgen2
RTL=../rtl/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd $@.wb
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd $@.wb
\ No newline at end of file
hdl/spec/wb_gen/carrier_csr.wb 0 → 100644
View file @ 8f1bbe69
peripheral {
name = "Carrier control and status registers";
description = "Wishbone slave for control and status registers related to the FMC carrier";
hdl_entity = "carrier_csr";
prefix = "carrier_csr";
reg {
name = "Carrier type and PCB version";
prefix = "carrier";
field {
name = "PCB revision";
description = "Binary coded PCB layout revision";
prefix = "pcb_rev";
type = SLV;
size = 4;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Dummy";
description = "Ignore on read, write with 0's";
prefix = "dummy";
type = SLV;
size = 12;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "Carrier type";
description = "Carrier type identifier";
prefix = "type";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Bitstream type";
prefix = "bitstream_type";
field {
name = "Bitstream type";
description = "Bitstream (firmware) type, unsigned 32-bit number";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Bitstream date";
prefix = "bitstream_date";
field {
name = "Bitstream date";
description = "Bitstream generation date, unsigned 32-bit UTC time";
type = SLV;
size = 32;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Status";
prefix = "stat";
field {
name = "FMC presence";
description = "0: FMC slot is not populated\n1: FMC slot is populated";
prefix = "fmc_pres";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "GN4142 core P2L PLL status";
description = "0: not locked\n1: locked";
prefix = "p2l_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "System clock PLL status";
description = "0: not locked\n1: locked";
prefix = "sys_pll_lck";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
field {
name = "DDR3 calibration status";
description = "0: not done\n1: done";
prefix = "ddr3_cal_done";
type = BIT;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
};
reg {
name = "Control";
prefix = "ctrl";
field {
name = "Green LED";
description = "Front panel green LED control";
prefix = "led_green";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Red LED";
description = "Front panel red LED control";
prefix = "led_red";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "DAC clear";
description = "Active low clear signal for VCXO DACs";
prefix = "dac_clr_n";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
-- ram {
-- name = "Release tag";
-- description = "256-byte ASCII area for text generated by versionning tool";
-- prefix = "rel_tag";
-- size = 64;
-- width = 32;
-- access_bus = READ_ONLY;
-- access_dev = WRITE_ONLY;
-- };
};
hdl/spec/wb_gen/fmc_adc_100Ms_csr.wb 0 → 100644
View file @ 8f1bbe69
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