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FMC ADC 100M 14b 4cha - Gateware
Commit 94a44c27 authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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hdl: Eradicate INT from wishbone records and peripheral ports.

parent 051e9b4c
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Showing with 10 additions and 22 deletions
hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @ 94a44c27
......@@ -512,7 +512,6 @@ begin
cnx_master_in(c_WB_SLAVE_FMC_ADC).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC_ADC).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC_ADC).stall <= '0';
cnx_master_in(c_WB_SLAVE_FMC_ADC).int <= '0';
------------------------------------------------------------------------------
-- Mezzanine 1-wire master
......@@ -566,7 +565,6 @@ begin
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC_EIC).int <= '0';
-- Detects end of adc core writing to ddr
p_ddr_wr_fifo_empty : process (sys_clk_i)
......@@ -633,6 +631,5 @@ begin
cnx_master_in(c_WB_SLAVE_TIMETAG).err <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).rty <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).stall <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).int <= '0';
end rtl;
etherbone-core @ 79a60811
Subproject commit 8489445985ff2afe6c72712014a92a271869f20a
Subproject commit 79a6081166043ee24d835cbe7c5e5632dacad1f6
general-cores @ 61ca3f49
Subproject commit c3cfcfdd48308aeb787fde006cd27f15097f3ed1
Subproject commit 61ca3f49b61233e922f4c2c034e1b62728c124bf
gn4124-core @ e7cd73db
Subproject commit 9b9625bb4270114266cd357f199d649f3d799f04
Subproject commit e7cd73db41ba056ed4b27731c21a3b2aa53eaa51
vme64x-core @ a120e226
Subproject commit fa34d06e35ca0bfad8eac24aa51713e81639da64
Subproject commit a120e2262e1cb23fa611dddb7fa3727b520a125c
wr-cores @ d4b42139
Subproject commit 1e01c22d441248dfd0206b754afb20af2cc08716
Subproject commit d4b42139d3cf88ebbc3bb78eb718db9f5dcce305
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ 94a44c27
......@@ -787,7 +787,6 @@ begin
csr_stall_i => cnx_slave_out(c_MASTER_GENNUM).stall,
csr_err_i => cnx_slave_out(c_MASTER_GENNUM).err,
csr_rty_i => cnx_slave_out(c_MASTER_GENNUM).rty,
csr_int_i => cnx_slave_out(c_MASTER_GENNUM).int,
-- DMA wishbone interface (pipelined)
dma_clk_i => sys_clk_62_5,
dma_adr_o => wb_dma_adr,
......@@ -815,7 +814,6 @@ begin
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_DMA).err <= '0';
cnx_master_in(c_WB_SLAVE_DMA).rty <= '0';
cnx_master_in(c_WB_SLAVE_DMA).int <= '0';
------------------------------------------------------------------------------
-- CSR wishbone crossbar
......@@ -959,7 +957,6 @@ begin
cnx_master_in(c_WB_SLAVE_SPEC_CSR).err <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_CSR).rty <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_CSR).stall <= '0';
cnx_master_in(c_WB_SLAVE_SPEC_CSR).int <= '0';
-- SPEC front panel leds
led_red_o <= led_red or csr_regout.ctrl_led_red_o;
......@@ -1007,7 +1004,6 @@ begin
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_DMA_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_DMA_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_DMA_EIC).int <= '0';
------------------------------------------------------------------------------
-- FMC ADC mezzanine (wb bridge with cross-clocking)
......@@ -1117,7 +1113,6 @@ begin
-- Unused wishbone signals
cnx_fmc0_sync_master_in.err <= '0';
cnx_fmc0_sync_master_in.rty <= '0';
cnx_fmc0_sync_master_in.int <= '0';
------------------------------------------------------------------------------
-- DMA wishbone bus slaves
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ 94a44c27
......@@ -674,6 +674,8 @@ begin
sys_clk_pll_locked <= '1';
ddr_clk_pll_rst <= sys_clk_pll_locked;
-- logic AND of all async reset sources for DDR (active low)
ddr_arst_n <= sys_clk_pll_locked and ddr_clk_pll_locked;
......@@ -758,8 +760,9 @@ begin
wb_i.err => cnx_slave_out(c_WB_MASTER_VME).err,
wb_i.rty => cnx_slave_out(c_WB_MASTER_VME).rty,
wb_i.stall => cnx_slave_out(c_WB_MASTER_VME).stall,
wb_i.int => irq_to_vme,
wb_i.dat => cnx_slave_out(c_WB_MASTER_VME).dat);
wb_i.dat => cnx_slave_out(c_WB_MASTER_VME).dat,
int_i => irq_to_vme);
vme_ga <= vme_gap_i & vme_ga_i;
vme_berr_o <= not vme_berr_n;
......@@ -912,7 +915,6 @@ begin
cnx_master_in(c_WB_SLAVE_SVEC_CSR).err <= '0';
cnx_master_in(c_WB_SLAVE_SVEC_CSR).rty <= '0';
cnx_master_in(c_WB_SLAVE_SVEC_CSR).stall <= '0';
cnx_master_in(c_WB_SLAVE_SVEC_CSR).int <= '0';
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
......@@ -1039,7 +1041,6 @@ begin
-- Unused wishbone signals
cnx_fmc0_sync_master_in.err <= '0';
cnx_fmc0_sync_master_in.rty <= '0';
cnx_fmc0_sync_master_in.int <= '0';
------------------------------------------------------------------------------
-- Slot 2 : FMC ADC mezzanine (wb bridge with cross-clocking)
......@@ -1148,7 +1149,6 @@ begin
-- Unused wishbone signals
cnx_fmc1_sync_master_in.err <= '0';
cnx_fmc1_sync_master_in.rty <= '0';
cnx_fmc1_sync_master_in.int <= '0';
------------------------------------------------------------------------------
-- DDR0 controller (bank 4)
......@@ -1300,11 +1300,9 @@ begin
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_DAT).int <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).stall <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_DDR_ADR).int <= '0';
------------------------------------------------------------------------------
-- DDR1 controller (bank 5)
......@@ -1456,11 +1454,9 @@ begin
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_DAT).int <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).stall <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).int <= '0';
------------------------------------------------------------------------------
-- Carrier front panel LEDs and LEMOs
......
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