[hdl] expose SERDES PLL lock status to CSR

Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>

[hdl] expose SERDES PLL lock status to CSR
Signed-off-by: Dimitris Lampridis <dimitris.lampridis@cern.ch>
9f76ed4d · Dimitris Lampridis · 1330c85a · 9f76ed4d · 9f76ed4d
Commit 9f76ed4d authored Mar 10, 2020 by Dimitris Lampridis
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Showing with 17 additions and 5 deletions

ltc2174_2l16b_receiver.vhd hdl/platform/xilinx/spartan6/ltc2174_2l16b_receiver.vhd +6 -4

fmc_adc_100Ms_core.vhd hdl/rtl/fmc_adc_100Ms_core.vhd +11 -1

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--- a/hdl/platform/xilinx/spartan6/ltc2174_2l16b_receiver.vhd
+++ b/hdl/platform/xilinx/spartan6/ltc2174_2l16b_receiver.vhd
@@ -61,6 +61,9 @@ entity ltc2174_2l16b_receiver is
    serdes_arst_i   : in  std_logic := '0';
    -- Manual bitslip command (optional)
    serdes_bslip_i  : in  std_logic := '0';
+    -- SERDES BUFPLL lock status flag
+    -- (used when g_USE_PLL=TRUE, otherwise it is tied to '1')
+    serdes_locked_o : out std_logic;
    -- Indication that SERDES is ok and locked to
    -- frame start pattern
    serdes_synced_o : out std_logic;
@@ -81,7 +84,6 @@ architecture arch of ltc2174_2l16b_receiver is
  signal adc_outb          : std_logic_vector(3 downto 0);
  signal clk_serdes_p      : std_logic;
  signal clk_serdes_n      : std_logic;
-  signal bufpll_locked     : std_logic;
  signal clk_div_buf       : std_logic;
  signal serdes_strobe     : std_logic                    := '0';
  signal serdes_auto_bslip : std_logic                    := '0';
@@ -232,7 +234,7 @@ begin  -- architecture arch
        DIVIDE => 8)
      port map (
        IOCLK        => clk_serdes_p,
-        LOCK         => bufpll_locked,
+        LOCK         => serdes_locked_o,
        SERDESSTROBE => serdes_strobe,
        GCLK         => clk_div_buf,
        LOCKED       => l_pll_locked,
@@ -282,7 +284,7 @@ begin  -- architecture arch
        O => clk_div_buf);

    -- not used in this case
-    bufpll_locked <= '1';
+    serdes_locked_o <= '1';

  end generate gen_dual_bufio2;

@@ -316,7 +318,7 @@ begin  -- architecture arch
  end process p_auto_bitslip;

  serdes_bitslip  <= serdes_auto_bslip or serdes_bslip_i;
-  serdes_synced_o <= serdes_synced and bufpll_locked;
+  serdes_synced_o <= serdes_synced;

  ------------------------------------------------------------------------------
  -- Data deserializer

--- a/hdl/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core.vhd
@@ -177,6 +177,8 @@ architecture rtl of fmc_adc_100Ms_core is
  signal serdes_out_data_synced  : std_logic_vector(63 downto 0);
  signal serdes_man_bitslip      : std_logic;
  signal serdes_man_bitslip_sync : std_logic;
+  signal serdes_locked           : std_logic;
+  signal serdes_locked_sync      : std_logic;
  signal serdes_synced           : std_logic;
  signal serdes_synced_sync      : std_logic;

@@ -455,6 +457,7 @@ begin
      adc_outb_n_i    => adc_outb_n_i,
      serdes_arst_i   => serdes_arst,
      serdes_bslip_i  => serdes_man_bitslip_sync,
+      serdes_locked_o => serdes_locked,
      serdes_synced_o => serdes_synced,
      adc_data_o      => serdes_out_data,
      adc_clk_o       => fs_clk);
@@ -466,6 +469,13 @@ begin
      d_i       => serdes_synced,
      q_o       => serdes_synced_sync);

+  cmp_serdes_locked_sync : gc_sync
+    port map (
+      clk_i     => sys_clk_i,
+      rst_n_a_i => '1',
+      d_i       => serdes_locked,
+      q_o       => serdes_locked_sync);
+
  ------------------------------------------------------------------------------
  -- ADC core control and status registers (CSR)
  ------------------------------------------------------------------------------
@@ -479,7 +489,7 @@ begin
      fmc_adc_100Ms_csr_o => csr_regout);

  csr_regin.sta_fsm           <= acq_fsm_state;
-  csr_regin.sta_serdes_pll    <= '1';
+  csr_regin.sta_serdes_pll    <= serdes_locked_sync;
  csr_regin.sta_serdes_synced <= serdes_synced_sync;
  csr_regin.sta_acq_cfg       <= acq_config_ok;
  csr_regin.trig_stat_ext     <= trig_storage(0);