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FMC ADC 100M 14b 4cha - Gateware
Commit ad916b89 authored by Dimitris Lampridis's avatar Dimitris Lampridis Committed by Dimitris Lampridis
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hdl: add bit to clear last trigger status, and prevent trigger status from… 

hdl: add bit to clear last trigger status, and prevent trigger status from updating when not in acquisition
parent 290c1c04
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doc/manual/fmc_adc_100Ms_csr.tex
View file @ ad916b89
......@@ -216,6 +216,11 @@ Manual TRIG LED
@code{ACQ_LED}
@tab @code{0} @tab
Manual ACQ LED
@item @code{8}
@tab W/O @tab
@code{CLEAR_TRIG_STAT}
@tab @code{0} @tab
Clear trigger status
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
......@@ -223,6 +228,7 @@ Manual ACQ LED
@item @code{test_data_en} @tab Write the DDR RAM address counter value instead of ADC data to DDR.@*Note that no timetags are appended at the end of test data.
@item @code{trig_led} @tab Manual control of the front panel TRIG LED
@item @code{acq_led} @tab Manual control of the front panel ACQ LED
@item @code{clear_trig_stat} @tab Write 1 to clear the last trigger status register. Auto-resets to zero.
@end multitable
@regsection @code{sta} - Status register
@multitable @columnfractions .10 .10 .15 .10 .55
......
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ ad916b89
......@@ -266,6 +266,7 @@ architecture rtl of fmc_adc_100Ms_core is
signal trig_fifo_rd : std_logic;
signal trig_fifo_wr : std_logic;
signal trig_storage : std_logic_vector(31 downto 0);
signal trig_storage_clear : std_logic;
-- Under-sampling
signal undersample_factor : std_logic_vector(31 downto 0);
......@@ -684,6 +685,7 @@ begin
test_data_en <= csr_regout.ctl_test_data_en_o;
trig_led_man <= csr_regout.ctl_trig_led_o;
acq_led_man <= csr_regout.ctl_acq_led_o;
trig_storage_clear <= csr_regout.ctl_clear_trig_stat_o;
ext_trig_delay <= csr_regout.ext_trig_dly_o;
ext_trig_en <= csr_regout.trig_en_ext_o;
ext_trig_pol <= csr_regout.trig_pol_ext_o;
......@@ -937,7 +939,7 @@ begin
"00" & sw_trig_fixed_delay(sw_trig_fixed_delay'HIGH) &
ext_trig_fixed_delay(ext_trig_fixed_delay'HIGH);
trig_fifo_wr <= not trig_fifo_full;
trig_fifo_wr <= not trig_fifo_full and acq_in_wait_trig;
cmp_trig_sync_fifo : generic_async_fifo
generic map (
......@@ -979,12 +981,12 @@ begin
trig_fifo_rd <= not trig_fifo_empty;
p_trig_storage_sys: process (sys_clk_i, sys_rst_n_i) is
p_trig_storage_sys: process (sys_clk_i) is
begin
if sys_rst_n_i = '0' then
trig_storage <= (others => '0');
elsif rising_edge(sys_clk_i) then
if trig_fifo_dout(32) = '1' and trig_fifo_empty = '0' then
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' or trig_storage_clear = '1' then
trig_storage <= (others => '0');
elsif trig_fifo_dout(32) = '1' and trig_fifo_empty = '0' then
trig_storage <= trig_fifo_dout(31 downto 0);
end if;
end if;
......
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ ad916b89
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Fri Jan 26 15:37:35 2018
-- Created : Mon Feb 19 14:22:24 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -48,6 +48,8 @@ signal fmc_adc_100ms_csr_ctl_man_bitslip_sync2 : std_logic ;
signal fmc_adc_100ms_csr_ctl_test_data_en_int : std_logic ;
signal fmc_adc_100ms_csr_ctl_trig_led_int : std_logic ;
signal fmc_adc_100ms_csr_ctl_acq_led_int : std_logic ;
signal fmc_adc_100ms_csr_ctl_clear_trig_stat_dly0 : std_logic ;
signal fmc_adc_100ms_csr_ctl_clear_trig_stat_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ext_int : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ext_sync0 : std_logic ;
signal fmc_adc_100ms_csr_trig_en_ext_sync1 : std_logic ;
......@@ -227,6 +229,7 @@ begin
fmc_adc_100ms_csr_ctl_test_data_en_int <= '0';
fmc_adc_100ms_csr_ctl_trig_led_int <= '0';
fmc_adc_100ms_csr_ctl_acq_led_int <= '0';
fmc_adc_100ms_csr_ctl_clear_trig_stat_int <= '0';
fmc_adc_100ms_csr_trig_en_ext_int <= '0';
fmc_adc_100ms_csr_trig_en_sw_int <= '0';
fmc_adc_100ms_csr_trig_en_time_int <= '0';
......@@ -314,6 +317,7 @@ begin
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
regs_o.ctl_fsm_cmd_wr_o <= '0';
fmc_adc_100ms_csr_ctl_clear_trig_stat_int <= '0';
ack_in_progress <= '0';
else
regs_o.ctl_fsm_cmd_wr_o <= '0';
......@@ -383,6 +387,7 @@ begin
fmc_adc_100ms_csr_ctl_test_data_en_int <= wrdata_reg(5);
fmc_adc_100ms_csr_ctl_trig_led_int <= wrdata_reg(6);
fmc_adc_100ms_csr_ctl_acq_led_int <= wrdata_reg(7);
fmc_adc_100ms_csr_ctl_clear_trig_stat_int <= wrdata_reg(8);
end if;
rddata_reg(2) <= fmc_adc_100ms_csr_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_100ms_csr_ctl_offset_dac_clr_n_int;
......@@ -390,9 +395,9 @@ begin
rddata_reg(5) <= fmc_adc_100ms_csr_ctl_test_data_en_int;
rddata_reg(6) <= fmc_adc_100ms_csr_ctl_trig_led_int;
rddata_reg(7) <= fmc_adc_100ms_csr_ctl_acq_led_int;
rddata_reg(8) <= '0';
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(8) <= 'X';
rddata_reg(9) <= 'X';
rddata_reg(10) <= 'X';
rddata_reg(11) <= 'X';
......@@ -1353,6 +1358,19 @@ begin
regs_o.ctl_trig_led_o <= fmc_adc_100ms_csr_ctl_trig_led_int;
-- Manual ACQ LED
regs_o.ctl_acq_led_o <= fmc_adc_100ms_csr_ctl_acq_led_int;
-- Clear trigger status
process (clk_sys_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_100ms_csr_ctl_clear_trig_stat_dly0 <= '0';
regs_o.ctl_clear_trig_stat_o <= '0';
elsif rising_edge(clk_sys_i) then
fmc_adc_100ms_csr_ctl_clear_trig_stat_dly0 <= fmc_adc_100ms_csr_ctl_clear_trig_stat_int;
regs_o.ctl_clear_trig_stat_o <= fmc_adc_100ms_csr_ctl_clear_trig_stat_int and (not fmc_adc_100ms_csr_ctl_clear_trig_stat_dly0);
end if;
end process;
-- State machine status
-- SerDes PLL status
-- SerDes synchronization status
......
hdl/adc/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
View file @ ad916b89
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Fri Jan 26 15:37:35 2018
-- Created : Mon Feb 19 14:22:24 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -76,6 +76,7 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ctl_test_data_en_o : std_logic;
ctl_trig_led_o : std_logic;
ctl_acq_led_o : std_logic;
ctl_clear_trig_stat_o : std_logic;
trig_en_ext_o : std_logic;
trig_en_sw_o : std_logic;
trig_en_time_o : std_logic;
......@@ -134,6 +135,7 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ctl_test_data_en_o => '0',
ctl_trig_led_o => '0',
ctl_acq_led_o => '0',
ctl_clear_trig_stat_o => '0',
trig_en_ext_o => '0',
trig_en_sw_o => '0',
trig_en_time_o => '0',
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ ad916b89
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Fri Jan 26 15:37:35 2018
* Created : Mon Feb 19 14:22:25 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -61,6 +61,9 @@
/* definitions for field: Manual ACQ LED in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_ACQ_LED WBGEN2_GEN_MASK(7, 1)
/* definitions for field: Clear trigger status in reg: Control register */
#define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT WBGEN2_GEN_MASK(8, 1)
/* definitions for register: Status register */
/* definitions for field: State machine status in reg: Status register */
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ ad916b89
......@@ -1010,6 +1010,23 @@ fmc_adc_100ms_csr_ctl_acq_led_o
wb_ack_o
</td>
<td class="td_sym_center">
</td>
<td class="td_pblock_right">
fmc_adc_100ms_csr_ctl_clear_trig_stat_o
</td>
<td class="td_arrow_right">
&rarr;
</td>
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
&nbsp;
</td>
<td class="td_pblock_right">
......@@ -1021,10 +1038,10 @@ wb_ack_o
</tr>
<tr>
<td class="td_arrow_left">
&larr;
</td>
<td class="td_pblock_left">
wb_stall_o
</td>
<td class="td_sym_center">
......@@ -3799,8 +3816,8 @@ CTL
<td class="td_unused">
-
</td>
<td class="td_unused">
-
<td style="border: solid 1px black;" colspan=1 class="td_field">
CLEAR_TRIG_STAT
</td>
</tr>
</table>
......@@ -3884,6 +3901,10 @@ TRIG_LED
ACQ_LED
</b>[<i>read/write</i>]: Manual ACQ LED
<br>Manual control of the front panel ACQ LED
<li><b>
CLEAR_TRIG_STAT
</b>[<i>write-only</i>]: Clear trigger status
<br>Write 1 to clear the last trigger status register. Auto-resets to zero.
</ul>
<a name="STA"></a>
<h3><a name="sect_3_2">3.2. Status register</a></h3>
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ ad916b89
......@@ -69,17 +69,12 @@ peripheral {
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 24;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
name = "Clear trigger status";
description = "Write 1 to clear the last trigger status register. Auto-resets to zero.";
prefix = "clear_trig_stat";
type = MONOSTABLE;
};
]]
};
reg {
......@@ -122,17 +117,6 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 26;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -407,17 +391,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -447,17 +420,6 @@ peripheral {
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -561,17 +523,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -588,17 +539,6 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -614,17 +554,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -640,17 +569,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -666,17 +584,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -735,17 +642,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -762,17 +658,6 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -788,17 +673,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -814,17 +688,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -840,17 +703,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -909,17 +761,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -936,17 +777,6 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -962,17 +792,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -988,17 +807,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -1014,17 +822,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -1082,17 +879,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 25;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -1109,17 +895,6 @@ peripheral {
access_dev = WRITE_ONLY;
clock = "fs_clk_i";
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_ONLY;
access_dev = WRITE_ONLY;
};
]]
};
reg {
......@@ -1135,17 +910,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -1161,17 +925,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 16;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
reg {
......@@ -1187,17 +940,6 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
--[[
field {
name = "Reserved";
description = "Ignore on read, write with 0's";
prefix = "reserved";
type = SLV;
size = 17;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
]]
};
......
hdl/spec/testbench/include/fmc_adc_100Ms_csr.v
View file @ ad916b89
......@@ -13,6 +13,8 @@
`define FMC_ADC_100MS_CSR_CTL_TRIG_LED 32'h00000040
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED_OFFSET 7
`define FMC_ADC_100MS_CSR_CTL_ACQ_LED 32'h00000080
`define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT_OFFSET 8
`define FMC_ADC_100MS_CSR_CTL_CLEAR_TRIG_STAT 32'h00000100
`define ADDR_FMC_ADC_100MS_CSR_STA 10'h4
`define FMC_ADC_100MS_CSR_STA_FSM_OFFSET 0
`define FMC_ADC_100MS_CSR_STA_FSM 32'h00000007
......
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