Add bit description for IRQ controller registers.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@112 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4

Add bit description for IRQ controller registers.
git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@112 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
af2eaddf · mcattin · 78c670fe · af2eaddf · af2eaddf · af2eaddf
Commit af2eaddf authored Jan 18, 2012 by mcattin
4 changed files
--- a/hdl/spec/rtl/irq_controller_regs.vhd
+++ b/hdl/spec/rtl/irq_controller_regs.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : ../rtl/irq_controller_regs.vhd
 -- Author         : auto-generated by wbgen2 from irq_controller_regs.wb
-- Created        : Mon Nov 21 18:08:05 2011
+-- Created        : Wed Jan 18 09:43:55 2012
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb

--- a/hdl/spec/wb_gen/irq_controller_regs.h
+++ b/hdl/spec/wb_gen/irq_controller_regs.h
@@ -3,7 +3,7 @@

  * File           : irq_controller_regs.h
  * Author         : auto-generated by wbgen2 from irq_controller_regs.wb
-  * Created        : Mon Nov 21 18:08:05 2011
+  * Created        : Wed Jan 18 09:43:55 2012
  * Standard       : ANSI C

    THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb

--- a/hdl/spec/wb_gen/irq_controller_regs.htm
+++ b/hdl/spec/wb_gen/irq_controller_regs.htm
@@ -355,7 +355,7 @@ MULTI_IRQ
 </tr>
 </table>
 <p>
-Multiple interrupts occurs before irq source is read.<br>Write '1' to clear a bit.
+Multiple interrupts occurs before irq source is read.<br>Write '1' to clear a bit.<br><br>Bit 0: DMA done.<br>Bit 1: DMA error.<br>Bit 2: Trigger.<br>Bit 3: Acquisition end.
 </p>
 <table cellpadding=0 cellspacing=0 border=0>
 <tr>
@@ -615,7 +615,7 @@ SRC
 </tr>
 </table>
 <p>
-Indicates the interrupt source.<br>Write '1' to clear a bit.
+Indicates the interrupt source.<br>Write '1' to clear a bit.<br><br>Bit 0: DMA done.<br>Bit 1: DMA error.<br>Bit 2: Trigger.<br>Bit 3: Acquisition end.
 </p>
 <table cellpadding=0 cellspacing=0 border=0>
 <tr>
@@ -875,7 +875,7 @@ EN_MASK
 </tr>
 </table>
 <p>
-Bit mask to independently enable interrupt sources.
+Bit mask to independently enable interrupt sources.<br><br>Bit 0: DMA done.<br>Bit 1: DMA error.<br>Bit 2: Trigger.<br>Bit 3: Acquisition end.
 </p>
 <table cellpadding=0 cellspacing=0 border=0>
 <tr>

--- a/hdl/spec/wb_gen/irq_controller_regs.wb
+++ b/hdl/spec/wb_gen/irq_controller_regs.wb
@@ -7,7 +7,7 @@ peripheral {

  reg {
    name = "Multiple interrupt register";
-    description = "Multiple interrupts occurs before irq source is read.\nWrite '1' to clear a bit.";
+    description = "Multiple interrupts occurs before irq source is read.\nWrite '1' to clear a bit.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
    prefix = "multi_irq";

    field {
@@ -22,7 +22,7 @@ peripheral {

  reg {
    name = "Interrupt sources register ";
-    description = "Indicates the interrupt source.\nWrite '1' to clear a bit.";
+    description = "Indicates the interrupt source.\nWrite '1' to clear a bit.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
    prefix = "src";

    field {
@@ -37,7 +37,7 @@ peripheral {

  reg {
    name = "Interrupt enable mask register";
-    description = "Bit mask to independently enable interrupt sources.";
+    description = "Bit mask to independently enable interrupt sources.\n\nBit 0: DMA done.\nBit 1: DMA error.\nBit 2: Trigger.\nBit 3: Acquisition end.";
    prefix = "en_mask";

    field {