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FMC ADC 100M 14b 4cha - Gateware
Commit b536d7b4 authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Move fmc eic and timetag core to mezzanine (behind the wb bridge). 

-> memory map changed!
parent f0c9a78a
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hdl/adc/rtl/fmc_adc_mezzanine.vhd
View file @ b536d7b4
......@@ -78,14 +78,11 @@ entity fmc_adc_mezzanine is
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
-- Events output pulses (for interrupt and time-stamping)
trigger_p_o : out std_logic;
acq_start_p_o : out std_logic;
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- Interrupts
ddr_wr_fifo_empty_i : in std_logic;
trig_irq_o : out std_logic;
acq_end_irq_o : out std_logic;
eic_irq_o : out std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
......@@ -131,6 +128,28 @@ end fmc_adc_mezzanine;
architecture rtl of fmc_adc_mezzanine is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component fmc_adc_eic
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_trig_i : in std_logic;
irq_acq_end_i : in std_logic
);
end component fmc_adc_eic;
------------------------------------------------------------------------------
-- SDB crossbar constants declaration
--
......@@ -138,7 +157,7 @@ architecture rtl of fmc_adc_mezzanine is
------------------------------------------------------------------------------
-- Number of master port(s) on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 5;
constant c_NUM_WB_MASTERS : integer := 7;
-- Number of slave port(s) on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
......@@ -152,6 +171,8 @@ architecture rtl of fmc_adc_mezzanine is
constant c_WB_SLAVE_FMC_I2C : integer := 2; -- Mezzanine I2C controller
constant c_WB_SLAVE_FMC_ADC : integer := 3; -- Mezzanine ADC core
constant c_WB_SLAVE_FMC_ONEWIRE : integer := 4; -- Mezzanine onewire interface
constant c_WB_SLAVE_FMC_EIC : integer := 5; -- Mezzanine interrupt controller
constant c_WB_SLAVE_TIMETAG : integer := 6; -- Mezzanine timetag core
-- Devices sdb description
constant c_wb_adc_csr_sdb : t_sdb_device := (
......@@ -170,17 +191,51 @@ architecture rtl of fmc_adc_mezzanine is
date => x"20121116",
name => "WB-FMC-ADC-Core ")));
constant c_wb_timetag_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000007F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604",
version => x"00000001",
date => x"20121116",
name => "WB-Timetag-Core ")));
constant c_wb_fmc_adc_eic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"26ec6086", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-FMC-ADC.EIC ")));
-- sdb header address
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(4 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(6 downto 0) :=
(
0 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_spi_sdb, x"00001100"),
2 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001200"),
3 => f_sdb_embed_device(c_wb_adc_csr_sdb, x"00001300"),
4 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001400")
4 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001400"),
5 => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00001500"),
6 => f_sdb_embed_device(c_wb_timetag_sdb, x"00001600")
);
......@@ -220,6 +275,19 @@ architecture rtl of fmc_adc_mezzanine is
signal mezz_owr_en : std_logic_vector(0 downto 0);
signal mezz_owr_i : std_logic_vector(0 downto 0);
-- Interrupts (eic)
signal ddr_wr_fifo_empty_d : std_logic;
signal ddr_wr_fifo_empty_p : std_logic;
signal acq_end_irq_p : std_logic;
signal acq_end_extend : std_logic;
-- Time-tagging core
signal trigger_p : std_logic;
signal acq_start_p : std_logic;
signal acq_stop_p : std_logic;
signal acq_end_p : std_logic;
signal trigger_tag : t_timetag;
begin
......@@ -398,12 +466,12 @@ begin
wb_ddr_ack_i => wb_ddr_ack_i,
wb_ddr_stall_i => wb_ddr_stall_i,
trigger_p_o => trigger_p_o,
acq_start_p_o => acq_start_p_o,
acq_stop_p_o => acq_stop_p_o,
acq_end_p_o => acq_end_p_o,
trigger_p_o => trigger_p,
acq_start_p_o => acq_start_p,
acq_stop_p_o => acq_stop_p,
acq_end_p_o => acq_end_p,
trigger_tag_i => trigger_tag_i,
trigger_tag_i => trigger_tag,
ext_trigger_p_i => ext_trigger_p_i,
ext_trigger_n_i => ext_trigger_n_i,
......@@ -461,4 +529,90 @@ begin
mezz_one_wire_b <= '0' when mezz_owr_en(0) = '1' else 'Z';
mezz_owr_i(0) <= mezz_one_wire_b;
------------------------------------------------------------------------------
-- FMC0 interrupt controller
------------------------------------------------------------------------------
cmp_fmc0_eic : fmc_adc_eic
port map(
rst_n_i => sys_rst_n_i,
clk_sys_i => sys_clk_i,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_FMC_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_FMC_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_FMC_EIC).stall,
wb_int_o => eic_irq_o,
irq_trig_i => trigger_p,
irq_acq_end_i => acq_end_irq_p
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC_EIC).int <= '0';
-- Detects end of adc core writing to ddr
p_ddr_wr_fifo_empty : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
ddr_wr_fifo_empty_d <= ddr_wr_fifo_empty_i;
end if;
end process p_ddr_wr_fifo_empty;
ddr_wr_fifo_empty_p <= ddr_wr_fifo_empty_i and not(ddr_wr_fifo_empty_d);
-- End of acquisition interrupt generation
p_acq_end_extend : process (sys_clk_i)
begin
if rising_edge(sys_clk_i) then
if sys_rst_n_i = '0' then
acq_end_extend <= '0';
elsif acq_end_p = '1' then
acq_end_extend <= '1';
elsif ddr_wr_fifo_empty_p = '1' then
acq_end_extend <= '0';
end if;
end if;
end process p_acq_end_extend;
acq_end_irq_p <= ddr_wr_fifo_empty_p and acq_end_extend;
trig_irq_o <= trigger_p;
acq_end_irq_o <= acq_end_irq_p;
------------------------------------------------------------------------------
-- Time-tagging core
------------------------------------------------------------------------------
cmp_timetag_core : timetag_core
port map(
clk_i => sys_clk_i,
rst_n_i => sys_rst_n_i,
trigger_p_i => trigger_p,
acq_start_p_i => acq_start_p,
acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p,
trig_tag_o => trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TIMETAG).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_TIMETAG).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_TIMETAG).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_TIMETAG).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_TIMETAG).ack
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TIMETAG).err <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).rty <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).stall <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).int <= '0';
end rtl;
hdl/adc/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ b536d7b4
......@@ -53,7 +53,7 @@ package fmc_adc_mezzanine_pkg is
component fmc_adc_mezzanine
generic(
g_multishot_ram_size : natural := 2048;
g_carrier_type : string := "SPEC"
g_carrier_type : string := "SPEC"
);
port (
-- Clock, reset
......@@ -82,14 +82,11 @@ package fmc_adc_mezzanine_pkg is
wb_ddr_ack_i : in std_logic;
wb_ddr_stall_i : in std_logic;
-- Events output pulses (for interrupt and time-stamping)
trigger_p_o : out std_logic;
acq_start_p_o : out std_logic;
acq_stop_p_o : out std_logic;
acq_end_p_o : out std_logic;
-- Trigger time-tag input
trigger_tag_i : t_timetag;
-- Interrupt
ddr_wr_fifo_empty_i : in std_logic;
trig_irq_o : out std_logic;
acq_end_irq_o : out std_logic;
eic_irq_o : out std_logic;
-- FMC interface
ext_trigger_p_i : in std_logic; -- External trigger
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ b536d7b4
......@@ -201,25 +201,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
);
end component carrier_csr;
component fmc_adc_eic
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
irq_trig_i : in std_logic;
irq_acq_end_i : in std_logic
);
end component fmc_adc_eic;
component dma_eic
port (
rst_n_i : in std_logic;
......@@ -247,7 +228,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- Number of master port(s) on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 8;
constant c_NUM_WB_MASTERS : integer := 6;
-- Number of slave port(s) on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
......@@ -261,9 +242,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
constant c_WB_SLAVE_SPEC_CSR : integer := 2; -- SPEC control and status registers
constant c_WB_SLAVE_VIC : integer := 3; -- Vectored interrupt controller
constant c_WB_SLAVE_DMA_EIC : integer := 4; -- DMA interrupt controller
constant c_WB_SLAVE_FMC0_EIC : integer := 5; -- FMC0 interrupt controller
constant c_WB_SLAVE_TIMETAG : integer := 6; -- TIMETAG core for time-tagging
constant c_WB_SLAVE_FMC_ADC : integer := 7; -- FMC ADC mezzanine
constant c_WB_SLAVE_FMC_ADC : integer := 5; -- FMC ADC mezzanine
-- Devices sdb description
constant c_wb_dma_ctrl_sdb : t_sdb_device := (
......@@ -298,22 +277,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_wb_timetag_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000007F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604",
version => x"00000001",
date => x"20121116",
name => "WB-Timetag-Core ")));
constant c_wb_dma_eic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
......@@ -330,22 +293,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
date => x"20131204",
name => "WB-DMA.EIC ")));
constant c_wb_fmc_adc_eic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"26ec6086", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-FMC-ADC.EIC ")));
-- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- Note: sdb_addr is the sdb records address relative to the bridge base address
constant c_fmc0_bridge_sdb : t_sdb_bridge := f_xwb_bridge_manual_sdb(x"00001fff", x"00000000");
......@@ -354,24 +301,22 @@ architecture rtl of spec_top_fmc_adc_100Ms is
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(10 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(8 downto 0) :=
(
0 => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001100"),
2 => f_sdb_embed_device(c_wb_spec_csr_sdb, x"00001200"),
3 => f_sdb_embed_device(c_xwb_vic_sdb, x"00001300"),
4 => f_sdb_embed_device(c_wb_dma_eic_sdb, x"00001400"),
5 => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00002000"),
6 => f_sdb_embed_device(c_wb_timetag_sdb, x"00002100"),
7 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00004000"),
8 => f_sdb_embed_repo_url(c_repo_url_sdb),
9 => f_sdb_embed_synthesis(c_synthesis_sdb),
10 => f_sdb_embed_integration(c_integration_sdb)
0 => f_sdb_embed_device(c_wb_dma_ctrl_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001100"),
2 => f_sdb_embed_device(c_wb_spec_csr_sdb, x"00001200"),
3 => f_sdb_embed_device(c_xwb_vic_sdb, x"00001300"),
4 => f_sdb_embed_device(c_wb_dma_eic_sdb, x"00001400"),
5 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00002000"),
6 => f_sdb_embed_repo_url(c_repo_url_sdb),
7 => f_sdb_embed_synthesis(c_synthesis_sdb),
8 => f_sdb_embed_integration(c_integration_sdb)
);
-- VIC default vector setting
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00002000",
(0 => x"00003500",
1 => x"00001400");
------------------------------------------------------------------------------
......@@ -444,18 +389,16 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal wb_ddr_stall : std_logic;
-- Interrupts stuff
signal dma_irq : std_logic_vector(1 downto 0);
signal dma_irq_p : std_logic_vector(1 downto 0);
signal irq_sources : std_logic_vector(3 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(3 downto 0);
signal ddr_wr_fifo_empty : std_logic;
signal ddr_wr_fifo_empty_d : std_logic;
signal ddr_wr_fifo_empty_p : std_logic;
signal acq_end_irq_p : std_logic;
signal acq_end : std_logic;
signal dma_eic_irq : std_logic;
signal fmc0_eic_irq : std_logic;
signal dma_irq : std_logic_vector(1 downto 0);
signal dma_irq_p : std_logic_vector(1 downto 0);
signal trig_irq_p : std_logic;
signal acq_end_irq_p : std_logic;
signal irq_sources : std_logic_vector(3 downto 0);
signal irq_to_gn4124 : std_logic;
signal irq_sources_2_led : std_logic_vector(3 downto 0);
signal ddr_wr_fifo_empty : std_logic;
signal dma_eic_irq : std_logic;
signal fmc0_eic_irq : std_logic;
-- LED control from carrier CSR register
signal led_red : std_logic;
......@@ -484,13 +427,6 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal carrier_owr_en : std_logic_vector(0 downto 0);
signal carrier_owr_i : std_logic_vector(0 downto 0);
-- Time-tagging core
signal trigger_p : std_logic;
signal acq_start_p : std_logic;
signal acq_stop_p : std_logic;
signal acq_end_p : std_logic;
signal trigger_tag : t_timetag;
-- led pwm
signal led_pwm_update_cnt : unsigned(9 downto 0);
signal led_pwm_update : std_logic;
......@@ -783,37 +719,6 @@ begin
led_red_o <= led_red;
led_green_o <= led_green;
------------------------------------------------------------------------------
-- Time-tagging core
------------------------------------------------------------------------------
cmp_timetag_core : timetag_core
port map(
clk_i => sys_clk_125,
rst_n_i => fmc0_rst_n,
trigger_p_i => trigger_p,
acq_start_p_i => acq_start_p,
acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p,
trig_tag_o => trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_TIMETAG).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_TIMETAG).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_TIMETAG).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_TIMETAG).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_TIMETAG).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_TIMETAG).ack
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_TIMETAG).err <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).rty <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).stall <= '0';
cnx_master_in(c_WB_SLAVE_TIMETAG).int <= '0';
------------------------------------------------------------------------------
-- Vectored interrupt controller (VIC)
------------------------------------------------------------------------------
......@@ -832,58 +737,6 @@ begin
irqs_i(1) => dma_eic_irq,
irq_master_o => irq_to_gn4124);
------------------------------------------------------------------------------
-- FMC0 interrupt controller
------------------------------------------------------------------------------
cmp_fmc0_eic : fmc_adc_eic
port map(
rst_n_i => sys_rst_n,
clk_sys_i => sys_clk_125,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC0_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_FMC0_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_FMC0_EIC).stall,
wb_int_o => fmc0_eic_irq,
irq_trig_i => trigger_p,
irq_acq_end_i => acq_end_irq_p
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC0_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_EIC).int <= '0';
-- Detects end of adc core writing to ddr
p_ddr_wr_fifo_empty : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
ddr_wr_fifo_empty_d <= ddr_wr_fifo_empty;
end if;
end process p_ddr_wr_fifo_empty;
ddr_wr_fifo_empty_p <= ddr_wr_fifo_empty and not(ddr_wr_fifo_empty_d);
-- End of acquisition interrupt generation
p_acq_end : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
acq_end <= '0';
elsif acq_end_p = '1' then
acq_end <= '1';
elsif ddr_wr_fifo_empty_p = '1' then
acq_end <= '0';
end if;
end if;
end process p_acq_end;
acq_end_irq_p <= ddr_wr_fifo_empty_p and acq_end;
------------------------------------------------------------------------------
-- GN4124 DMA interrupt controller
------------------------------------------------------------------------------
......@@ -912,11 +765,13 @@ begin
------------------------------------------------------------------------------
-- FMC ADC mezzanine (wb bridge)
-- Mezzanine system managment I2C master
-- Mezzanine SPI master
-- Mezzanine I2C
-- ADC core
-- Mezzanine 1-wire master
-- System managment I2C master
-- SPI master
-- I2C
-- ADC core csr
-- 1-wire master
-- eic
-- timetag core
------------------------------------------------------------------------------
cmp_fmc_adc_mezzanine_0 : fmc_adc_mezzanine
generic map(
......@@ -947,12 +802,10 @@ begin
wb_ddr_ack_i => wb_ddr_ack,
wb_ddr_stall_i => wb_ddr_stall,
trigger_p_o => trigger_p,
acq_start_p_o => acq_start_p,
acq_stop_p_o => acq_stop_p,
acq_end_p_o => acq_end_p,
trigger_tag_i => trigger_tag,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty,
trig_irq_o => trig_irq_p,
acq_end_irq_o => acq_end_irq_p,
eic_irq_o => fmc0_eic_irq,
ext_trigger_p_i => adc0_ext_trigger_p_i,
ext_trigger_n_i => adc0_ext_trigger_n_i,
......@@ -1170,7 +1023,7 @@ begin
-- 2 -> Trigger
-- 3 -> End of acquisition (data written to DDR)
irq_sources(1 downto 0) <= dma_irq;
irq_sources(2) <= trigger_p;
irq_sources(2) <= trig_irq_p;
irq_sources(3) <= acq_end_irq_p;
gen_irq_led : for I in 0 to irq_sources'length-1 generate
......
hdl/svec/rtl/svec_top_fmc_adc_100Ms.vhd
View file @ b536d7b4
......@@ -306,7 +306,7 @@ architecture rtl of svec_top_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- Number of master port(s) on the wishbone crossbar
constant c_NUM_WB_MASTERS : integer := 14;
constant c_NUM_WB_MASTERS : integer := 10;
-- Number of slave port(s) on the wishbone crossbar
constant c_NUM_WB_SLAVES : integer := 1;
......@@ -315,20 +315,16 @@ architecture rtl of svec_top_fmc_adc_100Ms is
constant c_WB_MASTER_VME : integer := 0;
-- Wishbone slave(s)
constant c_WB_SLAVE_I2C : integer := 0; -- Carrier I2C master
constant c_WB_SLAVE_ONEWIRE : integer := 1; -- Carrier onewire interface
constant c_WB_SLAVE_SVEC_CSR : integer := 2; -- SVEC control and status registers
constant c_WB_SLAVE_VIC : integer := 3; -- Vectored interrupt controller
constant c_WB_SLAVE_FMC0_EIC : integer := 4; -- FMC slot 1 interrupt controller
constant c_WB_SLAVE_FMC0_TIMETAG : integer := 5; -- FMC slot 1 timetag core
constant c_WB_SLAVE_FMC0_DDR_ADR : integer := 6; -- FMC slot 1 DDR address
constant c_WB_SLAVE_FMC0_DDR_DAT : integer := 7; -- FMC slot 1 DDR data
constant c_WB_SLAVE_FMC0_ADC : integer := 8; -- FMC slot 1 ADC mezzanine
constant c_WB_SLAVE_FMC1_EIC : integer := 9; -- FMC slot 2 interrupt controller
constant c_WB_SLAVE_FMC1_TIMETAG : integer := 10; -- FMC slot 2 timetag core
constant c_WB_SLAVE_FMC1_DDR_ADR : integer := 11; -- FMC slot 2 DDR address
constant c_WB_SLAVE_FMC1_DDR_DAT : integer := 12; -- FMC slot 2 DDR data
constant c_WB_SLAVE_FMC1_ADC : integer := 13; -- FMC slot 2 ADC mezzanine
constant c_WB_SLAVE_I2C : integer := 0; -- Carrier I2C master
constant c_WB_SLAVE_ONEWIRE : integer := 1; -- Carrier onewire interface
constant c_WB_SLAVE_SVEC_CSR : integer := 2; -- SVEC control and status registers
constant c_WB_SLAVE_VIC : integer := 3; -- Vectored interrupt controller
constant c_WB_SLAVE_FMC0_ADC : integer := 4; -- FMC slot 1 ADC mezzanine
constant c_WB_SLAVE_FMC0_DDR_ADR : integer := 5; -- FMC slot 1 DDR address
constant c_WB_SLAVE_FMC0_DDR_DAT : integer := 6; -- FMC slot 1 DDR data
constant c_WB_SLAVE_FMC1_ADC : integer := 7; -- FMC slot 2 ADC mezzanine
constant c_WB_SLAVE_FMC1_DDR_ADR : integer := 8; -- FMC slot 2 DDR address
constant c_WB_SLAVE_FMC1_DDR_DAT : integer := 9; -- FMC slot 2 DDR data
-- Devices sdb description
......@@ -348,38 +344,6 @@ architecture rtl of svec_top_fmc_adc_100Ms is
date => x"20121116",
name => "WB-SVEC-CSR ")));
constant c_wb_timetag_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000007F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"00000604",
version => x"00000001",
date => x"20121116",
name => "WB-Timetag-Core ")));
constant c_wb_fmc_adc_eic_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
wbd_endian => c_sdb_endian_big,
wbd_width => x"4", -- 32-bit port granularity
sdb_component => (
addr_first => x"0000000000000000",
addr_last => x"000000000000000F",
product => (
vendor_id => x"000000000000CE42", -- CERN
device_id => x"26ec6086", -- "WB-FMC-ADC.EIC " | md5sum | cut -c1-8
version => x"00000001",
date => x"20131204",
name => "WB-FMC-ADC.EIC ")));
constant c_wb_ddr_dat_sdb : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
......@@ -421,31 +385,27 @@ architecture rtl of svec_top_fmc_adc_100Ms is
constant c_SDB_ADDRESS : t_wishbone_address := x"00000000";
-- Wishbone crossbar layout
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(16 downto 0) :=
constant c_INTERCONNECT_LAYOUT : t_sdb_record_array(12 downto 0) :=
(
0 => f_sdb_embed_device(c_xwb_i2c_master_sdb, x"00001000"),
1 => f_sdb_embed_device(c_xwb_onewire_master_sdb, x"00001100"),
2 => f_sdb_embed_device(c_wb_svec_csr_sdb, x"00001200"),
3 => f_sdb_embed_device(c_xwb_vic_sdb, x"00001300"),
4 => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00002000"),
5 => f_sdb_embed_device(c_wb_timetag_sdb, x"00002100"),
6 => f_sdb_embed_device(c_wb_ddr_adr_sdb, x"00002200"),
7 => f_sdb_embed_device(c_wb_ddr_dat_sdb, x"00003000"),
8 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00004000"),
9 => f_sdb_embed_device(c_wb_fmc_adc_eic_sdb, x"00006000"),
10 => f_sdb_embed_device(c_wb_timetag_sdb, x"00006100"),
11 => f_sdb_embed_device(c_wb_ddr_adr_sdb, x"00006200"),
12 => f_sdb_embed_device(c_wb_ddr_dat_sdb, x"00007000"),
13 => f_sdb_embed_bridge(c_fmc1_bridge_sdb, x"00008000"),
14 => f_sdb_embed_repo_url(c_repo_url_sdb),
15 => f_sdb_embed_synthesis(c_synthesis_sdb),
16 => f_sdb_embed_integration(c_integration_sdb)
4 => f_sdb_embed_bridge(c_fmc0_bridge_sdb, x"00002000"),
5 => f_sdb_embed_device(c_wb_ddr_adr_sdb, x"00004000"),
6 => f_sdb_embed_device(c_wb_ddr_dat_sdb, x"00005000"),
7 => f_sdb_embed_bridge(c_fmc1_bridge_sdb, x"00006000"),
8 => f_sdb_embed_device(c_wb_ddr_adr_sdb, x"00008000"),
9 => f_sdb_embed_device(c_wb_ddr_dat_sdb, x"00009000"),
10 => f_sdb_embed_repo_url(c_repo_url_sdb),
11 => f_sdb_embed_synthesis(c_synthesis_sdb),
12 => f_sdb_embed_integration(c_integration_sdb)
);
-- VIC default vector setting
constant c_VIC_VECTOR_TABLE : t_wishbone_address_array(0 to 1) :=
(0 => x"00002000",
1 => x"00006000");
(0 => x"00003500",
1 => x"00007500");
------------------------------------------------------------------------------
-- Other constants declaration
......@@ -534,18 +494,14 @@ architecture rtl of svec_top_fmc_adc_100Ms is
-- Interrupts stuff
signal ddr_wr_fifo_empty : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal ddr_wr_fifo_empty_d : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal ddr_wr_fifo_empty_d1 : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal ddr_wr_fifo_empty_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_end_irq_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_end_extend : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal trig_irq_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal fmc0_trig_irq_led : std_logic;
signal fmc0_acq_end_irq_led : std_logic;
signal irq_to_vme : std_logic;
signal irq_to_vme_t : std_logic;
signal irq_to_vme_sync : std_logic;
signal fmc0_irq : std_logic;
signal fmc1_irq : std_logic;
signal fmc_irq : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
-- Front panel LED control
signal led_state : std_logic_vector(15 downto 0);
......@@ -577,14 +533,6 @@ architecture rtl of svec_top_fmc_adc_100Ms is
signal carrier_sda_out : std_logic;
signal carrier_sda_oe_n : std_logic;
-- Time-tagging core
signal trig_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_start_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_stop_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal acq_end_p : std_logic_vector(c_NB_FMC_SLOTS-1 downto 0);
signal fmc0_trigger_tag : t_timetag;
signal fmc1_trigger_tag : t_timetag;
-- led pwm
signal led_pwm_update_cnt : unsigned(9 downto 0);
signal led_pwm_update : std_logic;
......@@ -783,7 +731,7 @@ begin
vme_sync_master_in <= cnx_slave_out(c_WB_MASTER_VME);
-- Interrupt line synchronisation to vme 62.5MHz
p_irq_to_vme_sync : process (sys_clk_62_5)
p_irq_to_vme_sync : process (sys_clk_62_5, powerup_rst_n)
begin
if powerup_rst_n = '0' then
irq_to_vme_t <= '0';
......@@ -929,100 +877,10 @@ begin
rst_n_i => sys_rst_n,
slave_i => cnx_master_out(c_WB_SLAVE_VIC),
slave_o => cnx_master_in(c_WB_SLAVE_VIC),
irqs_i(0) => fmc0_irq,
irqs_i(1) => fmc1_irq,
irqs_i(0) => fmc_irq(0),
irqs_i(1) => fmc_irq(1),
irq_master_o => irq_to_vme);
------------------------------------------------------------------------------
-- FMC0 interrupt controller
------------------------------------------------------------------------------
cmp_fmc0_eic : fmc_adc_eic
port map(
rst_n_i => fmc0_rst_n,
clk_sys_i => sys_clk_125,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC0_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_FMC0_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_FMC0_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_FMC0_EIC).stall,
wb_int_o => fmc0_irq,
irq_trig_i => trig_p(0),
irq_acq_end_i => acq_end_irq_p(0)
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC0_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_EIC).int <= '0';
------------------------------------------------------------------------------
-- FMC1 interrupt controller
------------------------------------------------------------------------------
cmp_fmc1_eic : fmc_adc_eic
port map(
rst_n_i => fmc1_rst_n,
clk_sys_i => sys_clk_125,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).adr(3 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC1_EIC).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_FMC1_EIC).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_FMC1_EIC).ack,
wb_stall_o => cnx_master_in(c_WB_SLAVE_FMC1_EIC).stall,
wb_int_o => fmc1_irq,
irq_trig_i => trig_p(1),
irq_acq_end_i => acq_end_irq_p(1)
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC1_EIC).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_EIC).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_EIC).int <= '0';
------------------------------------------------------------------------------
-- End of acquisition interrupt generation
------------------------------------------------------------------------------
-- Detects end of adc core writing to ddr
l_ddr_wr_fifo_empty : for I in 0 to c_NB_FMC_SLOTS-1 generate
p_ddr_wr_fifo_empty : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if fmc0_rst_n = '0' or fmc1_rst_n = '0' then
ddr_wr_fifo_empty_d(I) <= '0';
ddr_wr_fifo_empty_d1(I) <= '0';
else
ddr_wr_fifo_empty_d(I) <= ddr_wr_fifo_empty(I);
ddr_wr_fifo_empty_d1(I) <= ddr_wr_fifo_empty_d(I);
end if;
end if;
end process p_ddr_wr_fifo_empty;
ddr_wr_fifo_empty_p(I) <= ddr_wr_fifo_empty_d(I) and not(ddr_wr_fifo_empty_d1(I));
end generate l_ddr_wr_fifo_empty;
-- End of acquisition interrupt generation
l_acq_end_irq : for I in 0 to c_NB_FMC_SLOTS-1 generate
p_acq_end_extend : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if fmc0_rst_n = '0' or fmc1_rst_n = '0' then
acq_end_extend(I) <= '0';
elsif acq_end_p(I) = '1' then
acq_end_extend(I) <= '1';
elsif ddr_wr_fifo_empty_p(I) = '1' then
acq_end_extend(I) <= '0';
end if;
end if;
end process p_acq_end_extend;
acq_end_irq_p(I) <= ddr_wr_fifo_empty_p(I) and acq_end_extend(I);
end generate l_acq_end_irq;
------------------------------------------------------------------------------
-- Slot 1 : FMC ADC mezzanine (wb bridge)
-- Mezzanine system managment I2C master
......@@ -1060,12 +918,10 @@ begin
wb_ddr_ack_i => wb_ddr0_adc_ack,
wb_ddr_stall_i => wb_ddr0_adc_stall,
trigger_p_o => trig_p(0),
acq_start_p_o => acq_start_p(0),
acq_stop_p_o => acq_stop_p(0),
acq_end_p_o => acq_end_p(0),
trigger_tag_i => fmc0_trigger_tag,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty(0),
trig_irq_o => trig_irq_p(0),
acq_end_irq_o => acq_end_irq_p(0),
eic_irq_o => fmc_irq(0),
ext_trigger_p_i => adc0_ext_trigger_p_i,
ext_trigger_n_i => adc0_ext_trigger_n_i,
......@@ -1148,12 +1004,10 @@ begin
wb_ddr_ack_i => wb_ddr1_adc_ack,
wb_ddr_stall_i => wb_ddr1_adc_stall,
trigger_p_o => trig_p(1),
acq_start_p_o => acq_start_p(1),
acq_stop_p_o => acq_stop_p(1),
acq_end_p_o => acq_end_p(1),
trigger_tag_i => fmc1_trigger_tag,
ddr_wr_fifo_empty_i => ddr_wr_fifo_empty(1),
trig_irq_o => trig_irq_p(1),
acq_end_irq_o => acq_end_irq_p(1),
eic_irq_o => fmc_irq(1),
ext_trigger_p_i => adc1_ext_trigger_p_i,
ext_trigger_n_i => adc1_ext_trigger_n_i,
......@@ -1503,68 +1357,6 @@ begin
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).stall <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_DDR_ADR).int <= '0';
------------------------------------------------------------------------------
-- FMC slot 1 : Time-tagging core
------------------------------------------------------------------------------
cmp_fmc0_timetag_core : timetag_core
port map(
clk_i => sys_clk_125,
rst_n_i => fmc0_rst_n,
trigger_p_i => trig_p(0),
acq_start_p_i => acq_start_p(0),
acq_stop_p_i => acq_stop_p(0),
acq_end_p_i => acq_end_p(0),
trig_tag_o => fmc0_trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_FMC0_TIMETAG).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).ack
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).stall <= '0';
cnx_master_in(c_WB_SLAVE_FMC0_TIMETAG).int <= '0';
------------------------------------------------------------------------------
-- FMC slot 2 : Time-tagging core
------------------------------------------------------------------------------
cmp_fmc1_timetag_core : timetag_core
port map(
clk_i => sys_clk_125,
rst_n_i => fmc1_rst_n,
trigger_p_i => trig_p(1),
acq_start_p_i => acq_start_p(1),
acq_stop_p_i => acq_stop_p(1),
acq_end_p_i => acq_end_p(1),
trig_tag_o => fmc1_trigger_tag,
wb_adr_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).dat,
wb_cyc_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).cyc,
wb_sel_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).sel,
wb_stb_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).stb,
wb_we_i => cnx_master_out(c_WB_SLAVE_FMC1_TIMETAG).we,
wb_ack_o => cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).ack
);
-- Unused wishbone signals
cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).err <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).rty <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).stall <= '0';
cnx_master_in(c_WB_SLAVE_FMC1_TIMETAG).int <= '0';
------------------------------------------------------------------------------
-- Front panel LED control
--
......@@ -1605,7 +1397,7 @@ begin
port map (
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
pulse_i => trig_p(0),
pulse_i => trig_irq_p(0),
extended_o => fmc0_trig_irq_led
);
......@@ -1638,7 +1430,7 @@ begin
led_state(11 downto 10) <= fmc0_acq_end_irq_led & '0';
-- LED 7 :
led_state(13 downto 12) <= '0' & fmc0_irq;
led_state(13 downto 12) <= '0' & fmc_irq(0);
-- LED 8 :
led_state(15 downto 14) <= '0' & irq_to_vme_sync;
......
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