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FMC ADC 100M 14b 4cha - Gateware
Commit b7fbece5 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: Introduce separate trigger delays for external and internal (channel) triggers.

parent d7472f32
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doc/manual/fmc_adc_100Ms_csr.tex
View file @ b7fbece5
......@@ -23,8 +23,8 @@ REG @tab
Trigger polarity
@item @code{0x14} @tab
REG @tab
@code{trig_dly} @tab
Trigger delay
@code{ext_trig_dly} @tab
External trigger delay
@item @code{0x18} @tab
REG @tab
@code{sw_trig} @tab
......@@ -89,6 +89,10 @@ Channel 1 saturation register
REG @tab
@code{ch1_trig_thres} @tab
Channel 1 trigger threshold configuration register
@item @code{0x98} @tab
REG @tab
@code{ch1_trig_dly} @tab
Channel 1 trigger delay
@item @code{0x100} @tab
REG @tab
@code{ch2_ctl} @tab
......@@ -113,6 +117,10 @@ Channel 2 saturation register
REG @tab
@code{ch2_trig_thres} @tab
Channel 2 trigger threshold configuration register
@item @code{0x118} @tab
REG @tab
@code{ch2_trig_dly} @tab
Channel 2 trigger delay
@item @code{0x180} @tab
REG @tab
@code{ch3_ctl} @tab
......@@ -137,6 +145,10 @@ Channel 3 saturation register
REG @tab
@code{ch3_trig_thres} @tab
Channel 3 trigger threshold configuration register
@item @code{0x198} @tab
REG @tab
@code{ch3_trig_dly} @tab
Channel 3 trigger delay
@item @code{0x200} @tab
REG @tab
@code{ch4_ctl} @tab
......@@ -161,6 +173,10 @@ Channel 4 saturation register
REG @tab
@code{ch4_trig_thres} @tab
Channel 4 trigger threshold configuration register
@item @code{0x218} @tab
REG @tab
@code{ch4_trig_dly} @tab
Channel 4 trigger delay
@end multitable
@regsection @code{ctl} - Control register
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -375,18 +391,18 @@ Channel 4 internal threshold trigger
@item @code{ch3} @tab 0: positive edge/slope@*1: negative edge/slope
@item @code{ch4} @tab 0: positive edge/slope@*1: negative edge/slope
@end multitable
@regsection @code{trig_dly} - Trigger delay
@regsection @code{ext_trig_dly} - External trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{TRIG_DLY}
@code{EXT_TRIG_DLY}
@tab @code{0} @tab
Trigger delay value
External trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@item @code{ext_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{sw_trig} - Software trigger
Writing (anything) to this register generates a software trigger.
......@@ -599,6 +615,19 @@ Internal trigger threshold hysteresis
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch1_trig_dly} - Channel 1 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH1_TRIG_DLY}
@tab @code{0} @tab
Channel 1 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch1_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{ch2_ctl} - Channel 2 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -683,6 +712,19 @@ Internal trigger threshold hysteresis
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch2_trig_dly} - Channel 2 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH2_TRIG_DLY}
@tab @code{0} @tab
Channel 2 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch2_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{ch3_ctl} - Channel 3 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -767,6 +809,19 @@ Internal trigger threshold hysteresis
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch3_trig_dly} - Channel 3 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH3_TRIG_DLY}
@tab @code{0} @tab
Channel 3 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch3_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
@regsection @code{ch4_ctl} - Channel 4 control register
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -851,3 +906,16 @@ Internal trigger threshold hysteresis
@item @code{val} @tab Treated as binary two's complement and compared to raw ADC data.
@item @code{hyst} @tab Configures the internal trigger threshold hysteresis (two's complement).
@end multitable
@regsection @code{ch4_trig_dly} - Channel 4 trigger delay
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{CH4_TRIG_DLY}
@tab @code{0} @tab
Channel 4 trigger delay value
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{ch4_trig_dly} @tab Delay to apply on the trigger in sampling clock period.@*The default clock frequency is 100MHz (period = 10ns).
@end multitable
hdl/adc/rtl/fmc_adc_100Ms_core.vhd
View file @ b7fbece5
This diff is collapsed.
hdl/adc/rtl/fmc_adc_100Ms_csr.vhd
View file @ b7fbece5
This diff is collapsed.
hdl/adc/rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
View file @ b7fbece5
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Jan 25 09:51:59 2018
-- Created : Fri Jan 26 15:37:35 2018
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -88,7 +88,7 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
trig_pol_ch2_o : std_logic;
trig_pol_ch3_o : std_logic;
trig_pol_ch4_o : std_logic;
trig_dly_o : std_logic_vector(31 downto 0);
ext_trig_dly_o : std_logic_vector(31 downto 0);
sw_trig_o : std_logic_vector(31 downto 0);
sw_trig_wr_o : std_logic;
shots_nb_o : std_logic_vector(15 downto 0);
......@@ -101,24 +101,28 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch1_sat_val_o : std_logic_vector(14 downto 0);
ch1_trig_thres_val_o : std_logic_vector(15 downto 0);
ch1_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch1_trig_dly_o : std_logic_vector(31 downto 0);
ch2_ctl_ssr_o : std_logic_vector(6 downto 0);
ch2_gain_val_o : std_logic_vector(15 downto 0);
ch2_offset_val_o : std_logic_vector(15 downto 0);
ch2_sat_val_o : std_logic_vector(14 downto 0);
ch2_trig_thres_val_o : std_logic_vector(15 downto 0);
ch2_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch2_trig_dly_o : std_logic_vector(31 downto 0);
ch3_ctl_ssr_o : std_logic_vector(6 downto 0);
ch3_gain_val_o : std_logic_vector(15 downto 0);
ch3_offset_val_o : std_logic_vector(15 downto 0);
ch3_sat_val_o : std_logic_vector(14 downto 0);
ch3_trig_thres_val_o : std_logic_vector(15 downto 0);
ch3_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch3_trig_dly_o : std_logic_vector(31 downto 0);
ch4_ctl_ssr_o : std_logic_vector(6 downto 0);
ch4_gain_val_o : std_logic_vector(15 downto 0);
ch4_offset_val_o : std_logic_vector(15 downto 0);
ch4_sat_val_o : std_logic_vector(14 downto 0);
ch4_trig_thres_val_o : std_logic_vector(15 downto 0);
ch4_trig_thres_hyst_o : std_logic_vector(15 downto 0);
ch4_trig_dly_o : std_logic_vector(31 downto 0);
end record;
constant c_fmc_adc_100ms_csr_out_registers_init_value: t_fmc_adc_100ms_csr_out_registers := (
......@@ -142,7 +146,7 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
trig_pol_ch2_o => '0',
trig_pol_ch3_o => '0',
trig_pol_ch4_o => '0',
trig_dly_o => (others => '0'),
ext_trig_dly_o => (others => '0'),
sw_trig_o => (others => '0'),
sw_trig_wr_o => '0',
shots_nb_o => (others => '0'),
......@@ -155,24 +159,28 @@ package fmc_adc_100ms_csr_wbgen2_pkg is
ch1_sat_val_o => (others => '0'),
ch1_trig_thres_val_o => (others => '0'),
ch1_trig_thres_hyst_o => (others => '0'),
ch1_trig_dly_o => (others => '0'),
ch2_ctl_ssr_o => (others => '0'),
ch2_gain_val_o => (others => '0'),
ch2_offset_val_o => (others => '0'),
ch2_sat_val_o => (others => '0'),
ch2_trig_thres_val_o => (others => '0'),
ch2_trig_thres_hyst_o => (others => '0'),
ch2_trig_dly_o => (others => '0'),
ch3_ctl_ssr_o => (others => '0'),
ch3_gain_val_o => (others => '0'),
ch3_offset_val_o => (others => '0'),
ch3_sat_val_o => (others => '0'),
ch3_trig_thres_val_o => (others => '0'),
ch3_trig_thres_hyst_o => (others => '0'),
ch3_trig_dly_o => (others => '0'),
ch4_ctl_ssr_o => (others => '0'),
ch4_gain_val_o => (others => '0'),
ch4_offset_val_o => (others => '0'),
ch4_sat_val_o => (others => '0'),
ch4_trig_thres_val_o => (others => '0'),
ch4_trig_thres_hyst_o => (others => '0')
ch4_trig_thres_hyst_o => (others => '0'),
ch4_trig_dly_o => (others => '0')
);
function "or" (left, right: t_fmc_adc_100ms_csr_in_registers) return t_fmc_adc_100ms_csr_in_registers;
function f_x_to_zero (x:std_logic) return std_logic;
......
hdl/adc/wb_gen/fmc_adc_100Ms_csr.h
View file @ b7fbece5
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Thu Jan 25 09:52:00 2018
* Created : Fri Jan 26 15:37:35 2018
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -141,7 +141,7 @@
/* definitions for field: Channel 4 internal threshold trigger in reg: Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL_CH4 WBGEN2_GEN_MASK(11, 1)
/* definitions for register: Trigger delay */
/* definitions for register: External trigger delay */
/* definitions for register: Software trigger */
......@@ -235,6 +235,8 @@
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 1 trigger delay */
/* definitions for register: Channel 2 control register */
/* definitions for field: Solid state relays control for channel 2 in reg: Channel 2 control register */
......@@ -289,6 +291,8 @@
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 2 trigger delay */
/* definitions for register: Channel 3 control register */
/* definitions for field: Solid state relays control for channel 3 in reg: Channel 3 control register */
......@@ -343,6 +347,8 @@
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 3 trigger delay */
/* definitions for register: Channel 4 control register */
/* definitions for field: Solid state relays control for channel 4 in reg: Channel 4 control register */
......@@ -397,6 +403,8 @@
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_W(value) WBGEN2_GEN_WRITE(value, 16, 16)
#define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_R(reg) WBGEN2_GEN_READ(reg, 16, 16)
/* definitions for register: Channel 4 trigger delay */
PACKED struct FMC_ADC_100MS_CSR_WB {
/* [0x0]: REG Control register */
uint32_t CTL;
......@@ -408,8 +416,8 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t TRIG_EN;
/* [0x10]: REG Trigger polarity */
uint32_t TRIG_POL;
/* [0x14]: REG Trigger delay */
uint32_t TRIG_DLY;
/* [0x14]: REG External trigger delay */
uint32_t EXT_TRIG_DLY;
/* [0x18]: REG Software trigger */
uint32_t SW_TRIG;
/* [0x1c]: REG Number of shots */
......@@ -444,8 +452,10 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t CH1_SAT;
/* [0x94]: REG Channel 1 trigger threshold configuration register */
uint32_t CH1_TRIG_THRES;
/* [0x98]: REG Channel 1 trigger delay */
uint32_t CH1_TRIG_DLY;
/* padding to: 64 words */
uint32_t __padding_1[26];
uint32_t __padding_1[25];
/* [0x100]: REG Channel 2 control register */
uint32_t CH2_CTL;
/* [0x104]: REG Channel 2 status register */
......@@ -458,8 +468,10 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t CH2_SAT;
/* [0x114]: REG Channel 2 trigger threshold configuration register */
uint32_t CH2_TRIG_THRES;
/* [0x118]: REG Channel 2 trigger delay */
uint32_t CH2_TRIG_DLY;
/* padding to: 96 words */
uint32_t __padding_2[26];
uint32_t __padding_2[25];
/* [0x180]: REG Channel 3 control register */
uint32_t CH3_CTL;
/* [0x184]: REG Channel 3 status register */
......@@ -472,8 +484,10 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t CH3_SAT;
/* [0x194]: REG Channel 3 trigger threshold configuration register */
uint32_t CH3_TRIG_THRES;
/* [0x198]: REG Channel 3 trigger delay */
uint32_t CH3_TRIG_DLY;
/* padding to: 128 words */
uint32_t __padding_3[26];
uint32_t __padding_3[25];
/* [0x200]: REG Channel 4 control register */
uint32_t CH4_CTL;
/* [0x204]: REG Channel 4 status register */
......@@ -486,6 +500,8 @@ PACKED struct FMC_ADC_100MS_CSR_WB {
uint32_t CH4_SAT;
/* [0x214]: REG Channel 4 trigger threshold configuration register */
uint32_t CH4_TRIG_THRES;
/* [0x218]: REG Channel 4 trigger delay */
uint32_t CH4_TRIG_DLY;
};
#endif
hdl/adc/wb_gen/fmc_adc_100Ms_csr.htm
View file @ b7fbece5
This diff is collapsed.
hdl/adc/wb_gen/fmc_adc_100Ms_csr.wb
View file @ b7fbece5
......@@ -368,11 +368,11 @@ peripheral {
};
reg {
name = "Trigger delay";
prefix = "trig_dly";
name = "External trigger delay";
prefix = "ext_trig_dly";
field {
name = "Trigger delay value";
name = "External trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
......@@ -707,6 +707,20 @@ peripheral {
};
};
reg {
name = "Channel 1 trigger delay";
prefix = "ch1_trig_dly";
field {
name = "Channel 1 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 2 control register";
prefix = "ch2_ctl";
......@@ -867,6 +881,20 @@ peripheral {
};
};
reg {
name = "Channel 2 trigger delay";
prefix = "ch2_trig_dly";
field {
name = "Channel 2 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 3 control register";
prefix = "ch3_ctl";
......@@ -1027,6 +1055,20 @@ peripheral {
};
};
reg {
name = "Channel 3 trigger delay";
prefix = "ch3_trig_dly";
field {
name = "Channel 3 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
name = "Channel 4 control register";
prefix = "ch4_ctl";
......@@ -1187,4 +1229,18 @@ peripheral {
};
};
reg {
name = "Channel 4 trigger delay";
prefix = "ch4_trig_dly";
field {
name = "Channel 4 trigger delay value";
description = "Delay to apply on the trigger in sampling clock period.\nThe default clock frequency is 100MHz (period = 10ns).";
type = SLV;
size = 32;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
};
hdl/spec/testbench/include/fmc_adc_100Ms_csr.v
View file @ b7fbece5
......@@ -63,7 +63,7 @@
`define FMC_ADC_100MS_CSR_TRIG_POL_CH3 32'h00000400
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_POL_CH4 32'h00000800
`define ADDR_FMC_ADC_100MS_CSR_TRIG_DLY 10'h14
`define ADDR_FMC_ADC_100MS_CSR_EXT_TRIG_DLY 10'h14
`define ADDR_FMC_ADC_100MS_CSR_SW_TRIG 10'h18
`define ADDR_FMC_ADC_100MS_CSR_SHOTS 10'h1c
`define FMC_ADC_100MS_CSR_SHOTS_NB_OFFSET 0
......@@ -100,6 +100,7 @@
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH1_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH1_TRIG_DLY 10'h98
`define ADDR_FMC_ADC_100MS_CSR_CH2_CTL 10'h100
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH2_CTL_SSR 32'h0000007f
......@@ -120,6 +121,7 @@
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH2_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_DLY 10'h118
`define ADDR_FMC_ADC_100MS_CSR_CH3_CTL 10'h180
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH3_CTL_SSR 32'h0000007f
......@@ -140,6 +142,7 @@
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH3_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_DLY 10'h198
`define ADDR_FMC_ADC_100MS_CSR_CH4_CTL 10'h200
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR_OFFSET 0
`define FMC_ADC_100MS_CSR_CH4_CTL_SSR 32'h0000007f
......@@ -160,3 +163,4 @@
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_VAL 32'h0000ffff
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST_OFFSET 16
`define FMC_ADC_100MS_CSR_CH4_TRIG_THRES_HYST 32'hffff0000
`define ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_DLY 10'h218
hdl/spec/testbench/top/main.sv
View file @ b7fbece5
......@@ -273,6 +273,8 @@ module main;
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_EXT_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_EXT_TRIG_DLY, 3);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000002);
......
hdl/spec/testbench/top/wave.do
View file @ b7fbece5
......@@ -32,7 +32,6 @@ add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_ack_i
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/l2p_dma_stall_i
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/p2l_dma_cyc_i
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/fifo_rst_n
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_rd
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_wr
add wave -noupdate -group l2p_dma /main/DUT/cmp_gn4124_core/cmp_l2p_dma_master/data_fifo_empty
......@@ -291,14 +290,19 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_n
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_data
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_thres
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_ch_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_d
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_d
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_fixed_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sw_trig_fixed_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/time_trig_fixed_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_empty
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_full
......@@ -307,9 +311,10 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_din
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_fifo_dout
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_storage
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/ext_trig_delay_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_delay
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/int_trig_delay_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/undersample_factor
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/undersample_cnt
......
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