Commit ba9e347f authored by Matthieu Cattin's avatar Matthieu Cattin

syn: Synthesis with meta-info

parent db95bb6e
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Thu Mar 07 12:40:49 2013
pcbe15575:: Thu Mar 07 18:50:59 2013
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
......@@ -125,25 +125,25 @@ Phase 1 : 45135 unrouted; REAL time: 19 secs
Phase 2 : 34792 unrouted; REAL time: 24 secs
Phase 3 : 14548 unrouted; REAL time: 52 secs
Phase 3 : 14548 unrouted; REAL time: 51 secs
Phase 4 : 14581 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 56 secs
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 40 secs
Phase 5 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 38 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 40 secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 38 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 40 secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 38 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 40 secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins 38 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 40 secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 39 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 43 secs
Total REAL time to Router completion: 1 mins 43 secs
Total CPU time to Router completion: 1 mins 43 secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 42 secs
Total REAL time to Router completion: 1 mins 42 secs
Total CPU time to Router completion: 1 mins 42 secs
Partition Implementation Status
-------------------------------
......@@ -482,8 +482,8 @@ All signals are completely routed.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 46 secs
Total CPU time to PAR completion: 1 mins 47 secs
Total REAL time to PAR completion: 1 mins 45 secs
Total CPU time to PAR completion: 1 mins 45 secs
Peak Memory Usage: 347 MB
......
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......@@ -2163,7 +2163,7 @@ Design statistics:
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Thu Mar 7 12:43:02 2013
Analysis completed Thu Mar 7 18:53:11 2013
--------------------------------------------------------------------------------
Trace Settings:
......
......@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Mar 7 12:35:52 2013
Mapped Date : Thu Mar 7 18:46:02 2013
Design Summary
--------------
......@@ -104,7 +104,7 @@ Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 417 MB
Total REAL time to MAP completion: 4 mins 50 secs
Total CPU time to MAP completion (all processors): 4 mins 53 secs
Total CPU time to MAP completion (all processors): 4 mins 52 secs
Table of Contents
-----------------
......
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