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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
ba9e347f
Commit
ba9e347f
authored
Mar 07, 2013
by
Matthieu Cattin
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syn: Synthesis with meta-info
parent
db95bb6e
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spec_top_fmc_adc_100Ms.par
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
+12
-12
spec_top_fmc_adc_100Ms.syr
hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
+53
-53
spec_top_fmc_adc_100Ms.twr
hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
+1
-1
spec_top_fmc_adc_100Ms_map.mrp
hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
+2
-2
No files found.
hdl/spec/syn/spec_top_fmc_adc_100Ms.par
View file @
ba9e347f
Release 13.3 par O.76xd (lin)
Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
pcbe15575:: Thu Mar 07 1
2:40:4
9 2013
pcbe15575:: Thu Mar 07 1
8:50:5
9 2013
par -w -intstyle ise -ol high -mt off spec_top_fmc_adc_100Ms_map.ncd
spec_top_fmc_adc_100Ms.ncd spec_top_fmc_adc_100Ms.pcf
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@@ -125,25 +125,25 @@ Phase 1 : 45135 unrouted; REAL time: 19 secs
Phase 2 : 34792 unrouted; REAL time: 24 secs
Phase 3 : 14548 unrouted; REAL time: 5
2
secs
Phase 3 : 14548 unrouted; REAL time: 5
1
secs
Phase 4 : 14581 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 56 secs
Updating file: spec_top_fmc_adc_100Ms.ncd with current fully routed design.
Phase 5 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins
40
secs
Phase 5 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins
38
secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins
40
secs
Phase 6 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins
38
secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins
40
secs
Phase 7 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins
38
secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins
40
secs
Phase 8 : 0 unrouted; (Setup:0, Hold:1455, Component Switching Limit:0) REAL time: 1 mins
38
secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins
40
secs
Phase 9 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins
39
secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 4
3
secs
Total REAL time to Router completion: 1 mins 4
3
secs
Total CPU time to Router completion: 1 mins 4
3
secs
Phase 10 : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0) REAL time: 1 mins 4
2
secs
Total REAL time to Router completion: 1 mins 4
2
secs
Total CPU time to Router completion: 1 mins 4
2
secs
Partition Implementation Status
-------------------------------
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@@ -482,8 +482,8 @@ All signals are completely routed.
WARNING:Par:283 - There are 6 loadless signals in this design. This design will cause Bitgen to issue DRC warnings.
Total REAL time to PAR completion: 1 mins 4
6
secs
Total CPU time to PAR completion: 1 mins 4
7
secs
Total REAL time to PAR completion: 1 mins 4
5
secs
Total CPU time to PAR completion: 1 mins 4
5
secs
Peak Memory Usage: 347 MB
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hdl/spec/syn/spec_top_fmc_adc_100Ms.syr
View file @
ba9e347f
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hdl/spec/syn/spec_top_fmc_adc_100Ms.twr
View file @
ba9e347f
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@@ -2163,7 +2163,7 @@ Design statistics:
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Thu Mar 7 1
2:43:02
2013
Analysis completed Thu Mar 7 1
8:53:11
2013
--------------------------------------------------------------------------------
Trace Settings:
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hdl/spec/syn/spec_top_fmc_adc_100Ms_map.mrp
View file @
ba9e347f
...
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@@ -11,7 +11,7 @@ Target Device : xc6slx45t
Target Package : fgg484
Target Speed : -3
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date : Thu Mar 7 1
2:35:5
2 2013
Mapped Date : Thu Mar 7 1
8:46:0
2 2013
Design Summary
--------------
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@@ -104,7 +104,7 @@ Average Fanout of Non-Clock Nets: 3.79
Peak Memory Usage: 417 MB
Total REAL time to MAP completion: 4 mins 50 secs
Total CPU time to MAP completion (all processors): 4 mins 5
3
secs
Total CPU time to MAP completion (all processors): 4 mins 5
2
secs
Table of Contents
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