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FMC ADC 100M 14b 4cha - Gateware
Commit bb84018b authored by Matthieu Cattin's avatar Matthieu Cattin
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hdl: Change utc core name into timetag core.

parent 2d06837c
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hdl/spec/rtl/Manifest.py
View file @ bb84018b
files = [
"spec_top_fmc_adc_100Ms.vhd",
"carrier_csr.vhd",
"utc_core_regs.vhd",
"utc_core.vhd",
"timetag_core_regs.vhd",
"timetag_core.vhd",
"irq_controller_regs.vhd",
"irq_controller.vhd",
"sdb_meta_pkg.vhd"];
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ bb84018b
......@@ -197,7 +197,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
);
end component carrier_csr;
component utc_core
component timetag_core
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
......@@ -214,7 +214,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end component utc_core;
end component timetag_core;
component irq_controller
port (
......@@ -253,7 +253,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
constant c_SLAVE_DMA : integer := 0; -- DMA controller in the Gennum core
constant c_SLAVE_ONEWIRE : integer := 1; -- Carrier onewire interface
constant c_SLAVE_SPEC_CSR : integer := 2; -- SPEC control and status registers
constant c_SLAVE_UTC : integer := 3; -- UTC core for time-tagging
constant c_SLAVE_TIMETAG : integer := 3; -- TIMETAG core for time-tagging
constant c_SLAVE_INT : integer := 4; -- Interrupt controller
constant c_SLAVE_FMC_SYS_I2C : integer := 5; -- Mezzanine system I2C interface (EEPROM)
constant c_SLAVE_FMC_SPI : integer := 6; -- Mezzanine SPI interface
......@@ -311,7 +311,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
date => x"20121116",
name => "WB-SPEC-CSR ")));
constant c_UTC_SDB_DEVICE : t_sdb_device := (
constant c_TIMETAG_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
abi_ver_major => x"01",
abi_ver_minor => x"01",
......@@ -325,7 +325,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
device_id => x"00000604",
version => x"00000001",
date => x"20121116",
name => "WB-UTC-Core ")));
name => "WB-Timetag-Core ")));
constant c_INT_SDB_DEVICE : t_sdb_device := (
abi_class => x"0000", -- undocumented device
......@@ -400,7 +400,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
0 => f_sdb_embed_device(c_DMA_SDB_DEVICE, x"00001000"),
1 => f_sdb_embed_device(c_ONEWIRE_SDB_DEVICE, x"00001200"),
2 => f_sdb_embed_device(c_SPEC_CSR_SDB_DEVICE, x"00001300"),
3 => f_sdb_embed_device(c_UTC_SDB_DEVICE, x"00001400"),
3 => f_sdb_embed_device(c_TIMETAG_SDB_DEVICE, x"00001400"),
4 => f_sdb_embed_device(c_INT_SDB_DEVICE, x"00001500"),
5 => f_sdb_embed_device(c_I2C_SDB_DEVICE, x"00001600"),
6 => f_sdb_embed_device(c_SPI_SDB_DEVICE, x"00001700"),
......@@ -540,7 +540,7 @@ architecture rtl of spec_top_fmc_adc_100Ms is
signal carrier_owr_en : std_logic_vector(0 downto 0);
signal carrier_owr_i : std_logic_vector(0 downto 0);
-- UTC core
-- Time-tagging core
signal trigger_p : std_logic;
signal acq_start_p : std_logic;
signal acq_stop_p : std_logic;
......@@ -818,9 +818,9 @@ begin
led_green_o <= led_green;
------------------------------------------------------------------------------
-- UTC core
-- Time-tagging core
------------------------------------------------------------------------------
cmp_utc_core : utc_core
cmp_timetag_core : timetag_core
port map(
clk_i => sys_clk_125,
rst_n_i => sys_rst_n,
......@@ -830,21 +830,21 @@ begin
acq_stop_p_i => acq_stop_p,
acq_end_p_i => acq_end_p,
wb_adr_i => cnx_master_out(c_SLAVE_UTC).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_SLAVE_UTC).dat,
wb_dat_o => cnx_master_in(c_SLAVE_UTC).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_UTC).cyc,
wb_sel_i => cnx_master_out(c_SLAVE_UTC).sel,
wb_stb_i => cnx_master_out(c_SLAVE_UTC).stb,
wb_we_i => cnx_master_out(c_SLAVE_UTC).we,
wb_ack_o => cnx_master_in(c_SLAVE_UTC).ack
wb_adr_i => cnx_master_out(c_SLAVE_TIMETAG).adr(6 downto 2), -- cnx_master_out.adr is byte address
wb_dat_i => cnx_master_out(c_SLAVE_TIMETAG).dat,
wb_dat_o => cnx_master_in(c_SLAVE_TIMETAG).dat,
wb_cyc_i => cnx_master_out(c_SLAVE_TIMETAG).cyc,
wb_sel_i => cnx_master_out(c_SLAVE_TIMETAG).sel,
wb_stb_i => cnx_master_out(c_SLAVE_TIMETAG).stb,
wb_we_i => cnx_master_out(c_SLAVE_TIMETAG).we,
wb_ack_o => cnx_master_in(c_SLAVE_TIMETAG).ack
);
-- Unused wishbone signals
cnx_master_in(c_SLAVE_UTC).err <= '0';
cnx_master_in(c_SLAVE_UTC).rty <= '0';
cnx_master_in(c_SLAVE_UTC).stall <= '0';
cnx_master_in(c_SLAVE_UTC).int <= '0';
cnx_master_in(c_SLAVE_TIMETAG).err <= '0';
cnx_master_in(c_SLAVE_TIMETAG).rty <= '0';
cnx_master_in(c_SLAVE_TIMETAG).stall <= '0';
cnx_master_in(c_SLAVE_TIMETAG).int <= '0';
------------------------------------------------------------------------------
-- Interrupt controller
......
hdl/spec/wb_gen/Makefile
View file @ bb84018b
......@@ -6,7 +6,7 @@ carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
utc_core_regs:
timetag_core_regs:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
......
hdl/spec/wb_gen/utc_core_regs.h → hdl/spec/wb_gen/timetag_core_regs.h
View file @ bb84018b
/*
Register definitions for slave core: UTC core registers
Register definitions for slave core: Time-tagging core registers
* File : utc_core_regs.h
* Author : auto-generated by wbgen2 from utc_core_regs.wb
* Created : Tue Apr 9 18:41:27 2013
* File : timetag_core_regs.h
* Author : auto-generated by wbgen2 from timetag_core_regs.wb
* Created : Fri May 3 16:52:50 2013
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE utc_core_regs.wb
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_UTC_CORE_REGS_WB
#define __WBGEN2_REGDEFS_UTC_CORE_REGS_WB
#ifndef __WBGEN2_REGDEFS_TIMETAG_CORE_REGS_WB
#define __WBGEN2_REGDEFS_TIMETAG_CORE_REGS_WB
#include <inttypes.h>
......@@ -31,13 +31,13 @@
#endif
/* definitions for register: UTC seconds register */
/* definitions for register: Timetag seconds register */
/* definitions for register: UTC coarse time register, system clock ticks (125MHz) */
/* definitions for register: Timetag coarse time register, system clock ticks (125MHz) */
/* definitions for register: Trigger time-tag metadata register */
/* definitions for register: Trigger time-tag UTC seconds register */
/* definitions for register: Trigger time-tag seconds register */
/* definitions for register: Trigger time-tag coarse time (system clock ticks 125MHz) register */
......@@ -45,7 +45,7 @@
/* definitions for register: Acquisition start time-tag metadata register */
/* definitions for register: Acquisition start time-tag UTC seconds register */
/* definitions for register: Acquisition start time-tag seconds register */
/* definitions for register: Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
......@@ -53,7 +53,7 @@
/* definitions for register: Acquisition stop time-tag metadata register */
/* definitions for register: Acquisition stop time-tag UTC seconds register */
/* definitions for register: Acquisition stop time-tag seconds register */
/* definitions for register: Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
......@@ -61,20 +61,20 @@
/* definitions for register: Acquisition end time-tag metadata register */
/* definitions for register: Acquisition end time-tag UTC seconds register */
/* definitions for register: Acquisition end time-tag seconds register */
/* definitions for register: Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
/* definitions for register: Acquisition end time-tag fine time register, always 0 (used for time-tag format compatibility) */
PACKED struct UTC_CORE_WB {
/* [0x0]: REG UTC seconds register */
PACKED struct TIMETAG_CORE_WB {
/* [0x0]: REG Timetag seconds register */
uint32_t SECONDS;
/* [0x4]: REG UTC coarse time register, system clock ticks (125MHz) */
/* [0x4]: REG Timetag coarse time register, system clock ticks (125MHz) */
uint32_t COARSE;
/* [0x8]: REG Trigger time-tag metadata register */
uint32_t TRIG_TAG_META;
/* [0xc]: REG Trigger time-tag UTC seconds register */
/* [0xc]: REG Trigger time-tag seconds register */
uint32_t TRIG_TAG_SECONDS;
/* [0x10]: REG Trigger time-tag coarse time (system clock ticks 125MHz) register */
uint32_t TRIG_TAG_COARSE;
......@@ -82,7 +82,7 @@ PACKED struct UTC_CORE_WB {
uint32_t TRIG_TAG_FINE;
/* [0x18]: REG Acquisition start time-tag metadata register */
uint32_t ACQ_START_TAG_META;
/* [0x1c]: REG Acquisition start time-tag UTC seconds register */
/* [0x1c]: REG Acquisition start time-tag seconds register */
uint32_t ACQ_START_TAG_SECONDS;
/* [0x20]: REG Acquisition start time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_START_TAG_COARSE;
......@@ -90,7 +90,7 @@ PACKED struct UTC_CORE_WB {
uint32_t ACQ_START_TAG_FINE;
/* [0x28]: REG Acquisition stop time-tag metadata register */
uint32_t ACQ_STOP_TAG_META;
/* [0x2c]: REG Acquisition stop time-tag UTC seconds register */
/* [0x2c]: REG Acquisition stop time-tag seconds register */
uint32_t ACQ_STOP_TAG_SECONDS;
/* [0x30]: REG Acquisition stop time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_STOP_TAG_COARSE;
......@@ -98,7 +98,7 @@ PACKED struct UTC_CORE_WB {
uint32_t ACQ_STOP_TAG_FINE;
/* [0x38]: REG Acquisition end time-tag metadata register */
uint32_t ACQ_END_TAG_META;
/* [0x3c]: REG Acquisition end time-tag UTC seconds register */
/* [0x3c]: REG Acquisition end time-tag seconds register */
uint32_t ACQ_END_TAG_SECONDS;
/* [0x40]: REG Acquisition end time-tag coarse time (system clock ticks 125MHz) register */
uint32_t ACQ_END_TAG_COARSE;
......
hdl/spec/wb_gen/timetag_core_regs.htm 0 → 100644
View file @ bb84018b
This diff is collapsed.
hdl/spec/wb_gen/utc_core_regs.wb → hdl/spec/wb_gen/timetag_core_regs.wb
View file @ bb84018b
peripheral {
name = "UTC core registers";
description = "Wishbone slave for registers related to UTC core";
hdl_entity = "utc_core_regs";
name = "Time-tagging core registers";
description = "Wishbone slave for registers related to time-tagging core";
hdl_entity = "timetag_core_regs";
prefix = "utc_core";
prefix = "timetag_core";
reg {
name = "UTC seconds register";
description = "UTC seconds counter. Incremented everytime the UTC coarse counter overflows.";
name = "Timetag seconds register";
description = "Seconds counter. Incremented everytime the coarse counter overflows.";
prefix = "seconds";
field {
name = "UTC seconds";
name = "Timetag seconds";
type = SLV;
load = LOAD_EXT;
size = 32;
......@@ -21,12 +21,12 @@ peripheral {
};
reg {
name = "UTC coarse time register, system clock ticks (125MHz)";
description = "UTC coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
name = "Timetag coarse time register, system clock ticks (125MHz)";
description = "Coarse time counter clocked by 125MHz system clock.\nCounts from 0 to 125000000.";
prefix = "coarse";
field {
name = "UTC coarse time";
name = "Timetag coarse time";
type = SLV;
load = LOAD_EXT;
size = 32;
......@@ -50,12 +50,12 @@ peripheral {
};
reg {
name = "Trigger time-tag UTC seconds register";
name = "Trigger time-tag seconds register";
prefix = "trig_tag_seconds";
field {
name = "Trigger time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last trigger event";
name = "Trigger time-tag seconds";
description = "Holds time-tag seconds of the last trigger event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -106,12 +106,12 @@ peripheral {
};
reg {
name = "Acquisition start time-tag UTC seconds register";
name = "Acquisition start time-tag seconds register";
prefix = "acq_start_tag_seconds";
field {
name = "Acquisition start time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last acquisition start event";
name = "Acquisition start time-tag seconds";
description = "Holds time-tag seconds of the last acquisition start event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -162,12 +162,12 @@ peripheral {
};
reg {
name = "Acquisition stop time-tag UTC seconds register";
name = "Acquisition stop time-tag seconds register";
prefix = "acq_stop_tag_seconds";
field {
name = "Acquisition stop time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last acquisition stop event";
name = "Acquisition stop time-tag seconds";
description = "Holds time-tag seconds of the last acquisition stop event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......@@ -218,12 +218,12 @@ peripheral {
};
reg {
name = "Acquisition end time-tag UTC seconds register";
name = "Acquisition end time-tag seconds register";
prefix = "acq_end_tag_seconds";
field {
name = "Acquisition end time-tag UTC seconds";
description = "Holds time-tag UTC seconds of the last acquisition end event";
name = "Acquisition end time-tag seconds";
description = "Holds time-tag seconds of the last acquisition end event";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......
hdl/spec/wb_gen/utc_core_regs.htm deleted 100644 → 0
View file @ 2d06837c
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