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FMC ADC 100M 14b 4cha - Gateware
Commits
bfce7558
Commit
bfce7558
authored
Apr 01, 2016
by
Dimitris Lampridis
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hdl/testbench: corrected and expanded new system verilog testbench for SPEC. Tested, works
parent
cdaafa33
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9 changed files
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288 additions
and
141 deletions
+288
-141
.gitignore
.gitignore
+13
-7
Manifest.py
hdl/spec/testbench/top/Manifest.py
+14
-4
ddr3.v
hdl/spec/testbench/top/ddr3/ddr3.v
+1
-0
ddr3_parameters.vh
hdl/spec/testbench/top/ddr3/ddr3_parameters.vh
+2
-1
gn4124_bfm.svh
hdl/spec/testbench/top/gn4124_bfm/gn4124_bfm.svh
+23
-23
gn412x_bfm.vhd
hdl/spec/testbench/top/gn4124_bfm/gn412x_bfm.vhd
+8
-6
main.sv
hdl/spec/testbench/top/main.sv
+107
-76
run.do
hdl/spec/testbench/top/run.do
+1
-1
wave.do
hdl/spec/testbench/top/wave.do
+119
-23
No files found.
.gitignore
View file @
bfce7558
...
@@ -5,6 +5,12 @@ hdl/*/sim/vsim.wlf
...
@@ -5,6 +5,12 @@ hdl/*/sim/vsim.wlf
hdl/*/sim/Makefile
hdl/*/sim/Makefile
hdl/*/sim/modelsim.ini
hdl/*/sim/modelsim.ini
hdl/*/sim/work/
hdl/*/sim/work/
hdl/*/testbench/top/transcript
hdl/*/testbench/top/vsim.wlf
hdl/*/testbench/top/Makefile
hdl/*/testbench/top/modelsim.ini
hdl/*/testbench/top/work/
hdl/*/testbench/top/NullFile
hdl/*/sim/fifo_generator_v6_1/
hdl/*/sim/fifo_generator_v6_1/
hdl/*/syn/_ngo/
hdl/*/syn/_ngo/
hdl/*/syn/_xmsgs/
hdl/*/syn/_xmsgs/
...
@@ -56,13 +62,13 @@ hdl/*/syn/*_summary.html
...
@@ -56,13 +62,13 @@ hdl/*/syn/*_summary.html
hdl/*/release/
hdl/*/release/
hdl/*/chipscope/*.vcd
hdl/*/chipscope/*.vcd
hdl/*/chipscope/*.wlf
hdl/*/chipscope/*.wlf
hdl/svec/sim/testbench/fifo_generator_v6_1/
hdl/svec/sim/testbench/
top/
fifo_generator_v6_1/
hdl/svec/sim/testbench/modelsim.ini
hdl/svec/sim/testbench/
top/
modelsim.ini
hdl/svec/sim/testbench/simdrv_defs.svh
hdl/svec/sim/testbench/
top/
simdrv_defs.svh
hdl/svec/sim/testbench/transcript
hdl/svec/sim/testbench/t
op/t
ranscript
hdl/svec/sim/testbench/vsim.wlf
hdl/svec/sim/testbench/
top/
vsim.wlf
hdl/svec/sim/testbench/vsim_stacktrace.vstf
hdl/svec/sim/testbench/
top/
vsim_stacktrace.vstf
hdl/svec/sim/testbench/work/
hdl/svec/sim/testbench/
top/
work/
doc/manual/*.html
doc/manual/*.html
*.texi
*.texi
*.aux
*.aux
...
...
hdl/spec/testbench/top/Manifest.py
View file @
bfce7558
...
@@ -6,10 +6,20 @@ fetchto = "../../ip_cores"
...
@@ -6,10 +6,20 @@ fetchto = "../../ip_cores"
syn_device
=
"xc6slx45t"
syn_device
=
"xc6slx45t"
include_dirs
=
[
"../include"
,
"gn4124_bfm"
,
"ddr3"
]
include_dirs
=
[
"../include"
,
"gn4124_bfm"
,
"ddr3"
]
files
=
[
"main.sv"
,
"ddr3/ddr3.v"
]
files
=
[
"main.sv"
,
"ddr3/ddr3.v"
,
"../../../ip_cores/adc_serdes.vhd"
,
"../../../ip_cores/monostable/monostable_rtl.vhd"
,
"../../../ip_cores/ext_pulse_sync/ext_pulse_sync_rtl.vhd"
,
"../../../ip_cores/utils/utils_pkg.vhd"
]
modules
=
{
"local"
:
[
"../../rtl"
,
"gn4124_bfm"
,
"../../../adc/rtl"
,
"../../../ip_cores/timetag_core/rtl"
,
modules
=
{
"local"
:
[
"../../rtl"
,
"../../../ip_cores/general-cores"
,
"../../../ip_cores/ddr3-sp6-core"
,
"gn4124_bfm"
,
"../../../ip_cores/gn4124-core"
]};
"../../../adc/rtl"
,
"../../../ip_cores/timetag_core/rtl"
,
"../../../ip_cores/general-cores"
,
"../../../ip_cores/ddr3-sp6-core"
,
"../../../ip_cores/gn4124-core"
]};
ctrls
=
[
"bank3_64b_32b"
]
ctrls
=
[
"bank3_64b_32b"
]
hdl/spec/testbench/top/ddr3/ddr3.v
View file @
bfce7558
...
@@ -80,6 +80,7 @@
...
@@ -80,6 +80,7 @@
// model flags
// model flags
// `define MODEL_PASR
// `define MODEL_PASR
`define
sg15
module
ddr3
(
module
ddr3
(
rst_n
,
rst_n
,
...
...
hdl/spec/testbench/top/ddr3/ddr3_parameters.vh
View file @
bfce7558
...
@@ -559,7 +559,8 @@
...
@@ -559,7 +559,8 @@
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TWLO = 9000; // tWLO ps Write levelization output delay
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter TAA_MIN = 12500; // TAA ps Internal READ command to first data
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
parameter CL_TIME = 12500; // CL ps Minimum CAS Latency
`else `define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
`else
`define sg25 // sg25 is equivalent to the JEDEC DDR3-800E (6-6-6) speed bin
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TCK_MIN = 2500; // tCK ps Minimum Clock Cycle Time
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_PER = 100; // tJIT(per) ps Period JItter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
parameter TJIT_CC = 200; // tJIT(cc) ps Cycle to Cycle jitter
...
...
hdl/spec/testbench/top/gn4124_bfm/gn4124_bfm.svh
View file @
bfce7558
...
@@ -229,29 +229,29 @@ endinterface
...
@@ -229,29 +229,29 @@ endinterface
/* Helper macro for wiring Gennum-Xilinx ports in spec_top */
/* Helper macro for wiring Gennum-Xilinx ports in spec_top */
`define
GENNUM_WIRE_SPEC_PINS
(
IF_NAME
)
\
`define
GENNUM_WIRE_SPEC_PINS
(
IF_NAME
)
\
.
L_RST_N
(
IF_NAME
.
SYS
.
rst_n
),
\
.
L_RST_N
(
IF_NAME
.
rst_n
),
\
.
L_CLKp
(
IF_NAME
.
SYS
.
lclk_p
),
\
.
L_CLKp
(
IF_NAME
.
lclk_p
),
\
.
L_CLKn
(
IF_NAME
.
SYS
.
lclk_n
),
\
.
L_CLKn
(
IF_NAME
.
lclk_n
),
\
.
p2l_clkp
(
IF_NAME
.
P2L
.
p2l_clk_p
),
\
.
p2l_clkp
(
IF_NAME
.
p2l_clk_p
),
\
.
p2l_clkn
(
IF_NAME
.
P2L
.
p2l_clk_n
),
\
.
p2l_clkn
(
IF_NAME
.
p2l_clk_n
),
\
.
p2l_data
(
IF_NAME
.
P2L
.
p2l_data
),
\
.
p2l_data
(
IF_NAME
.
p2l_data
),
\
.
p2l_dframe
(
IF_NAME
.
P2L
.
p2l_dframe
),
\
.
p2l_dframe
(
IF_NAME
.
p2l_dframe
),
\
.
p2l_valid
(
IF_NAME
.
P2L
.
p2l_valid
),
\
.
p2l_valid
(
IF_NAME
.
p2l_valid
),
\
.
p2l_rdy
(
IF_NAME
.
P2L
.
p2l_rdy
),
\
.
p2l_rdy
(
IF_NAME
.
p2l_rdy
),
\
.
p_wr_req
(
IF_NAME
.
P2L
.
p_wr_req
),
\
.
p_wr_req
(
IF_NAME
.
p_wr_req
),
\
.
p_wr_rdy
(
IF_NAME
.
P2L
.
p_wr_rdy
),
\
.
p_wr_rdy
(
IF_NAME
.
p_wr_rdy
),
\
.
rx_error
(
IF_NAME
.
P2L
.
rx_error
),
\
.
rx_error
(
IF_NAME
.
rx_error
),
\
.
l2p_clkp
(
IF_NAME
.
L2P
.
l2p_clk_p
),
\
.
l2p_clkp
(
IF_NAME
.
l2p_clk_p
),
\
.
l2p_clkn
(
IF_NAME
.
L2P
.
l2p_clk_n
),
\
.
l2p_clkn
(
IF_NAME
.
l2p_clk_n
),
\
.
l2p_data
(
IF_NAME
.
L2P
.
l2p_data
),
\
.
l2p_data
(
IF_NAME
.
l2p_data
),
\
.
l2p_dframe
(
IF_NAME
.
L2P
.
l2p_dframe
),
\
.
l2p_dframe
(
IF_NAME
.
l2p_dframe
),
\
.
l2p_valid
(
IF_NAME
.
L2P
.
l2p_valid
),
\
.
l2p_valid
(
IF_NAME
.
l2p_valid
),
\
.
l2p_edb
(
IF_NAME
.
L2P
.
l2p_edb
),
\
.
l2p_edb
(
IF_NAME
.
l2p_edb
),
\
.
l2p_rdy
(
IF_NAME
.
L2P
.
l2p_rdy
),
\
.
l2p_rdy
(
IF_NAME
.
l2p_rdy
),
\
.
l_wr_rdy
(
IF_NAME
.
L2P
.
l_wr_rdy
),
\
.
l_wr_rdy
(
IF_NAME
.
l_wr_rdy
),
\
.
p_rd_d_rdy
(
IF_NAME
.
L2P
.
p_rd_d_rdy
),
\
.
p_rd_d_rdy
(
IF_NAME
.
p_rd_d_rdy
),
\
.
tx_error
(
IF_NAME
.
L2P
.
tx_error
),
\
.
tx_error
(
IF_NAME
.
tx_error
),
\
.
vc_rdy
(
IF_NAME
.
P2L
.
vc_rdy
)
.
vc_rdy
(
IF_NAME
.
vc_rdy
)
`endif
// `ifndef __GN4124_BFM_SVH
`endif
// `ifndef __GN4124_BFM_SVH
hdl/spec/testbench/top/gn4124_bfm/gn412x_bfm.vhd
View file @
bfce7558
...
@@ -911,8 +911,8 @@ CMD <= f_cmd_to_string(CMD_INT);
...
@@ -911,8 +911,8 @@ CMD <= f_cmd_to_string(CMD_INT);
--
--
--#########################################################################--
--#########################################################################--
process
process
--
file OUT_FILE : text is out "STD_OUTPUT";
file
OUT_FILE
:
text
is
out
"STD_OUTPUT"
;
file
OUT_FILE
:
text
open
write_mode
is
"NullFile"
;
--
file OUT_FILE : text open write_mode is "NullFile";
variable
OUTPUT_LINE
:
line
;
variable
OUTPUT_LINE
:
line
;
variable
ERR_CNT
:
integer
;
variable
ERR_CNT
:
integer
;
variable
L_CMD
:
string
(
1
to
80
);
variable
L_CMD
:
string
(
1
to
80
);
...
@@ -2231,8 +2231,8 @@ writeline(OUT_FILE, OUTPUT_LINE);
...
@@ -2231,8 +2231,8 @@ writeline(OUT_FILE, OUTPUT_LINE);
--
--
--#########################################################################--
--#########################################################################--
process
process
--
file OUT_FILE : text is out "STD_OUTPUT";
file
OUT_FILE
:
text
is
out
"STD_OUTPUT"
;
file
OUT_FILE
:
text
open
write_mode
is
"NullFile"
;
--
file OUT_FILE : text open write_mode is "NullFile";
variable
OUTPUT_LINE
:
line
;
variable
OUTPUT_LINE
:
line
;
variable
HEADER_TC
:
std_ulogic_vector
(
2
downto
0
);
variable
HEADER_TC
:
std_ulogic_vector
(
2
downto
0
);
...
@@ -2675,7 +2675,8 @@ writeline(OUT_FILE, OUTPUT_LINE);
...
@@ -2675,7 +2675,8 @@ writeline(OUT_FILE, OUTPUT_LINE);
end
process
;
end
process
;
process
process
file
OUT_FILE
:
text
open
write_mode
is
"NullFile"
;
file
OUT_FILE
:
text
is
out
"STD_OUTPUT"
;
--file OUT_FILE : text open write_mode is "NullFile";
variable
OUTPUT_LINE
:
line
;
variable
OUTPUT_LINE
:
line
;
variable
vHEADER
:
std_ulogic_vector
(
31
downto
0
);
variable
vHEADER
:
std_ulogic_vector
(
31
downto
0
);
variable
vADDRESS
:
std_ulogic_vector
(
63
downto
0
);
variable
vADDRESS
:
std_ulogic_vector
(
63
downto
0
);
...
@@ -2801,7 +2802,8 @@ writeline(OUT_FILE, OUTPUT_LINE);
...
@@ -2801,7 +2802,8 @@ writeline(OUT_FILE, OUTPUT_LINE);
--
--
--#########################################################################--
--#########################################################################--
process
process
file
OUT_FILE
:
text
open
write_mode
is
"NullFile"
;
file
OUT_FILE
:
text
is
out
"STD_OUTPUT"
;
--file OUT_FILE : text open write_mode is "NullFile";
variable
OUTPUT_LINE
:
line
;
variable
OUTPUT_LINE
:
line
;
variable
vHEADER
:
std_ulogic_vector
(
31
downto
0
);
variable
vHEADER
:
std_ulogic_vector
(
31
downto
0
);
variable
vADDRESS
:
std_ulogic_vector
(
63
downto
0
);
variable
vADDRESS
:
std_ulogic_vector
(
63
downto
0
);
...
...
hdl/spec/testbench/top/main.sv
View file @
bfce7558
...
@@ -7,21 +7,17 @@
...
@@ -7,21 +7,17 @@
module
main
;
module
main
;
reg
clk_125m_pllref
=
0
;
reg
clk_20m_vcxo
=
0
;
reg
clk_20m_vcxo
=
0
;
reg
clk_ext
=
0
;
reg
rst_n
=
0
;
reg
rst_n
=
0
;
reg
adc0_dco
=
0
;
reg
adc0_dco
=
0
;
reg
adc0_fr
=
0
;
reg
adc0_fr
=
0
;
always
#
5
ns
adc0_dco
<=
~
adc0_dco
;
always
#
50
ns
clk_ext
<=
~
clk_ext
;
always
#
4
ns
clk_125m_pllref
<=
~
clk_125m_pllref
;
always
#
20
ns
clk_20m_vcxo
<=
~
clk_20m_vcxo
;
always
#
1.25
ns
adc0_dco
<=
~
adc0_dco
;
always
#
25
ns
clk_20m_vcxo
<=
~
clk_20m_vcxo
;
IGN4124PCIMaster
I_Gennum
()
;
IGN4124PCIMaster
I_Gennum
()
;
wire
ddr_cas_n
,
ddr_ck_p
,
ddr_ck_n
,
ddr_cke
;
wire
ddr_cas_n
,
ddr_ck_p
,
ddr_ck_n
,
ddr_cke
;
...
@@ -33,7 +29,7 @@ module main;
...
@@ -33,7 +29,7 @@ module main;
wire
ddr_zio
,
ddr_rzq
;
wire
ddr_zio
,
ddr_rzq
;
pulldown
(
ddr_rzq
)
;
pulldown
(
ddr_rzq
)
;
spec_top_fmc_adc_100Ms
spec_top_fmc_adc_100Ms
#(
#(
.
g_simulation
(
"TRUE"
)
,
.
g_simulation
(
"TRUE"
)
,
...
@@ -44,7 +40,7 @@ module main;
...
@@ -44,7 +40,7 @@ module main;
.
adc0_dco_n_i
(
~
adc0_dco
)
,
.
adc0_dco_n_i
(
~
adc0_dco
)
,
.
adc0_fr_p_i
(
adc0_fr
)
,
.
adc0_fr_p_i
(
adc0_fr
)
,
.
adc0_fr_n_i
(
~
adc0_fr
)
,
.
adc0_fr_n_i
(
~
adc0_fr
)
,
.
DDR3_CAS_N
(
ddr_cas_n
)
,
.
DDR3_CAS_N
(
ddr_cas_n
)
,
.
DDR3_CK_N
(
ddr_ck_n
)
,
.
DDR3_CK_N
(
ddr_ck_n
)
,
.
DDR3_CK_P
(
ddr_ck_p
)
,
.
DDR3_CK_P
(
ddr_ck_p
)
,
...
@@ -64,83 +60,118 @@ module main;
...
@@ -64,83 +60,118 @@ module main;
.
DDR3_BA
(
ddr_ba
)
,
.
DDR3_BA
(
ddr_ba
)
,
.
DDR3_ZIO
(
ddr_zio
)
,
.
DDR3_ZIO
(
ddr_zio
)
,
.
DDR3_RZQ
(
ddr_rzq
)
,
.
DDR3_RZQ
(
ddr_rzq
)
,
`GENNUM_WIRE_SPEC_PINS
(
I_Gennum
)
`GENNUM_WIRE_SPEC_PINS
(
I_Gennum
)
)
;
)
;
ddr3
#(
ddr3
#(
.
DEBUG
(
1
)
.
DEBUG
(
1
)
)
mem
(
)
mem
(
.
rst_n
(
ddr_reset_n
)
,
.
rst_n
(
ddr_reset_n
)
,
.
ck
(
ddr_ck_p
)
,
.
ck
(
ddr_ck_p
)
,
.
ck_n
(
ddr_ck_n
)
,
.
ck_n
(
ddr_ck_n
)
,
.
cke
(
ddr_cke
)
,
.
cke
(
ddr_cke
)
,
.
cs_n
(
1'b0
)
,
.
cs_n
(
1'b0
)
,
.
ras_n
(
ddr_ras_n
)
,
.
ras_n
(
ddr_ras_n
)
,
.
cas_n
(
ddr_cas_n
)
,
.
cas_n
(
ddr_cas_n
)
,
.
we_n
(
ddr_we_n
)
,
.
we_n
(
ddr_we_n
)
,
.
dm_tdqs
(
{
ddr_udm
,
ddr_ldm
}
)
,
.
dm_tdqs
(
{
ddr_udm
,
ddr_ldm
}
)
,
.
ba
(
ddr_ba
)
,
.
ba
(
ddr_ba
)
,
.
addr
(
ddr_a
)
,
.
addr
(
ddr_a
)
,
.
dq
(
ddr_dq
)
,
.
dq
(
ddr_dq
)
,
.
dqs
(
{
ddr_udqs_p
,
ddr_ldqs_p
}
)
,
.
dqs
(
{
ddr_udqs_p
,
ddr_ldqs_p
}
)
,
.
dqs_n
(
{
ddr_udqs_n
,
ddr_ldqs_n
}
)
,
.
dqs_n
(
{
ddr_udqs_n
,
ddr_ldqs_n
}
)
,
.
tdqs_n
()
,
.
tdqs_n
()
,
.
odt
(
ddr_odt
)
.
odt
(
ddr_odt
)
)
;
)
;
int
adc_div
=
0
;
int
adc_div
=
0
;
always
@
(
posedge
adc0_dco
)
always
@
(
posedge
adc0_dco
)
if
(
adc_div
==
3
)
if
(
adc_div
==
1
)
begin
begin
adc0_fr
<=
~
adc0_fr
;
adc0_fr
<=
1
;
adc_div
<=
0
;
adc_div
<=
0
;
end
end
else
begin
else
begin
adc0_fr
<=
0
;
adc_div
<=
adc_div
+
1
;
adc_div
<=
adc_div
+
1
;
end
end
initial
begin
initial
begin
CBusAccessor
acc
;
CBusAccessor
acc
;
uint64_t
rv
;
uint64_t
val
;
@
(
posedge
I_Gennum
.
ready
)
;
@
(
posedge
I_Gennum
.
ready
)
;
acc
=
I_Gennum
.
get_accessor
()
;
acc
=
I_Gennum
.
get_accessor
()
;
#
40u
s
;
acc
.
set_default_xfer_size
(
4
)
;
acc
.
set_default_xfer_size
(
4
)
;
acc
.
read
(
0
,
rv
)
;
$
display
(
"ID: %x"
,
rv
)
;
acc
.
write
(
'h100c
,
'h1000
)
;
// host addr
acc
.
write
(
'h1010
,
0
)
;
acc
.
write
(
'h1014
,
'h1000
)
;
// len
acc
.
write
(
'h1018
,
0
)
;
// next
acc
.
write
(
'h101c
,
0
)
;
acc
.
write
(
'h1008
,
'h0
)
;
acc
.
write
(
'h1020
,
'h0
)
;
// attrib: pcie -> host
acc
.
write
(
'h1000
,
'h1
)
;
// xfer start
end
endmodule
// main
@
(
posedge
DUT
.
sys_clk_pll_locked
)
;
#
5u
s
;
acc
.
read
(
0
,
val
)
;
$
display
(
"ID: %x"
,
val
)
;
acc
.
read
(
'h3304
,
val
)
;
// status
$
display
(
"STATUS: %x"
,
val
)
;
acc
.
write
(
'h3308
,
'h00000008
)
;
// trigger cfg: enable sw trigger
acc
.
write
(
'h3328
,
'h00000000
)
;
// #pre-samples
acc
.
write
(
'h332C
,
'h00000010
)
;
// #post-samples
acc
.
write
(
'h3314
,
'h00000001
)
;
// #nshots: single-shot acq
acc
.
read
(
'h3304
,
val
)
;
// status
$
display
(
"STATUS: %x"
,
val
)
;
acc
.
write
(
'h3300
,
'h00000001
)
;
// FSM start
#
1u
s
;
acc
.
write
(
'h3310
,
'hFFFFFFFF
)
;
// soft trigger
#
2u
s
;
acc
.
write
(
'h3314
,
'h00000003
)
;
// #nshots: 3x multi-shot acq
acc
.
write
(
'h3300
,
'h00000001
)
;
// FSM start
#
1u
s
;
acc
.
write
(
'h3310
,
'hFFFFFFFE
)
;
// soft trigger
#
1u
s
;
acc
.
write
(
'h3310
,
'hFFFFFFFD
)
;
// soft trigger
#
1u
s
;
acc
.
write
(
'h3310
,
'hFFFFFFFC
)
;
// soft trigger
#
2u
s
;
// DMA transfer
acc
.
write
(
'h100C
,
'h00001000
)
;
// host addr
acc
.
write
(
'h1010
,
'h00000000
)
;
acc
.
write
(
'h1014
,
'h00001000
)
;
// len
acc
.
write
(
'h1018
,
'h00000000
)
;
// next
acc
.
write
(
'h101C
,
'h00000000
)
;
acc
.
write
(
'h1008
,
'h00000000
)
;
acc
.
write
(
'h1020
,
'h00000000
)
;
// attrib: pcie -> host
acc
.
write
(
'h1000
,
'h00000001
)
;
// xfer start
end
endmodule
// main
hdl/spec/testbench/top/run.do
View file @
bfce7558
...
@@ -3,6 +3,6 @@ set StdArithNoWarnings 1
...
@@ -3,6 +3,6 @@ set StdArithNoWarnings 1
set NumericStdNoWarnings 1
set NumericStdNoWarnings 1
do wave.do
do wave.do
radix -hexadecimal
radix -hexadecimal
run
10
0us
run
5
0us
wave zoomfull
wave zoomfull
radix -hexadecimal
radix -hexadecimal
hdl/spec/testbench/top/wave.do
View file @
bfce7558
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