hdl: major rework of SVEC reference design
- Remove duplicate code and introduce a "for loop" generate for the two mezzanines. - Complete rework of timing constraints - Use SVEC BSP from WR for PLLs and reset - Replace xwb_clock_crossing with new xwb_clock_bridge - Redefine front panel LED functions, eliminate "heart-beat" LED - Fix bug where tm_time_valid was not re-synchronised
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