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FMC ADC 100M 14b 4cha - Gateware
Commit cacc6846 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: add extra synthesis options to hdlmake manifests

parent 57a89ed9
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Showing with 66 additions and 6 deletions
hdl/syn/spec_ref_design_wr/.gitignore
View file @ cacc6846
......@@ -2,3 +2,4 @@
!.gitignore
!Manifest.py
!spec_ref_fmc_adc_100Ms_wr.ucf
!syn_extra_steps.tcl
hdl/syn/spec_ref_design_wr/Manifest.py
View file @ cacc6846
......@@ -29,6 +29,9 @@ fetchto="../../ip_cores"
ctrls = ["bank3_64b_32b" ]
syn_post_project_cmd = "$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE)"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
hdl/syn/spec_ref_design_wr/syn_extra_steps.tcl 0 → 100644
View file @ cacc6846
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
xilinx::project save
xilinx::project close
hdl/syn/svec_ref_design_wr/.gitignore
View file @ cacc6846
......@@ -2,3 +2,4 @@
!.gitignore
!Manifest.py
!svec_ref_fmc_adc_100Ms_wr.ucf
!syn_extra_steps.tcl
hdl/syn/svec_ref_design_wr/Manifest.py
View file @ cacc6846
......@@ -29,6 +29,9 @@ fetchto="../../ip_cores"
ctrls = ["bank4_64b_32b", "bank5_64b_32b"]
syn_post_project_cmd = "$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE)"
syn_post_project_cmd = (
"$(TCL_INTERPRETER) " + \
fetchto + "/general-cores/tools/sdb_desc_gen.tcl " + \
syn_tool + " $(PROJECT_FILE);" \
"$(TCL_INTERPRETER) syn_extra_steps.tcl $(PROJECT_FILE)"
)
hdl/syn/svec_ref_design_wr/syn_extra_steps.tcl 0 → 100644
View file @ cacc6846
# get project file from 1st command-line argument
set project_file [lindex $argv 0]
if {![file exists $project_file]} {
report ERROR "Missing file $project_file, exiting."
exit -1
}
xilinx::project open $project_file
# Some of these are not respected by ISE when passed through hdlmake,
# so we add them all ourselves after creating the project
#
# Not respected by ISE when passed through hdlmake:
# 1. Pack I/O Registers/Latches into IOBs
# 2. Register Duplication Map
xilinx::project set "Enable Multi-Threading" "2" -process "Map"
xilinx::project set "Enable Multi-Threading" "4" -process "Place & Route"
#xilinx::project set "Pack I/O Registers into IOBs" "Yes"
#xilinx::project set "Pack I/O Registers/Latches into IOBs" "For Inputs and Outputs"
xilinx::project set "Register Balancing" "Yes"
xilinx::project set "Register Duplication Map" "On"
xilinx::project save
xilinx::project close
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