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FMC ADC 100M 14b 4cha - Gateware
Commit cb6feb94 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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hdl: moved timetag_core out of ip-cores since it is a local module, integral to the adc rtl

parent df13844f
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Showing with 17 additions and 19 deletions
doc/manual/timetag_core_regs.tex
View file @ cb6feb94
......@@ -20,11 +20,11 @@ Time trigger seconds register (upper)
@item @code{0x10} @tab
REG @tab
@code{time_trig_seconds_lower} @tab
Timetag seconds register (lower)
Time trigger seconds register (lower)
@item @code{0x14} @tab
REG @tab
@code{time_trig_coarse} @tab
Timetag coarse time register, system clock ticks (125MHz)
Time trigger coarse time register, system clock ticks (125MHz)
@item @code{0x18} @tab
REG @tab
@code{trig_tag_seconds_upper} @tab
......@@ -114,7 +114,7 @@ Timetag coarse time
@tab @code{0} @tab
Time trigger seconds
@end multitable
@regsection @code{time_trig_seconds_lower} - Timetag seconds register (lower)
@regsection @code{time_trig_seconds_lower} - Time trigger seconds register (lower)
32 lower bits of seconds used for time trigger.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......@@ -124,7 +124,7 @@ Time trigger seconds
@tab @code{0} @tab
Time trigger seconds
@end multitable
@regsection @code{time_trig_coarse} - Timetag coarse time register, system clock ticks (125MHz)
@regsection @code{time_trig_coarse} - Time trigger coarse time register, system clock ticks (125MHz)
Coarse time counter clocked by 125MHz system clock.@*Counts from 0 to 125000000.
@multitable @columnfractions .10 .10 .15 .10 .55
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
......
hdl/adc/rtl/Manifest.py
View file @ cb6feb94
......@@ -8,3 +8,5 @@ files = [
"fmc_adc_eic.vhd",
"offset_gain_s.vhd",
"var_sat_s.vhd"]
modules = { "local" : ["timetag_core/rtl"] }
hdl/ip_cores/timetag_core/rtl/timetag_core_regs.vhd → hdl/adc/rtl/timetag_core/rtl/timetag_core_regs.vhd
View file @ cb6feb94
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/timetag_core_regs.vhd
-- Author : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created : Thu Jun 16 17:23:36 2016
-- Created : Thu Jun 23 11:13:24 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......
hdl/ip_cores/timetag_core/rtl/timetag_core_regs_wbgen2_pkg.vhd → hdl/adc/rtl/timetag_core/rtl/timetag_core_regs_wbgen2_pkg.vhd
View file @ cb6feb94
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/timetag_core_regs_wbgen2_pkg.vhd
-- Author : auto-generated by wbgen2 from timetag_core_regs.wb
-- Created : Thu Jun 16 17:23:36 2016
-- Created : Thu Jun 23 11:13:24 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......
hdl/ip_cores/timetag_core/wb_gen/Makefile → hdl/adc/rtl/timetag_core/wb_gen/Makefile
View file @ cb6feb94
WBGEN2=$(shell which wbgen2)
RTL=../rtl/
TEX=../../../../doc/manual/
TEX=../../../../../doc/manual/
timetag_core_regs:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
......
hdl/ip_cores/timetag_core/wb_gen/timetag_core_regs.h → hdl/adc/rtl/timetag_core/wb_gen/timetag_core_regs.h
View file @ cb6feb94
......@@ -3,7 +3,7 @@
* File : timetag_core_regs.h
* Author : auto-generated by wbgen2 from timetag_core_regs.wb
* Created : Tue Jun 21 11:42:34 2016
* Created : Thu Jun 23 11:13:24 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE timetag_core_regs.wb
......
hdl/spec/syn/Manifest.py
View file @ cb6feb94
......@@ -13,8 +13,7 @@ files = [
"../../ip_cores/adc_serdes.vhd"]
modules = { "local" : ["../rtl",
"../../adc/rtl",
"../../ip_cores/timetag_core/rtl"],
"../../adc/rtl"],
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git@@c26ee857158e4a65fd9d2add8b63fcb6fb4691ea",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git@@503171933f184ae878836f28e67a78a7c81b4325",
"git://ohwr.org/hdl-core-lib/gn4124-core.git@@e0dcb3f9a3e6804f64c544743bdf46b5fcbbefab"]}
......
hdl/spec/testbench/top/Manifest.py
View file @ cb6feb94
......@@ -11,10 +11,9 @@ files = [
"ddr3/ddr3.v",
"../../../ip_cores/adc_serdes.vhd"]
modules = { "local" : [ "../../rtl",
"gn4124_bfm",
modules = { "local" : [ "gn4124_bfm",
"../../rtl",
"../../../adc/rtl",
"../../../ip_cores/timetag_core/rtl",
"../../../ip_cores/general-cores",
"../../../ip_cores/ddr3-sp6-core",
"../../../ip_cores/gn4124-core" ]};
......
hdl/svec/sim/testbench/Manifest.py
View file @ cb6feb94
......@@ -8,10 +8,9 @@ include_dirs=["../vme64x_bfm", "../2048Mb_ddr3", "../../../ip_cores/general-core
files = [ "main.sv",
"../../../ip_cores/adc_serdes.vhd"]
modules = { "local" : [ "../../rtl",
"../2048Mb_ddr3",
"../../../adc/rtl",
"../../../ip_cores/timetag_core/rtl"],
modules = { "local" : [ "../2048Mb_ddr3",
"../../rtl",
"../../../adc/rtl"],
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git::sdb_extension",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git::svec_bank4_64b_32b_bank5_64b_32b",
"git://ohwr.org/hdl-core-lib/vme64x-core.git::master"]}
......
hdl/svec/syn/Manifest.py
View file @ cb6feb94
......@@ -13,8 +13,7 @@ files = [
"../../ip_cores/adc_serdes.vhd"]
modules = { "local" : ["../rtl",
"../../adc/rtl",
"../../ip_cores/timetag_core/rtl"],
"../../adc/rtl"],
"git" : ["git://ohwr.org/hdl-core-lib/general-cores.git@@c26ee857158e4a65fd9d2add8b63fcb6fb4691ea",
"git://ohwr.org/hdl-core-lib/ddr3-sp6-core.git@@503171933f184ae878836f28e67a78a7c81b4325",
"git://ohwr.org/hdl-core-lib/vme64x-core.git@@b2fc3ce76485404f831d15f7ce31fdde08e234d5"]}
......
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