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FMC ADC 100M 14b 4cha - Gateware
Commit ce4ef303 authored by Dimitris Lampridis's avatar Dimitris Lampridis
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[hdl] rename ALT triggers to AUX, always enable SW and AUX triggers

parent 449a1292
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doc/manual/fmc_adc_100Ms_csr.html
View file @ ce4ef303
......@@ -133,9 +133,9 @@
<tr class="tr_even">
<td class="td_code">0x02c</td>
<td>REG</td>
<td><A href="#undersample">undersample</a></td>
<td class="td_code">undersample</td>
<td class="td_code">undersample</td>
<td><A href="#downsample">downsample</a></td>
<td class="td_code">downsample</td>
<td class="td_code">downsample</td>
</tr>
<tr class="tr_odd">
<td class="td_code">0x030</td>
......@@ -711,10 +711,10 @@ Trigger enable
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">fwd_ch4</td>
<td class="td_field" colspan="1">fwd_ch3</td>
<td class="td_field" colspan="1">fwd_ch2</td>
<td class="td_field" colspan="1">fwd_ch1</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
......@@ -734,7 +734,7 @@ Trigger enable
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">fwd_ext</td>
<td class="td_unused" colspan="1">-</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
......@@ -769,7 +769,7 @@ Trigger enable
<tr>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_field" colspan="1">alt_time</td>
<td class="td_field" colspan="1">aux_time</td>
<td class="td_field" colspan="1">time</td>
<td class="td_unused" colspan="1">-</td>
<td class="td_unused" colspan="1">-</td>
......@@ -785,15 +785,15 @@ ext
<li><b>
sw
</b>[<i>rw</i>]: Software trigger
<br>0: disable<br>1: enable
<br>Always enabled
<li><b>
time
</b>[<i>rw</i>]: Timetag trigger
<br>0: disable<br>1: enable
<li><b>
alt_time
</b>[<i>rw</i>]: Alternate timetag trigger
<br>0: disable<br>1: enable
aux_time
</b>[<i>rw</i>]: Auxiliary timetag trigger
<br>Always enabled
<li><b>
ch1
</b>[<i>rw</i>]: Channel 1 internal threshold trigger
......@@ -810,26 +810,6 @@ ch3
ch4
</b>[<i>rw</i>]: Channel 4 internal threshold trigger
<br>0: disable<br>1: enable
<li><b>
fwd_ext
</b>[<i>rw</i>]: Forward external trigger to trigger out
<br>0: disable<br>1: enable
<li><b>
fwd_ch1
</b>[<i>rw</i>]: Forward channel 1 internal threshold trigger to trigger out
<br>0: disable<br>1: enable
<li><b>
fwd_ch2
</b>[<i>rw</i>]: Forward channel 2 internal threshold trigger to trigger out
<br>0: disable<br>1: enable
<li><b>
fwd_ch3
</b>[<i>rw</i>]: Forward channel 3 internal threshold trigger to trigger out
<br>0: disable<br>1: enable
<li><b>
fwd_ch4
</b>[<i>rw</i>]: Forward channel 4 internal threshold trigger to trigger out
<br>0: disable<br>1: enable
</ul>
<a name="trig_pol"></a>
<h3><a name="sect_3_5">2.5. trig_pol</a></h3>
......@@ -1371,16 +1351,16 @@ Sampling clock frequency
fs_freq
</b>[<i>ro</i>]: Sampling clock frequency
</ul>
<a name="undersample"></a>
<h3><a name="sect_3_12">2.12. undersample</a></h3>
<a name="downsample"></a>
<h3><a name="sect_3_12">2.12. downsample</a></h3>
<table cellpadding=0 cellspacing=0 border=0>
<tr><td><b>HW prefix:</b></td><td class="td_code">undersample</td></tr>
<tr><td><b>HW prefix:</b></td><td class="td_code">downsample</td></tr>
<tr><td><b>HW address:</b></td><td class="td_code">0x2c</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">undersample</td></tr>
<tr><td><b>C prefix:</b></td><td class="td_code">downsample</td></tr>
<tr><td><b>C block offset:</b></td><td class="td_code">0x2c</td></tr>
</table>
<p>
Undersampling ratio
Downsampling ratio
</p>
<table cellpadding=0 cellspacing=0 border=0>
<tr>
......@@ -1394,7 +1374,7 @@ Undersampling ratio
<td class="td_bit" colspan="1">24</td>
</tr>
<tr>
<td class="td_field" colspan="8">undersample[31:24]</td>
<td class="td_field" colspan="8">downsample[31:24]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">23</td>
......@@ -1407,7 +1387,7 @@ Undersampling ratio
<td class="td_bit" colspan="1">16</td>
</tr>
<tr>
<td class="td_field" colspan="8">undersample[23:16]</td>
<td class="td_field" colspan="8">downsample[23:16]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">15</td>
......@@ -1420,7 +1400,7 @@ Undersampling ratio
<td class="td_bit" colspan="1">8</td>
</tr>
<tr>
<td class="td_field" colspan="8">undersample[15:8]</td>
<td class="td_field" colspan="8">downsample[15:8]</td>
</tr>
<tr>
<td class="td_bit" colspan="1">7</td>
......@@ -1433,13 +1413,13 @@ Undersampling ratio
<td class="td_bit" colspan="1">0</td>
</tr>
<tr>
<td class="td_field" colspan="8">undersample[7:0]</td>
<td class="td_field" colspan="8">downsample[7:0]</td>
</tr>
</table>
<ul>
<li><b>
undersample
</b>[<i>rw</i>]: Undersampling ratio
downsample
</b>[<i>rw</i>]: Downsampling ratio
</ul>
<a name="pre_samples"></a>
<h3><a name="sect_3_13">2.13. pre_samples</a></h3>
......@@ -1827,7 +1807,7 @@ Channel 1 status register
<li><b>
val
</b>[<i>ro</i>]: Channel 1 current ADC value
<br>Current ADC raw value. The format is binary two\'s complement.
<br>Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is<br>configured for "offset binary". The FMC-ADC driver when loaded, will change this to<br>binary two\'s complement.
</ul>
<a name="ch1_calib"></a>
<h3><a name="sect_3_18">2.18. ch1_calib</a></h3>
......@@ -2311,7 +2291,7 @@ Channel 2 status register
<li><b>
val
</b>[<i>ro</i>]: Channel 2 current ACD value
<br>Current ADC raw value. The format is binary two\'s complement.
<br>Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is<br>configured for "offset binary". The FMC-ADC driver when loaded, will change this to<br>binary two\'s complement.
</ul>
<a name="ch2_calib"></a>
<h3><a name="sect_3_24">2.24. ch2_calib</a></h3>
......@@ -2795,7 +2775,7 @@ Channel 3 status register
<li><b>
val
</b>[<i>ro</i>]: Channel 3 current ADC value
<br>Current ADC raw value. The format is binary two\'s complement.
<br>Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is<br>configured for "offset binary". The FMC-ADC driver when loaded, will change this to<br>binary two\'s complement.
</ul>
<a name="ch3_calib"></a>
<h3><a name="sect_3_30">2.30. ch3_calib</a></h3>
......@@ -3279,7 +3259,7 @@ Channel 4 status register
<li><b>
val
</b>[<i>ro</i>]: Channel 4 current ADC value
<br>Current ADC raw value. The format is binary two\'s complement.
<br>Current ADC raw value. The format depends on ADC configuration; Upon reset, the ADC is<br>configured for "offset binary". The FMC-ADC driver when loaded, will change this to<br>binary two\'s complement.
</ul>
<a name="ch4_calib"></a>
<h3><a name="sect_3_36">2.36. ch4_calib</a></h3>
......
doc/manual/fmc_adc_aux_trigin.html 0 → 100644
View file @ ce4ef303
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doc/manual/fmc_adc_aux_trigout.html 0 → 100644
View file @ ce4ef303
This diff is collapsed.
hdl/rtl/Manifest.py
View file @ ce4ef303
......@@ -4,8 +4,8 @@ files = [
"fmc_adc_100Ms_core.vhd",
"fmc_adc_100Ms_core_pkg.vhd",
"fmc_adc_100Ms_csr.vhd",
"fmc_adc_alt_trigin.vhd",
"fmc_adc_alt_trigout.vhd",
"fmc_adc_aux_trigin.vhd",
"fmc_adc_aux_trigout.vhd",
"fmc_adc_eic.vhd",
"offset_gain_s.vhd",
"timetag_core_regs.vhd",
......
hdl/rtl/fmc_adc_100Ms_core.vhd
View file @ ce4ef303
......@@ -82,7 +82,7 @@ entity fmc_adc_100Ms_core is
-- Trigger time-tag inputs
trigger_tag_i : in t_timetag;
time_trig_i : in std_logic;
alt_time_trig_i : in std_logic;
aux_time_trig_i : in std_logic;
-- WR status (for trigout).
wr_tm_link_up_i : in std_logic;
......@@ -206,16 +206,14 @@ architecture rtl of fmc_adc_100Ms_core is
signal int_trig_thres_in : t_fmc_adc_vec16_array(1 to 4);
signal int_trig_thres_hyst_in : t_fmc_adc_vec16_array(1 to 4);
signal sw_trig : std_logic;
signal sw_trig_en : std_logic;
signal sw_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
signal sw_trig_in : std_logic := '0';
signal sw_trig_sync_ack : std_logic := '0';
signal time_trig : std_logic;
signal time_trig_en : std_logic;
signal time_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
signal alt_time_trig : std_logic;
signal alt_time_trig_en : std_logic;
signal alt_time_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
signal aux_time_trig : std_logic;
signal aux_time_trig_fixed_delay : std_logic_vector(g_TRIG_DELAY_SW+2 downto 0);
signal trig : std_logic;
signal trig_align : std_logic_vector(8 downto 0);
signal trig_storage : std_logic_vector(31 downto 0);
......@@ -490,6 +488,8 @@ begin
csr_regin.trig_stat_ch2 <= trig_storage(9);
csr_regin.trig_stat_ch3 <= trig_storage(10);
csr_regin.trig_stat_ch4 <= trig_storage(11);
csr_regin.trig_en_sw <= '1';
csr_regin.trig_en_aux_time <= '1';
csr_regin.shots_remain <= remaining_shots;
csr_regin.trig_pos <= trig_addr;
csr_regin.fs_freq <= fs_freq;
......@@ -540,8 +540,6 @@ begin
sat_val_in <= csr_regout.ch4_sat_val & csr_regout.ch3_sat_val &
csr_regout.ch2_sat_val & csr_regout.ch1_sat_val;
-- NOTE: trigger forwards are read from CSR in the b_trigout block later
-- Delays for user-controlled GPIO outputs to help with timing
p_delay_gpio_ssr : process (sys_clk_i) is
begin
......@@ -569,13 +567,6 @@ begin
data_i => csr_regout.trig_pol_ext,
synced_o => ext_trig_pol);
cmp_sw_trig_en_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => csr_regout.trig_en_sw,
synced_o => sw_trig_en);
cmp_time_trig_en_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
......@@ -583,13 +574,6 @@ begin
data_i => csr_regout.trig_en_time,
synced_o => time_trig_en);
cmp_alt_time_trig_en_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => csr_regout.trig_en_alt_time,
synced_o => alt_time_trig_en);
cmp_downsample_sync : gc_sync_word_wr
generic map (
g_AUTO_WR => TRUE,
......@@ -828,14 +812,14 @@ begin
npulse_o => open,
ppulse_o => time_trig);
cmp_alt_time_trig_sync : gc_sync_ffs
cmp_aux_time_trig_sync : gc_sync_ffs
port map (
clk_i => fs_clk,
rst_n_i => '1',
data_i => alt_time_trig_i,
data_i => aux_time_trig_i,
synced_o => open,
npulse_o => open,
ppulse_o => alt_time_trig);
ppulse_o => aux_time_trig);
-- Internal hardware trigger
g_int_trig : for I in 1 to 4 generate
......@@ -934,19 +918,19 @@ begin
sw_trig_fixed_delay <= (others => '0');
ext_trig_fixed_delay <= (others => '0');
time_trig_fixed_delay <= (others => '0');
alt_time_trig_fixed_delay <= (others => '0');
aux_time_trig_fixed_delay <= (others => '0');
else
sw_trig_fixed_delay <= sw_trig_fixed_delay(sw_trig_fixed_delay'high -1 downto 0) & sw_trig;
ext_trig_fixed_delay <= ext_trig_fixed_delay(ext_trig_fixed_delay'high -1 downto 0) & ext_trig_d;
time_trig_fixed_delay <= time_trig_fixed_delay(time_trig_fixed_delay'high -1 downto 0) & time_trig;
alt_time_trig_fixed_delay <= alt_time_trig_fixed_delay(alt_time_trig_fixed_delay'high -1 downto 0) & alt_time_trig;
aux_time_trig_fixed_delay <= aux_time_trig_fixed_delay(aux_time_trig_fixed_delay'high -1 downto 0) & aux_time_trig;
end if;
end if;
end process p_trig_shift;
trig_src_vector <= (sw_trig_fixed_delay(sw_trig_fixed_delay'high) and sw_trig_en) &
trig_src_vector <= sw_trig_fixed_delay(sw_trig_fixed_delay'high) &
(ext_trig_fixed_delay(ext_trig_fixed_delay'high) and ext_trig_en) &
(alt_time_trig_fixed_delay(alt_time_trig_fixed_delay'high) and alt_time_trig_en) &
aux_time_trig_fixed_delay(aux_time_trig_fixed_delay'high) &
(time_trig_fixed_delay(time_trig_fixed_delay'high) and time_trig_en) &
(int_trig_d(4) and int_trig_en(4)) &
(int_trig_d(3) and int_trig_en(3)) &
......@@ -1020,7 +1004,7 @@ begin
-- Data to FIFO
-- 72 : sw trigger
-- 71 : ext trigger
-- 70 : alt time trigger
-- 70 : aux time trigger
-- 69 : time trigger
-- 68 : int4 trigger
-- 67 : int3 trigger
......@@ -1628,7 +1612,6 @@ begin
b_trigout : block
subtype t_trigout_channels is std_logic_vector(4 downto 0);
signal trigout_triggers : t_trigout_channels;
signal trigout_en : t_trigout_channels;
signal trigout_trig : std_logic;
......@@ -1647,7 +1630,7 @@ begin
signal trigout_fifo_rd : std_logic;
begin
cmp_alt_trigout : entity work.alt_trigout
cmp_aux_trigout : entity work.aux_trigout
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
......@@ -1674,13 +1657,7 @@ begin
trigout_triggers(3) <= trig_storage(11);
trigout_triggers(4) <= trig_storage(0);
trigout_en(0) <= csr_regout.trig_en_fwd_ch1;
trigout_en(1) <= csr_regout.trig_en_fwd_ch2;
trigout_en(2) <= csr_regout.trig_en_fwd_ch3;
trigout_en(3) <= csr_regout.trig_en_fwd_ch4;
trigout_en(4) <= csr_regout.trig_en_fwd_ext;
trigout_trig <= f_reduce_or (trigout_triggers and trigout_en);
trigout_trig <= f_reduce_or (trigout_triggers);
-- Acquisition trigger delayed pulse
p_acq_end : process (sys_clk_i)
......
hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
View file @ ce4ef303
......@@ -91,7 +91,7 @@ package fmc_adc_100Ms_core_pkg is
-- Trigger time-tag input
trigger_tag_i : in t_timetag;
time_trig_i : in std_logic;
alt_time_trig_i : in std_logic;
aux_time_trig_i : in std_logic;
-- WR status (for trigout).
wr_tm_link_up_i : in std_logic;
......
hdl/rtl/fmc_adc_100Ms_csr.cheby
View file @ ce4ef303
......@@ -189,8 +189,9 @@ memory-map:
range: 1
description: Software trigger
comment: |
0: disable
1: enable
Always enabled
x-hdl:
type: wire
- field:
name: time
range: 4
......@@ -199,12 +200,13 @@ memory-map:
0: disable
1: enable
- field:
name: alt_time
name: aux_time
range: 5
description: Alternate timetag trigger
description: Auxiliary timetag trigger
comment: |
0: disable
1: enable
Always enabled
x-hdl:
type: wire
- field:
name: ch1
range: 8
......@@ -233,41 +235,6 @@ memory-map:
comment: |
0: disable
1: enable
- field:
name: fwd_ext
range: 16
description: Forward external trigger to trigger out
comment: |
0: disable
1: enable
- field:
name: fwd_ch1
range: 24
description: Forward channel 1 internal threshold trigger to trigger out
comment: |
0: disable
1: enable
- field:
name: fwd_ch2
range: 25
description: Forward channel 2 internal threshold trigger to trigger out
comment: |
0: disable
1: enable
- field:
name: fwd_ch3
range: 26
description: Forward channel 3 internal threshold trigger to trigger out
comment: |
0: disable
1: enable
- field:
name: fwd_ch4
range: 27
description: Forward channel 4 internal threshold trigger to trigger out
comment: |
0: disable
1: enable
- reg:
name: trig_pol
address: 0x00000010
......
hdl/rtl/fmc_adc_100Ms_csr.vhd
View file @ ce4ef303
......@@ -20,16 +20,11 @@ package fmc_adc_100ms_csr_pkg is
trig_en_ext : std_logic;
trig_en_sw : std_logic;
trig_en_time : std_logic;
trig_en_alt_time : std_logic;
trig_en_aux_time : std_logic;
trig_en_ch1 : std_logic;
trig_en_ch2 : std_logic;
trig_en_ch3 : std_logic;
trig_en_ch4 : std_logic;
trig_en_fwd_ext : std_logic;
trig_en_fwd_ch1 : std_logic;
trig_en_fwd_ch2 : std_logic;
trig_en_fwd_ch3 : std_logic;
trig_en_fwd_ch4 : std_logic;
trig_pol_ext : std_logic;
trig_pol_ch1 : std_logic;
trig_pol_ch2 : std_logic;
......@@ -89,6 +84,8 @@ package fmc_adc_100ms_csr_pkg is
trig_stat_ch2 : std_logic;
trig_stat_ch3 : std_logic;
trig_stat_ch4 : std_logic;
trig_en_sw : std_logic;
trig_en_aux_time : std_logic;
shots_remain : std_logic_vector(15 downto 0);
multi_depth : std_logic_vector(31 downto 0);
trig_pos : std_logic_vector(31 downto 0);
......@@ -136,18 +133,11 @@ architecture syn of fmc_adc_100ms_csr is
signal ctl_trig_led_reg : std_logic;
signal ctl_acq_led_reg : std_logic;
signal trig_en_ext_reg : std_logic;
signal trig_en_sw_reg : std_logic;
signal trig_en_time_reg : std_logic;
signal trig_en_alt_time_reg : std_logic;
signal trig_en_ch1_reg : std_logic;
signal trig_en_ch2_reg : std_logic;
signal trig_en_ch3_reg : std_logic;
signal trig_en_ch4_reg : std_logic;
signal trig_en_fwd_ext_reg : std_logic;
signal trig_en_fwd_ch1_reg : std_logic;
signal trig_en_fwd_ch2_reg : std_logic;
signal trig_en_fwd_ch3_reg : std_logic;
signal trig_en_fwd_ch4_reg : std_logic;
signal trig_pol_ext_reg : std_logic;
signal trig_pol_ch1_reg : std_logic;
signal trig_pol_ch2_reg : std_logic;
......@@ -228,18 +218,11 @@ begin
fmc_adc_100ms_csr_o.ctl_trig_led <= ctl_trig_led_reg;
fmc_adc_100ms_csr_o.ctl_acq_led <= ctl_acq_led_reg;
fmc_adc_100ms_csr_o.trig_en_ext <= trig_en_ext_reg;
fmc_adc_100ms_csr_o.trig_en_sw <= trig_en_sw_reg;
fmc_adc_100ms_csr_o.trig_en_time <= trig_en_time_reg;
fmc_adc_100ms_csr_o.trig_en_alt_time <= trig_en_alt_time_reg;
fmc_adc_100ms_csr_o.trig_en_ch1 <= trig_en_ch1_reg;
fmc_adc_100ms_csr_o.trig_en_ch2 <= trig_en_ch2_reg;
fmc_adc_100ms_csr_o.trig_en_ch3 <= trig_en_ch3_reg;
fmc_adc_100ms_csr_o.trig_en_ch4 <= trig_en_ch4_reg;
fmc_adc_100ms_csr_o.trig_en_fwd_ext <= trig_en_fwd_ext_reg;
fmc_adc_100ms_csr_o.trig_en_fwd_ch1 <= trig_en_fwd_ch1_reg;
fmc_adc_100ms_csr_o.trig_en_fwd_ch2 <= trig_en_fwd_ch2_reg;
fmc_adc_100ms_csr_o.trig_en_fwd_ch3 <= trig_en_fwd_ch3_reg;
fmc_adc_100ms_csr_o.trig_en_fwd_ch4 <= trig_en_fwd_ch4_reg;
fmc_adc_100ms_csr_o.trig_pol_ext <= trig_pol_ext_reg;
fmc_adc_100ms_csr_o.trig_pol_ch1 <= trig_pol_ch1_reg;
fmc_adc_100ms_csr_o.trig_pol_ch2 <= trig_pol_ch2_reg;
......@@ -291,18 +274,11 @@ begin
ctl_trig_led_reg <= '0';
ctl_acq_led_reg <= '0';
trig_en_ext_reg <= '0';
trig_en_sw_reg <= '0';
trig_en_time_reg <= '0';
trig_en_alt_time_reg <= '0';
trig_en_ch1_reg <= '0';
trig_en_ch2_reg <= '0';
trig_en_ch3_reg <= '0';
trig_en_ch4_reg <= '0';
trig_en_fwd_ext_reg <= '0';
trig_en_fwd_ch1_reg <= '0';
trig_en_fwd_ch2_reg <= '0';
trig_en_fwd_ch3_reg <= '0';
trig_en_fwd_ch4_reg <= '0';
trig_pol_ext_reg <= '0';
trig_pol_ch1_reg <= '0';
trig_pol_ch2_reg <= '0';
......@@ -369,18 +345,13 @@ begin
-- Register trig_en
if wr_int = '1' then
trig_en_ext_reg <= wb_i.dat(0);
trig_en_sw_reg <= wb_i.dat(1);
fmc_adc_100ms_csr_o.trig_en_sw <= wb_i.dat(1);
trig_en_time_reg <= wb_i.dat(4);
trig_en_alt_time_reg <= wb_i.dat(5);
fmc_adc_100ms_csr_o.trig_en_aux_time <= wb_i.dat(5);
trig_en_ch1_reg <= wb_i.dat(8);
trig_en_ch2_reg <= wb_i.dat(9);
trig_en_ch3_reg <= wb_i.dat(10);
trig_en_ch4_reg <= wb_i.dat(11);
trig_en_fwd_ext_reg <= wb_i.dat(16);
trig_en_fwd_ch1_reg <= wb_i.dat(24);
trig_en_fwd_ch2_reg <= wb_i.dat(25);
trig_en_fwd_ch3_reg <= wb_i.dat(26);
trig_en_fwd_ch4_reg <= wb_i.dat(27);
end if;
wr_ack_int <= wr_int;
when "0000100" =>
......@@ -621,18 +592,13 @@ begin
when "0000011" =>
-- trig_en
reg_rdat_int(0) <= trig_en_ext_reg;
reg_rdat_int(1) <= trig_en_sw_reg;
reg_rdat_int(1) <= fmc_adc_100ms_csr_i.trig_en_sw;
reg_rdat_int(4) <= trig_en_time_reg;
reg_rdat_int(5) <= trig_en_alt_time_reg;
reg_rdat_int(5) <= fmc_adc_100ms_csr_i.trig_en_aux_time;
reg_rdat_int(8) <= trig_en_ch1_reg;
reg_rdat_int(9) <= trig_en_ch2_reg;
reg_rdat_int(10) <= trig_en_ch3_reg;
reg_rdat_int(11) <= trig_en_ch4_reg;
reg_rdat_int(16) <= trig_en_fwd_ext_reg;
reg_rdat_int(24) <= trig_en_fwd_ch1_reg;
reg_rdat_int(25) <= trig_en_fwd_ch2_reg;
reg_rdat_int(26) <= trig_en_fwd_ch3_reg;
reg_rdat_int(27) <= trig_en_fwd_ch4_reg;
rd_ack1_int <= rd_int;
when "0000100" =>
-- trig_pol
......
hdl/rtl/fmc_adc_alt_trigin.cheby → hdl/rtl/fmc_adc_aux_trigin.cheby
View file @ ce4ef303
memory-map:
bus: wb-32-be
name: alt_trigin
description: FMC ADC alt trigger out registers
name: aux_trigin
description: FMC ADC aux trigger out registers
x-hdl:
busgroup: True
children:
......
hdl/rtl/fmc_adc_alt_trigin.vhd → hdl/rtl/fmc_adc_aux_trigin.vhd
View file @ ce4ef303
-- Do not edit; this file was generated by Cheby using these options:
-- -i fmc_adc_alt_trigin.cheby --gen-hdl=fmc_adc_alt_trigin.vhd
-- -i fmc_adc_aux_trigin.cheby --gen-hdl=fmc_adc_aux_trigin.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity alt_trigin is
entity aux_trigin is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
......@@ -24,9 +24,9 @@ entity alt_trigin is
-- Time (cycles) to trigger
cycles_o : out std_logic_vector(31 downto 0)
);
end alt_trigin;
end aux_trigin;
architecture syn of alt_trigin is
architecture syn of aux_trigin is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
......
hdl/rtl/fmc_adc_alt_trigout.cheby → hdl/rtl/fmc_adc_aux_trigout.cheby
View file @ ce4ef303
memory-map:
bus: wb-32-be
name: alt_trigout
description: FMC ADC alt trigger out registers
name: aux_trigout
description: FMC ADC aux trigger out registers
x-hdl:
busgroup: True
reg_prefix: False
......
hdl/rtl/fmc_adc_alt_trigout.vhd → hdl/rtl/fmc_adc_aux_trigout.vhd
View file @ ce4ef303
-- Do not edit; this file was generated by Cheby using these options:
-- -i fmc_adc_alt_trigout.cheby --gen-hdl=fmc_adc_alt_trigout.vhd
-- -i fmc_adc_aux_trigout.cheby --gen-hdl=fmc_adc_aux_trigout.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity alt_trigout is
entity aux_trigout is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
......@@ -47,9 +47,9 @@ entity alt_trigout is
cycles_i : in std_logic_vector(27 downto 0);
ts_cycles_rd_o : out std_logic
);
end alt_trigout;
end aux_trigout;
architecture syn of alt_trigout is
architecture syn of aux_trigout is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
......
hdl/rtl/fmc_adc_mezzanine.vhd
View file @ ce4ef303
......@@ -75,7 +75,7 @@ entity fmc_adc_mezzanine is
eic_irq_o : out std_logic;
acq_cfg_ok_o : out std_logic;
-- Alternate trigger input wishbone interface
-- Auxiliary trigger input wishbone interface
wb_trigin_slave_i : in t_wishbone_slave_in;
wb_trigin_slave_o : out t_wishbone_slave_out;
......@@ -272,14 +272,14 @@ architecture rtl of fmc_adc_mezzanine is
signal trigger_tag : t_timetag;
signal time_trigger : std_logic;
-- Alternative time trigger
signal alt_trigin_enable_in : std_logic;
signal alt_trigin_enable_out : std_logic;
signal alt_trigin_enable_wr : std_logic;
signal alt_trigin_tag : t_timetag;
signal alt_time_trigger : std_logic;
signal alt_trigin_secs : std_logic_vector(63 downto 0);
signal alt_trigin_cycs : std_logic_vector(31 downto 0);
-- Aux time trigger
signal aux_trigin_enable_in : std_logic;
signal aux_trigin_enable_out : std_logic;
signal aux_trigin_enable_wr : std_logic;
signal aux_trigin_tag : t_timetag;
signal aux_time_trigger : std_logic;
signal aux_trigin_secs : std_logic_vector(63 downto 0);
signal aux_trigin_cycs : std_logic_vector(31 downto 0);
begin
------------------------------------------------------------------------------
......@@ -477,7 +477,7 @@ begin
trigger_tag_i => trigger_tag,
time_trig_i => time_trigger,
alt_time_trig_i => alt_time_trigger,
aux_time_trig_i => aux_time_trigger,
wr_tm_link_up_i => wr_tm_link_up_i,
wr_tm_time_valid_i => wr_tm_time_valid_i,
......@@ -615,31 +615,31 @@ begin
trig_tag_o => trigger_tag,
time_trig_o => time_trigger,
alt_trigin_enable_o => alt_trigin_enable_in,
alt_trigin_enable_i => alt_trigin_enable_out,
alt_trigin_enable_wr_i => alt_trigin_enable_wr,
alt_trigin_tag_i => alt_trigin_tag,
alt_trigin_o => alt_time_trigger,
aux_trigin_enable_o => aux_trigin_enable_in,
aux_trigin_enable_i => aux_trigin_enable_out,
aux_trigin_enable_wr_i => aux_trigin_enable_wr,
aux_trigin_tag_i => aux_trigin_tag,
aux_trigin_o => aux_time_trigger,
wb_i => cnx_slave_in(c_WB_SLAVE_TIMETAG),
wb_o => cnx_slave_out(c_WB_SLAVE_TIMETAG));
cmp_alt_trigin : entity work.alt_trigin
cmp_aux_trigin : entity work.aux_trigin
port map (
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
wb_i => wb_trigin_slave_i,
wb_o => wb_trigin_slave_o,
ctrl_enable_i => alt_trigin_enable_in,
ctrl_enable_o => alt_trigin_enable_out,
ctrl_wr_o => alt_trigin_enable_wr,
ctrl_enable_i => aux_trigin_enable_in,
ctrl_enable_o => aux_trigin_enable_out,
ctrl_wr_o => aux_trigin_enable_wr,
seconds_o => alt_trigin_secs,
cycles_o => alt_trigin_cycs
seconds_o => aux_trigin_secs,
cycles_o => aux_trigin_cycs
);
alt_trigin_tag <= (seconds => alt_trigin_secs(39 downto 0),
coarse => alt_trigin_cycs(27 downto 0));
aux_trigin_tag <= (seconds => aux_trigin_secs(39 downto 0),
coarse => aux_trigin_cycs(27 downto 0));
end rtl;
hdl/rtl/fmc_adc_mezzanine_pkg.vhd
View file @ ce4ef303
......@@ -80,7 +80,7 @@ package fmc_adc_mezzanine_pkg is
eic_irq_o : out std_logic;
acq_cfg_ok_o : out std_logic;
-- Alternate trigger input wishbone interface
-- Auxiliary trigger input wishbone interface
wb_trigin_slave_i : in t_wishbone_slave_in := c_DUMMY_WB_SLAVE_IN;
wb_trigin_slave_o : out t_wishbone_slave_out;
......
hdl/rtl/timetag_core.vhd
View file @ ce4ef303
......@@ -81,12 +81,12 @@ entity timetag_core is
trig_tag_o : out t_timetag;
time_trig_o : out std_logic;
-- Alternative trigger in time
alt_trigin_enable_o : out std_logic;
alt_trigin_enable_i : in std_logic;
alt_trigin_enable_wr_i : in std_logic;
alt_trigin_tag_i : in t_timetag;
alt_trigin_o : out std_logic;
-- Auxiliary trigger in time
aux_trigin_enable_o : out std_logic;
aux_trigin_enable_i : in std_logic;
aux_trigin_enable_wr_i : in std_logic;
aux_trigin_tag_i : in t_timetag;
aux_trigin_o : out std_logic;
-- Wishbone interface
wb_i : in t_wishbone_slave_in;
......@@ -116,9 +116,9 @@ architecture rtl of timetag_core is
signal regin : t_timetag_core_master_in;
signal regout : t_timetag_core_master_out;
signal alt_trigin : std_logic;
signal alt_trigin_d : std_logic;
signal alt_trigin_enable : std_logic;
signal aux_trigin : std_logic;
signal aux_trigin_d : std_logic;
signal aux_trigin_enable : std_logic := '0';
signal wb_in : t_wishbone_slave_in;
signal wb_out : t_wishbone_slave_out;
......@@ -241,40 +241,40 @@ begin
time_trig_o <= time_trig or time_trig_d;
-- Alternative time trigger generation (also stretched).
alt_trigin <= alt_trigin_enable when alt_trigin_tag_i = current_time else '0';
-- Auxiliary time trigger generation (also stretched).
aux_trigin <= aux_trigin_enable when aux_trigin_tag_i = current_time else '0';
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
alt_trigin_enable <= '0';
aux_trigin_enable <= '0';
else
if alt_trigin_enable_wr_i = '1' then
if aux_trigin_enable_wr_i = '1' then
-- User write.
alt_trigin_enable <= alt_trigin_enable_i;
elsif alt_trigin = '1' then
aux_trigin_enable <= aux_trigin_enable_i;
elsif aux_trigin = '1' then
-- Auto clear after trigger.
alt_trigin_enable <= '0';
aux_trigin_enable <= '0';
end if;
end if;
end if;
end process;
alt_trigin_enable_o <= alt_trigin_enable;
aux_trigin_enable_o <= aux_trigin_enable;
process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
alt_trigin_d <= '0';
aux_trigin_d <= '0';
else
alt_trigin_d <= alt_trigin;
aux_trigin_d <= aux_trigin;
end if;
end if;
end process;
alt_trigin_o <= alt_trigin or alt_trigin_d;
aux_trigin_o <= aux_trigin or aux_trigin_d;
------------------------------------------------------------------------------
-- Last trigger event time-tag
......
hdl/testbench/fmc_adc_mezzanine/main.sv
View file @ ce4ef303
......@@ -3,8 +3,8 @@
`include "vhd_wishbone_master.svh"
`include "fmc_adc_100Ms_csr.v"
`include "timetag_core_regs.v"
`include "fmc_adc_alt_trigin.v"
`include "fmc_adc_alt_trigout.v"
`include "fmc_adc_aux_trigin.v"
`include "fmc_adc_aux_trigout.v"
`define SDB_ADDR 'h0000
`define CSR_BASE 'h1000
......@@ -217,9 +217,6 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH2_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH3_TRIG_THRES, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_CH4_TRIG_THRES, val);
// Enable only software trigger.
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
expected = 'h39;
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_STA, val);
......@@ -230,22 +227,13 @@ module main;
end
// Check trigout status
trigout_acc.read(`ADDR_ALT_TRIGOUT_STATUS, val);
val &= `ALT_TRIGOUT_TS_PRESENT;
trigout_acc.read(`ADDR_AUX_TRIGOUT_STATUS, val);
val &= `AUX_TRIGOUT_TS_PRESENT;
expected = 0;
if (val != expected)
$fatal (1, "trigout status error (got 0x%8x, expected 0x%8x).",
val, expected);
// Save all triggers in trigout fifo.
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
val |= `FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT
| `FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1
| `FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2
| `FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3
| `FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
#1us;
acc.write(`TAG_BASE + `ADDR_TIMETAG_CORE_REGS_SECONDS_UPPER, 'h00000032); // timetag core seconds high
......@@ -291,8 +279,7 @@ module main;
// FMC-ADC core trigger configuration
acc.read(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
val |= (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_SW_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET) |
val |= (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET) |
(1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_CH3_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
......@@ -356,14 +343,14 @@ module main;
#1us;
// set time trigger
trigin_acc.write(`ADDR_ALT_TRIGIN_SECONDS + 0, 'h00000032);
trigin_acc.write(`ADDR_ALT_TRIGIN_SECONDS + 4, 'h00005a34);
trigin_acc.write(`ADDR_AUX_TRIGIN_SECONDS + 0, 'h00000032);
trigin_acc.write(`ADDR_AUX_TRIGIN_SECONDS + 4, 'h00005a34);
acc.read(`TAG_BASE + `ADDR_TIMETAG_CORE_REGS_TIME_TRIG_COARSE, val);
trigin_acc.write(`ADDR_ALT_TRIGIN_CYCLES, val + 'h00001000);
trigin_acc.write(`ADDR_ALT_TRIGIN_CTRL, `ALT_TRIGIN_CTRL_ENABLE);
trigin_acc.write(`ADDR_AUX_TRIGIN_CYCLES, val + 'h00001000);
trigin_acc.write(`ADDR_AUX_TRIGIN_CTRL, `AUX_TRIGIN_CTRL_ENABLE);
trigin_acc.read(`ADDR_ALT_TRIGIN_CTRL, val);
expected = `ALT_TRIGIN_CTRL_ENABLE;
trigin_acc.read(`ADDR_AUX_TRIGIN_CTRL, val);
expected = `AUX_TRIGIN_CTRL_ENABLE;
if (val != expected)
begin
$fatal (1, "trigin ctrl error (got 0x%8x, expected 0x%8x).",
......@@ -374,8 +361,7 @@ module main;
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_POST_SAMPLES, 'h00000008);
// FMC-ADC core trigger configuration
val = (1'b1 << `FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, val);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_TRIG_EN, 0);
acc.write(`CSR_BASE + `ADDR_FMC_ADC_100MS_CSR_SHOTS, 'h0000001);
......@@ -386,7 +372,7 @@ module main;
wait (acq_fsm_state == 1);
trigin_acc.read(`ADDR_ALT_TRIGIN_CTRL, val);
trigin_acc.read(`ADDR_AUX_TRIGIN_CTRL, val);
expected = 0;
if (val != expected)
begin
......@@ -401,13 +387,13 @@ module main;
while (1) begin
uint64_t sec_hi, sec_lo, cycs;
trigout_acc.read(`ADDR_ALT_TRIGOUT_STATUS, val);
if (!(val & `ALT_TRIGOUT_TS_PRESENT))
trigout_acc.read(`ADDR_AUX_TRIGOUT_STATUS, val);
if (!(val & `AUX_TRIGOUT_TS_PRESENT))
break;
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_MASK_SEC + 0, sec_hi);
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_MASK_SEC + 4, sec_lo);
trigout_acc.read(`ADDR_ALT_TRIGOUT_TS_CYCLES, cycs);
trigout_acc.read(`ADDR_AUX_TRIGOUT_TS_MASK_SEC + 0, sec_hi);
trigout_acc.read(`ADDR_AUX_TRIGOUT_TS_MASK_SEC + 4, sec_lo);
trigout_acc.read(`ADDR_AUX_TRIGOUT_TS_CYCLES, cycs);
$display("trigout TS: 0x%16x 0x%8x",
((sec_hi << 32) | sec_lo), cycs);
......
hdl/testbench/include/fmc_adc_100Ms_csr.v
View file @ ce4ef303
......@@ -47,8 +47,8 @@
`define FMC_ADC_100MS_CSR_TRIG_EN_SW 'h2
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME_OFFSET 4
`define FMC_ADC_100MS_CSR_TRIG_EN_TIME 'h10
`define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME_OFFSET 5
`define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME 'h20
`define FMC_ADC_100MS_CSR_TRIG_EN_AUX_TIME_OFFSET 5
`define FMC_ADC_100MS_CSR_TRIG_EN_AUX_TIME 'h20
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1_OFFSET 8
`define FMC_ADC_100MS_CSR_TRIG_EN_CH1 'h100
`define FMC_ADC_100MS_CSR_TRIG_EN_CH2_OFFSET 9
......@@ -57,16 +57,6 @@
`define FMC_ADC_100MS_CSR_TRIG_EN_CH3 'h400
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4_OFFSET 11
`define FMC_ADC_100MS_CSR_TRIG_EN_CH4 'h800
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT_OFFSET 16
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT 'h10000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1_OFFSET 24
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1 'h1000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2_OFFSET 25
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2 'h2000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3_OFFSET 26
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3 'h4000000
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4_OFFSET 27
`define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4 'h8000000
`define ADDR_FMC_ADC_100MS_CSR_TRIG_POL 'h10
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT_OFFSET 0
`define FMC_ADC_100MS_CSR_TRIG_POL_EXT 'h1
......
hdl/testbench/include/fmc_adc_alt_trigin.v deleted 100644 → 0
View file @ 449a1292
`define ALT_TRIGIN_SIZE 20
`define ADDR_ALT_TRIGIN_VERSION 'h0
`define ALT_TRIGIN_VERSION_PRESET 'hadc10001
`define ADDR_ALT_TRIGIN_CTRL 'h4
`define ALT_TRIGIN_CTRL_ENABLE_OFFSET 0
`define ALT_TRIGIN_CTRL_ENABLE 'h1
`define ADDR_ALT_TRIGIN_SECONDS 'h8
`define ADDR_ALT_TRIGIN_CYCLES 'h10
hdl/testbench/include/fmc_adc_alt_trigout.v deleted 100644 → 0
View file @ 449a1292
`define ALT_TRIGOUT_SIZE 20
`define ADDR_ALT_TRIGOUT_STATUS 'h0
`define ALT_TRIGOUT_WR_ENABLE_OFFSET 0
`define ALT_TRIGOUT_WR_ENABLE 'h1
`define ALT_TRIGOUT_WR_LINK_OFFSET 1
`define ALT_TRIGOUT_WR_LINK 'h2
`define ALT_TRIGOUT_WR_VALID_OFFSET 2
`define ALT_TRIGOUT_WR_VALID 'h4
`define ALT_TRIGOUT_TS_PRESENT_OFFSET 8
`define ALT_TRIGOUT_TS_PRESENT 'h100
`define ADDR_ALT_TRIGOUT_TS_MASK_SEC 'h8
`define ALT_TRIGOUT_TS_SEC_OFFSET 0
`define ALT_TRIGOUT_TS_SEC 'hffffffffff
`define ALT_TRIGOUT_CH1_MASK_OFFSET 48
`define ALT_TRIGOUT_CH1_MASK 'h1000000000000
`define ALT_TRIGOUT_CH2_MASK_OFFSET 49
`define ALT_TRIGOUT_CH2_MASK 'h2000000000000
`define ALT_TRIGOUT_CH3_MASK_OFFSET 50
`define ALT_TRIGOUT_CH3_MASK 'h4000000000000
`define ALT_TRIGOUT_CH4_MASK_OFFSET 51
`define ALT_TRIGOUT_CH4_MASK 'h8000000000000
`define ALT_TRIGOUT_EXT_MASK_OFFSET 56
`define ALT_TRIGOUT_EXT_MASK 'h100000000000000
`define ADDR_ALT_TRIGOUT_TS_CYCLES 'h10
`define ALT_TRIGOUT_CYCLES_OFFSET 0
`define ALT_TRIGOUT_CYCLES 'hfffffff
hdl/testbench/include/fmc_adc_aux_trigin.v 0 → 100644
View file @ ce4ef303
`define AUX_TRIGIN_SIZE 20
`define ADDR_AUX_TRIGIN_VERSION 'h0
`define AUX_TRIGIN_VERSION_PRESET 'hadc10001
`define ADDR_AUX_TRIGIN_CTRL 'h4
`define AUX_TRIGIN_CTRL_ENABLE_OFFSET 0
`define AUX_TRIGIN_CTRL_ENABLE 'h1
`define ADDR_AUX_TRIGIN_SECONDS 'h8
`define ADDR_AUX_TRIGIN_CYCLES 'h10
hdl/testbench/include/fmc_adc_aux_trigout.v 0 → 100644
View file @ ce4ef303
`define AUX_TRIGOUT_SIZE 20
`define ADDR_AUX_TRIGOUT_STATUS 'h0
`define AUX_TRIGOUT_WR_ENABLE_OFFSET 0
`define AUX_TRIGOUT_WR_ENABLE 'h1
`define AUX_TRIGOUT_WR_LINK_OFFSET 1
`define AUX_TRIGOUT_WR_LINK 'h2
`define AUX_TRIGOUT_WR_VALID_OFFSET 2
`define AUX_TRIGOUT_WR_VALID 'h4
`define AUX_TRIGOUT_TS_PRESENT_OFFSET 8
`define AUX_TRIGOUT_TS_PRESENT 'h100
`define ADDR_AUX_TRIGOUT_TS_MASK_SEC 'h8
`define AUX_TRIGOUT_TS_SEC_OFFSET 0
`define AUX_TRIGOUT_TS_SEC 'hffffffffff
`define AUX_TRIGOUT_CH1_MASK_OFFSET 48
`define AUX_TRIGOUT_CH1_MASK 'h1000000000000
`define AUX_TRIGOUT_CH2_MASK_OFFSET 49
`define AUX_TRIGOUT_CH2_MASK 'h2000000000000
`define AUX_TRIGOUT_CH3_MASK_OFFSET 50
`define AUX_TRIGOUT_CH3_MASK 'h4000000000000
`define AUX_TRIGOUT_CH4_MASK_OFFSET 51
`define AUX_TRIGOUT_CH4_MASK 'h8000000000000
`define AUX_TRIGOUT_EXT_MASK_OFFSET 56
`define AUX_TRIGOUT_EXT_MASK 'h100000000000000
`define ADDR_AUX_TRIGOUT_TS_CYCLES 'h10
`define AUX_TRIGOUT_CYCLES_OFFSET 0
`define AUX_TRIGOUT_CYCLES 'hfffffff
software/include/hw/fmc_adc_100Ms_csr.h
View file @ ce4ef303
......@@ -36,16 +36,11 @@
#define FMC_ADC_100MS_CSR_TRIG_EN_EXT 0x1UL
#define FMC_ADC_100MS_CSR_TRIG_EN_SW 0x2UL
#define FMC_ADC_100MS_CSR_TRIG_EN_TIME 0x10UL
#define FMC_ADC_100MS_CSR_TRIG_EN_ALT_TIME 0x20UL
#define FMC_ADC_100MS_CSR_TRIG_EN_AUX_TIME 0x20UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH1 0x100UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH2 0x200UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH3 0x400UL
#define FMC_ADC_100MS_CSR_TRIG_EN_CH4 0x800UL
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_EXT 0x10000UL
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH1 0x1000000UL
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH2 0x2000000UL
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH3 0x4000000UL
#define FMC_ADC_100MS_CSR_TRIG_EN_FWD_CH4 0x8000000UL
/* Trigger polarity */
#define FMC_ADC_100MS_CSR_TRIG_POL 0x10UL
......
software/include/hw/fmc_adc_alt_trigin.h → software/include/hw/fmc_adc_aux_trigin.h
View file @ ce4ef303
#ifndef __CHEBY__ALT_TRIGIN__H__
#define __CHEBY__ALT_TRIGIN__H__
#ifndef __CHEBY__AUX_TRIGIN__H__
#define __CHEBY__AUX_TRIGIN__H__
/* Core version */
#define ALT_TRIGIN_VERSION 0x0UL
#define ALT_TRIGIN_VERSION_PRESET 0xadc10001UL
#define AUX_TRIGIN_VERSION 0x0UL
#define AUX_TRIGIN_VERSION_PRESET 0xadc10001UL
/* Control register */
#define ALT_TRIGIN_CTRL 0x4UL
#define ALT_TRIGIN_CTRL_ENABLE 0x1UL
#define AUX_TRIGIN_CTRL 0x4UL
#define AUX_TRIGIN_CTRL_ENABLE 0x1UL
/* Time (seconds) to trigger */
#define ALT_TRIGIN_SECONDS 0x8UL
#define AUX_TRIGIN_SECONDS 0x8UL
/* Time (cycles) to trigger */
#define ALT_TRIGIN_CYCLES 0x10UL
#define AUX_TRIGIN_CYCLES 0x10UL
struct alt_trigin {
struct aux_trigin {
/* [0x0]: REG (ro) Core version */
uint32_t version;
......@@ -29,4 +29,4 @@ struct alt_trigin {
uint32_t cycles;
};
#endif /* __CHEBY__ALT_TRIGIN__H__ */
#endif /* __CHEBY__AUX_TRIGIN__H__ */
software/include/hw/fmc_adc_alt_trigout.h → software/include/hw/fmc_adc_aux_trigout.h
View file @ ce4ef303
#ifndef __CHEBY__ALT_TRIGOUT__H__
#define __CHEBY__ALT_TRIGOUT__H__
#ifndef __CHEBY__AUX_TRIGOUT__H__
#define __CHEBY__AUX_TRIGOUT__H__
/* Status register */
#define ALT_TRIGOUT_STATUS 0x0UL
#define ALT_TRIGOUT_WR_ENABLE 0x1UL
#define ALT_TRIGOUT_WR_LINK 0x2UL
#define ALT_TRIGOUT_WR_VALID 0x4UL
#define ALT_TRIGOUT_TS_PRESENT 0x100UL
#define AUX_TRIGOUT_STATUS 0x0UL
#define AUX_TRIGOUT_WR_ENABLE 0x1UL
#define AUX_TRIGOUT_WR_LINK 0x2UL
#define AUX_TRIGOUT_WR_VALID 0x4UL
#define AUX_TRIGOUT_TS_PRESENT 0x100UL
/* Time (seconds) of the last event */
#define ALT_TRIGOUT_TS_MASK_SEC 0x8UL
#define ALT_TRIGOUT_TS_SEC_MASK 0xffffffffffULL
#define ALT_TRIGOUT_TS_SEC_SHIFT 0
#define ALT_TRIGOUT_CH1_MASK 0x1000000000000ULL
#define ALT_TRIGOUT_CH2_MASK 0x2000000000000ULL
#define ALT_TRIGOUT_CH3_MASK 0x4000000000000ULL
#define ALT_TRIGOUT_CH4_MASK 0x8000000000000ULL
#define ALT_TRIGOUT_EXT_MASK 0x100000000000000ULL
#define AUX_TRIGOUT_TS_MASK_SEC 0x8UL
#define AUX_TRIGOUT_TS_SEC_MASK 0xffffffffffULL
#define AUX_TRIGOUT_TS_SEC_SHIFT 0
#define AUX_TRIGOUT_CH1_MASK 0x1000000000000ULL
#define AUX_TRIGOUT_CH2_MASK 0x2000000000000ULL
#define AUX_TRIGOUT_CH3_MASK 0x4000000000000ULL
#define AUX_TRIGOUT_CH4_MASK 0x8000000000000ULL
#define AUX_TRIGOUT_EXT_MASK 0x100000000000000ULL
/* Cycles part of timestamp fifo. */
#define ALT_TRIGOUT_TS_CYCLES 0x10UL
#define ALT_TRIGOUT_CYCLES_MASK 0xfffffffUL
#define ALT_TRIGOUT_CYCLES_SHIFT 0
#define AUX_TRIGOUT_TS_CYCLES 0x10UL
#define AUX_TRIGOUT_CYCLES_MASK 0xfffffffUL
#define AUX_TRIGOUT_CYCLES_SHIFT 0
struct alt_trigout {
struct aux_trigout {
/* [0x0]: REG (ro) Status register */
uint32_t status;
......@@ -37,4 +37,4 @@ struct alt_trigout {
uint32_t ts_cycles;
};
#endif /* __CHEBY__ALT_TRIGOUT__H__ */
#endif /* __CHEBY__AUX_TRIGOUT__H__ */
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