Commit d0407fc2 authored by Dimitris Lampridis's avatar Dimitris Lampridis

[hdl] replace wbgen EIC with a custom one based on cheby

Signed-off-by: Dimitris Lampridis's avatarDimitris Lampridis <dimitris.lampridis@cern.ch>
parent 9f76ed4d
memory-map:
bus: wb-32-be
name: fmc_adc_eic_regs
size: 0x10
description: FMC ADC Embedded Interrupt Controller (EIC) registers
comment: |
inspired by wbgen2 EIC
x-hdl:
busgroup: True
iogroup: fmc_adc_eic_regs
children:
- reg:
name: idr
address: 0x00000000
width: 32
access: wo
description: Interrupt Disable Register
comment: |
Write 1 to a bit to disable the respective interrupt.
x-hdl:
type: wire
write-strobe: True
- reg:
name: ier
address: 0x00000004
width: 32
access: wo
description: Interrupt Enable Register
comment: |
Write 1 to a bit to enable the respective interrupt.
x-hdl:
type: wire
write-strobe: True
- reg:
name: imr
address: 0x00000008
width: 32
access: ro
description: Interrupt Mask Register
comment: |
If a bit is set to 1, it means that the respective interrupt is enabled.
- reg:
name: isr
address: 0x0000000C
width: 32
access: rw
description: Interrupt Status Register
comment: |
If a bit is set to 1, it means that the respective interrupt is pending.
Write a 0 to bit to acknowledge and clear the respective interrupt.
x-hdl:
type: wire
write-strobe: True
-- Do not edit; this file was generated by Cheby using these options:
-- -i fmc_adc_eic_regs.cheby --gen-hdl=fmc_adc_eic_regs.vhd
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
package fmc_adc_eic_regs_pkg is
type t_fmc_adc_eic_regs_master_out is record
idr : std_logic_vector(31 downto 0);
idr_wr : std_logic;
ier : std_logic_vector(31 downto 0);
ier_wr : std_logic;
isr : std_logic_vector(31 downto 0);
isr_wr : std_logic;
end record t_fmc_adc_eic_regs_master_out;
subtype t_fmc_adc_eic_regs_slave_in is t_fmc_adc_eic_regs_master_out;
type t_fmc_adc_eic_regs_slave_out is record
imr : std_logic_vector(31 downto 0);
isr : std_logic_vector(31 downto 0);
end record t_fmc_adc_eic_regs_slave_out;
subtype t_fmc_adc_eic_regs_master_in is t_fmc_adc_eic_regs_slave_out;
end fmc_adc_eic_regs_pkg;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
use work.fmc_adc_eic_regs_pkg.all;
entity fmc_adc_eic_regs is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
wb_i : in t_wishbone_slave_in;
wb_o : out t_wishbone_slave_out;
-- Wires and registers
fmc_adc_eic_regs_i : in t_fmc_adc_eic_regs_master_in;
fmc_adc_eic_regs_o : out t_fmc_adc_eic_regs_master_out
);
end fmc_adc_eic_regs;
architecture syn of fmc_adc_eic_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
signal ack_int : std_logic;
signal wb_rip : std_logic;
signal wb_wip : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
begin
-- WB decode signals
wb_en <= wb_i.cyc and wb_i.stb;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_i.we)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_i.we) and not wb_rip;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_i.we)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_i.we) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_o.ack <= ack_int;
wb_o.stall <= not ack_int and wb_en;
wb_o.rty <= '0';
wb_o.err <= '0';
-- Assign outputs
-- Process for write requests.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wr_ack_int <= '0';
fmc_adc_eic_regs_o.idr_wr <= '0';
fmc_adc_eic_regs_o.ier_wr <= '0';
fmc_adc_eic_regs_o.isr_wr <= '0';
else
wr_ack_int <= '0';
fmc_adc_eic_regs_o.idr_wr <= '0';
fmc_adc_eic_regs_o.ier_wr <= '0';
fmc_adc_eic_regs_o.isr_wr <= '0';
case wb_i.adr(3 downto 2) is
when "00" =>
-- Register idr
fmc_adc_eic_regs_o.idr_wr <= wr_int;
if wr_int = '1' then
fmc_adc_eic_regs_o.idr <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when "01" =>
-- Register ier
fmc_adc_eic_regs_o.ier_wr <= wr_int;
if wr_int = '1' then
fmc_adc_eic_regs_o.ier <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when "10" =>
-- Register imr
when "11" =>
-- Register isr
fmc_adc_eic_regs_o.isr_wr <= wr_int;
if wr_int = '1' then
fmc_adc_eic_regs_o.isr <= wb_i.dat;
end if;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end if;
end process;
-- Process for registers read.
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack1_int <= '0';
else
reg_rdat_int <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- idr
rd_ack1_int <= rd_int;
when "01" =>
-- ier
rd_ack1_int <= rd_int;
when "10" =>
-- imr
reg_rdat_int <= fmc_adc_eic_regs_i.imr;
rd_ack1_int <= rd_int;
when "11" =>
-- isr
reg_rdat_int <= fmc_adc_eic_regs_i.isr;
rd_ack1_int <= rd_int;
when others =>
reg_rdat_int <= (others => 'X');
rd_ack1_int <= rd_int;
end case;
end if;
end if;
end process;
-- Process for read requests.
process (wb_i.adr, reg_rdat_int, rd_ack1_int, rd_int) begin
-- By default ack read requests
wb_o.dat <= (others => '0');
case wb_i.adr(3 downto 2) is
when "00" =>
-- idr
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "01" =>
-- ier
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "10" =>
-- imr
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when "11" =>
-- isr
wb_o.dat <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
when others =>
rd_ack_int <= rd_int;
end case;
end process;
end syn;
......@@ -14,11 +14,8 @@ memory-map:
- submap:
name: fmc_adc_eic
address: 0x1500
size: 0x10
interface: wb-32-be
x-hdl:
busgroup: True
description: FMC ADC Embedded Interrupt Controller
filename: fmc_adc_eic_regs.cheby
- submap:
name: si570_i2c_master
address: 0x1600
......
......@@ -8,6 +8,7 @@ files = [
"timetag_core.vhd",
"../cheby/fmc_adc_mezzanine_mmap.vhd",
"../cheby/fmc_adc_100Ms_csr.vhd",
"../cheby/fmc_adc_eic_regs.vhd",
"../cheby/fmc_adc_aux_trigin.vhd",
"../cheby/fmc_adc_aux_trigout.vhd",
"../cheby/timetag_core_regs.vhd",
......
This diff is collapsed.
......@@ -406,27 +406,16 @@ begin
------------------------------------------------------------------------------
-- FMC0 interrupt controller
------------------------------------------------------------------------------
cmp_fmc0_eic : entity work.fmc_adc_eic
port map(
cmp_fmc_adc_eic : entity work.fmc_adc_eic
port map (
rst_n_i => sys_rst_n_i,
clk_sys_i => sys_clk_i,
wb_adr_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).adr(3 downto 2), -- cnx_slave_in.adr is byte address
wb_dat_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).dat,
wb_dat_o => cnx_slave_out(c_WB_SLAVE_FMC_EIC).dat,
wb_cyc_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).cyc,
wb_sel_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).sel,
wb_stb_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).stb,
wb_we_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC).we,
wb_ack_o => cnx_slave_out(c_WB_SLAVE_FMC_EIC).ack,
wb_stall_o => cnx_slave_out(c_WB_SLAVE_FMC_EIC).stall,
wb_int_o => eic_irq_o,
clk_i => sys_clk_i,
wb_i => cnx_slave_in(c_WB_SLAVE_FMC_EIC),
wb_o => cnx_slave_out(c_WB_SLAVE_FMC_EIC),
irq_trig_i => trigger_p,
irq_acq_end_i => acq_end_irq_p
);
-- Unused wishbone signals
cnx_slave_out(c_WB_SLAVE_FMC_EIC).err <= '0';
cnx_slave_out(c_WB_SLAVE_FMC_EIC).rty <= '0';
irq_acq_end_i => acq_end_irq_p,
int_o => eic_irq_o);
-- Detects end of adc core writing to ddr
p_ddr_wr_fifo_empty : process (sys_clk_i)
......
WBGEN2=$(shell which wbgen2)
RTL=../
SIM=../../testbench/include/
TEX=../../../doc/manual/
all: fmc_adc_eic
fmc_adc_eic:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -f html -D $@.htm -C $@.h $@.wb
$(WBGEN2) -f texinfo -D $(TEX)$@.tex $@.wb
/*
Register definitions for slave core: Fmc-adc embedded interrupt controller
* File : fmc_adc_eic.h
* Author : auto-generated by wbgen2 from fmc_adc_eic.wb
* Created : Thu Jun 16 17:04:12 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_eic.wb
DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
*/
#ifndef __WBGEN2_REGDEFS_FMC_ADC_EIC_WB
#define __WBGEN2_REGDEFS_FMC_ADC_EIC_WB
#ifdef __KERNEL__
#include <linux/types.h>
#else
#include <inttypes.h>
#endif
#if defined( __GNUC__)
#define PACKED __attribute__ ((packed))
#else
#error "Unsupported compiler?"
#endif
#ifndef __WBGEN2_MACROS_DEFINED__
#define __WBGEN2_MACROS_DEFINED__
#define WBGEN2_GEN_MASK(offset, size) (((1<<(size))-1) << (offset))
#define WBGEN2_GEN_WRITE(value, offset, size) (((value) & ((1<<(size))-1)) << (offset))
#define WBGEN2_GEN_READ(reg, offset, size) (((reg) >> (offset)) & ((1<<(size))-1))
#define WBGEN2_SIGN_EXTEND(value, bits) (((value) & (1<<bits) ? ~((1<<(bits))-1): 0 ) | (value))
#endif
/* definitions for register: Interrupt disable register */
/* definitions for field: Trigger interrupt in reg: Interrupt disable register */
#define FMC_ADC_EIC_EIC_IDR_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt disable register */
#define FMC_ADC_EIC_EIC_IDR_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt enable register */
/* definitions for field: Trigger interrupt in reg: Interrupt enable register */
#define FMC_ADC_EIC_EIC_IER_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt enable register */
#define FMC_ADC_EIC_EIC_IER_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt mask register */
/* definitions for field: Trigger interrupt in reg: Interrupt mask register */
#define FMC_ADC_EIC_EIC_IMR_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt mask register */
#define FMC_ADC_EIC_EIC_IMR_ACQ_END WBGEN2_GEN_MASK(1, 1)
/* definitions for register: Interrupt status register */
/* definitions for field: Trigger interrupt in reg: Interrupt status register */
#define FMC_ADC_EIC_EIC_ISR_TRIG WBGEN2_GEN_MASK(0, 1)
/* definitions for field: End of acquisition interrupt in reg: Interrupt status register */
#define FMC_ADC_EIC_EIC_ISR_ACQ_END WBGEN2_GEN_MASK(1, 1)
PACKED struct FMC_ADC_EIC_WB {
/* [0x0]: REG Interrupt disable register */
uint32_t EIC_IDR;
/* [0x4]: REG Interrupt enable register */
uint32_t EIC_IER;
/* [0x8]: REG Interrupt mask register */
uint32_t EIC_IMR;
/* [0xc]: REG Interrupt status register */
uint32_t EIC_ISR;
};
#endif
This diff is collapsed.
peripheral {
name = "Fmc-adc embedded interrupt controller";
description = "Embedded interrrupt controller for one fmc-adc mezzanine.";
hdl_entity = "fmc_adc_eic";
prefix = "fmc_adc_eic";
irq {
name = "Trigger interrupt";
description = "Trigger interrupt line (rising edge sensitive).";
prefix = "trig";
trigger = EDGE_RISING;
};
irq {
name = "End of acquisition interrupt";
description = "End of acquisition interrupt line (rising edge sensitive).";
prefix = "acq_end";
trigger = EDGE_RISING;
};
};
`define FMC_ADC_EIC_REGS_SIZE 16
`define ADDR_FMC_ADC_EIC_REGS_IDR 'h0
`define ADDR_FMC_ADC_EIC_REGS_IER 'h4
`define ADDR_FMC_ADC_EIC_REGS_IMR 'h8
`define ADDR_FMC_ADC_EIC_REGS_ISR 'hc
#ifndef __CHEBY__FMC_ADC_EIC_REGS__H__
#define __CHEBY__FMC_ADC_EIC_REGS__H__
#define FMC_ADC_EIC_REGS_SIZE 16
/* Interrupt Disable Register */
#define FMC_ADC_EIC_REGS_IDR 0x0UL
/* Interrupt Enable Register */
#define FMC_ADC_EIC_REGS_IER 0x4UL
/* Interrupt Mask Register */
#define FMC_ADC_EIC_REGS_IMR 0x8UL
/* Interrupt Status Register */
#define FMC_ADC_EIC_REGS_ISR 0xcUL
struct fmc_adc_eic_regs {
/* [0x0]: REG (wo) Interrupt Disable Register */
uint32_t idr;
/* [0x4]: REG (wo) Interrupt Enable Register */
uint32_t ier;
/* [0x8]: REG (ro) Interrupt Mask Register */
uint32_t imr;
/* [0xc]: REG (rw) Interrupt Status Register */
uint32_t isr;
};
#endif /* __CHEBY__FMC_ADC_EIC_REGS__H__ */
......@@ -2,6 +2,7 @@
#define __CHEBY__FMC_ADC_MEZZANINE_MMAP__H__
#include "timetag_core_regs.h"
#include "fmc_adc_eic_regs.h"
#include "wb_ds182x_regs.h"
#include "fmc_adc_100ms_csr.h"
#define FMC_ADC_MEZZANINE_MMAP_SIZE 8192
......@@ -41,7 +42,7 @@ struct fmc_adc_mezzanine_mmap {
uint32_t __padding_1[192];
/* [0x1500]: SUBMAP FMC ADC Embedded Interrupt Controller */
uint32_t fmc_adc_eic[4];
struct fmc_adc_eic_regs fmc_adc_eic;
/* padding to: 1408 words */
uint32_t __padding_2[60];
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment