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FMC ADC 100M 14b 4cha - Gateware
Commit d27e5a09 authored by Matthieu Cattin's avatar Matthieu Cattin
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doc, hdl: add note about the sampling frequency. 

The sampling frequency can't be changed dynamically in the current design.
This is due to the internal fpga pll that is configured for a fixed 400MHz input.
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doc/manual/fmcadc100m14b4cha_gateware_manual.in
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...@@ -583,6 +583,8 @@ Then the data clock (DCO) output of the LTC2174 is connected to the FPGA. ...@@ -583,6 +583,8 @@ Then the data clock (DCO) output of the LTC2174 is connected to the FPGA.
The data clock is four times the sampling clock. The data clock is four times the sampling clock.
The sampling clock (@code{fs_clk}) and the ADC data de-serialiser clock (@code{serdes_clk}) are derived from the data clock using a PLL (internal to the FPGA). The sampling clock (@code{fs_clk}) and the ADC data de-serialiser clock (@code{serdes_clk}) are derived from the data clock using a PLL (internal to the FPGA).
@b{Note:} The internal PLL expects a 400MHz input frequency (define in the hdl code), therefore the sampling frequency has to be 100MHz and can't be change dynamically.
@c TODO : possibility to control the Si570 via I2C @c TODO : possibility to control the Si570 via I2C
The ADC core implements a sampling clock frequency meter. The ADC core implements a sampling clock frequency meter.
...@@ -1222,6 +1224,7 @@ The @ref{fig:mem_multi_shot} shows the shots organisation in the DDR memory. ...@@ -1222,6 +1224,7 @@ The @ref{fig:mem_multi_shot} shows the shots organisation in the DDR memory.
@c DONE @item Add hysteresis on internal trigger slope detection (-> non-monotonic signals, noisy). @c DONE @item Add hysteresis on internal trigger slope detection (-> non-monotonic signals, noisy).
@c DONE @item Add debug mode: ch1=analog input, ch2=int_trig_over_thres, ch3=int_trig, ch4=trig @c DONE @item Add debug mode: ch1=analog input, ch2=int_trig_over_thres, ch3=int_trig, ch4=trig
@c DONE @item Make data saturation programmable. @c DONE @item Make data saturation programmable.
@item Trigger hold-off in multi-shot mode?
@end itemize @end itemize
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hdl/adc/rtl/fmc_adc_100Ms_core.vhd
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...@@ -524,6 +524,8 @@ begin ...@@ -524,6 +524,8 @@ begin
-- Clock PLL for SerDes -- Clock PLL for SerDes
-- LTC2174-14 must be configured in 16-bit serialization -- LTC2174-14 must be configured in 16-bit serialization
-- dco_clk = 4*fs_clk = 400MHz -- dco_clk = 4*fs_clk = 400MHz
-- WARNING : The PLL expects a 400MHz input frequency, therefore the sampling
-- frequency has to be 100MHz and can't be change dynamically.
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_serdes_clk_pll : PLL_BASE cmp_serdes_clk_pll : PLL_BASE
generic map ( generic map (
......
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