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FMC ADC 100M 14b 4cha - Gateware
Commit d5592fa4 authored by mcattin's avatar mcattin
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Bug fix in serdes data reordering, add manual bitslip 

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@44 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 0b5d6966
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Showing with 285 additions and 196 deletions
hdl/spec/ip_cores/adc_serdes.vhd
View file @ d5592fa4
......@@ -232,12 +232,12 @@ begin
in_slices: for slice_count in 0 to num_serial_bits-1 generate begin
-- This places the first data in time on the right
DATA_IN_TO_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w) <=
iserdes_q(num_serial_bits-slice_count-1);
--DATA_IN_TO_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w) <=
-- iserdes_q(num_serial_bits-slice_count-1);
-- To place the first data in time on the left, use the
-- following code, instead
-- DATA_IN_TO_DEVICE(slice_count*sys_w+sys_w-1 downto sys_w) <=
-- iserdes_q(slice_count);
DATA_IN_TO_DEVICE(slice_count*sys_w+sys_w-1 downto slice_count*sys_w) <=
iserdes_q(slice_count);
end generate in_slices;
......
hdl/spec/ise_project/spec_top_summary.html
View file @ d5592fa4
......@@ -522,5 +522,5 @@ System Settings</A>
</TABLE>
<br><center><b>Date Generated:</b> 03/09/2011 - 11:19:20</center>
<br><center><b>Date Generated:</b> 03/10/2011 - 15:11:49</center>
</BODY></HTML>
\ No newline at end of file
hdl/spec/rtl/carrier_csr.vhd
View file @ d5592fa4
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/carrier_csr.vhd
-- Author : auto-generated by wbgen2 from carrier_csr.wb
-- Created : Mon Feb 28 16:09:47 2011
-- Created : Thu Mar 10 14:51:39 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE carrier_csr.wb
......
hdl/spec/rtl/fmc_adc_100Ms_core.vhd
View file @ d5592fa4
......@@ -132,6 +132,7 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_ctl_fsm_cmd_wr_o : out std_logic;
fmc_adc_core_ctl_fmc_clk_oe_o : out std_logic;
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
fmc_adc_core_ctl_man_bitslip_o : out std_logic;
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
fmc_adc_core_sta_serdes_pll_i : in std_logic;
fmc_adc_core_sta_serdes_synced_i : in std_logic;
......@@ -260,14 +261,16 @@ architecture rtl of fmc_adc_100Ms_core is
signal fs_clk_buf : std_logic;
-- SerDes
signal serdes_in_p : std_logic_vector(8 downto 0);
signal serdes_in_n : std_logic_vector(8 downto 0);
signal serdes_out_raw : std_logic_vector(71 downto 0);
signal serdes_out_data : std_logic_vector(63 downto 0);
signal serdes_out_fr : std_logic_vector(7 downto 0);
signal serdes_bitslip : std_logic;
signal serdes_synced : std_logic;
signal bitslip_sreg : std_logic_vector(7 downto 0);
signal serdes_in_p : std_logic_vector(8 downto 0);
signal serdes_in_n : std_logic_vector(8 downto 0);
signal serdes_out_raw : std_logic_vector(71 downto 0);
signal serdes_out_data : std_logic_vector(63 downto 0);
signal serdes_out_fr : std_logic_vector(7 downto 0);
signal serdes_auto_bitslip : std_logic;
signal serdes_man_bitslip : std_logic;
signal serdes_bitslip : std_logic;
signal serdes_synced : std_logic;
signal bitslip_sreg : std_logic_vector(7 downto 0);
-- Trigger
signal ext_trig_a : std_logic;
......@@ -355,18 +358,18 @@ begin
gpio_led_power_o <= serdes_synced;
cmp_trig_led_monostable : monostable
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '1',
g_OUTPUT_RETRIG => true,
g_OUTPUT_LENGTH => 12500000
)
port map(
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
trigger_i => acq_fsm_trig,
pulse_o => gpio_led_trigger_o
);
generic map(
g_INPUT_POLARITY => '1',
g_OUTPUT_POLARITY => '1',
g_OUTPUT_RETRIG => true,
g_OUTPUT_LENGTH => 12500000
)
port map(
rst_n_i => sys_rst_n_i,
clk_i => sys_clk_i,
trigger_i => acq_fsm_trig,
pulse_o => gpio_led_trigger_o
);
------------------------------------------------------------------------------
-- Resets
......@@ -460,16 +463,19 @@ begin
& adc_outa_n_i(1) & adc_outb_n_i(1)
& adc_outa_n_i(0) & adc_outb_n_i(0);
-- serdes outputs re-ordering
-- out_raw(7:0) = CH1D12 CH1D10 CH1D8 CH1D6 CH1D4 CH1D2 CH1D0 0 = CH1_B
-- out_raw(15:8) = CH1D13 CH1D11 CH1D9 CH1D7 CH1D5 CH1D3 CH1D1 0 = CH1_A
-- out_raw(23:16) = CH2D12 CH2D10 CH2D8 CH2D6 CH2D4 CH2D2 CH2D0 0 = CH2_B
-- out_raw(31:24) = CH2D13 CH2D11 CH2D9 CH2D7 CH2D5 CH2D3 CH2D1 0 = CH2_A
-- out_raw(39:32) = CH3D12 CH3D10 CH3D8 CH3D6 CH3D4 CH3D2 CH3D0 0 = CH3_B
-- out_raw(47:40) = CH3D13 CH3D11 CH3D9 CH3D7 CH3D5 CH3D3 CH3D1 0 = CH3_A
-- out_raw(55:48) = CH4D12 CH4D10 CH4D8 CH4D6 CH4D4 CH4D2 CH4D0 0 = CH4_B
-- out_raw(63:56) = CH4D13 CH4D11 CH4D9 CH4D7 CH4D5 CH4D3 CH4D1 0 = CH4_A
-- out_raw(71:64) = FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 = FR
-- serdes outputs re-ordering (time slices -> channel)
-- out_raw :(71:63)(62:54)(53:45)(44:36)(35:27)(26:18)(17:9)(8:0)
-- | | | | | | | |
-- V V V V V V V V
-- CH1D12 CH1D10 CH1D8 CH1D6 CH1D4 CH1D2 CH1D0 0 = CH1_B
-- CH1D13 CH1D11 CH1D9 CH1D7 CH1D5 CH1D3 CH1D1 0 = CH1_A
-- CH2D12 CH2D10 CH2D8 CH2D6 CH2D4 CH2D2 CH2D0 0 = CH2_B
-- CH2D13 CH2D11 CH2D9 CH2D7 CH2D5 CH2D3 CH2D1 0 = CH2_A
-- CH3D12 CH3D10 CH3D8 CH3D6 CH3D4 CH3D2 CH3D0 0 = CH3_B
-- CH3D13 CH3D11 CH3D9 CH3D7 CH3D5 CH3D3 CH3D1 0 = CH3_A
-- CH4D12 CH4D10 CH4D8 CH4D6 CH4D4 CH4D2 CH4D0 0 = CH4_B
-- CH4D13 CH4D11 CH4D9 CH4D7 CH4D5 CH4D3 CH4D1 0 = CH4_A
-- FR7 FR6 FR5 FR4 FR3 FR2 FR1 FR0 = FR
--
-- out_data(15:0) = CH1
-- out_data(31:16) = CH2
......@@ -477,24 +483,24 @@ begin
-- out_data(63:48) = CH4
-- Note: The two LSBs of each channel are always '0' => 14-bit ADC
gen_serdes_dout_reorder : for I in 0 to 7 generate
serdes_out_data(0*16 + 2*i) <= serdes_out_raw(i + 0*8); -- CH1 even bits
serdes_out_data(0*16 + 2*i+1) <= serdes_out_raw(i + 1*8); -- CH1 odd bits
serdes_out_data(1*16 + 2*i) <= serdes_out_raw(i + 2*8); -- CH2 even bits
serdes_out_data(1*16 + 2*i+1) <= serdes_out_raw(i + 3*8); -- CH2 odd bits
serdes_out_data(2*16 + 2*i) <= serdes_out_raw(i + 4*8); -- CH3 even bits
serdes_out_data(2*16 + 2*i+1) <= serdes_out_raw(i + 5*8); -- CH3 odd bits
serdes_out_data(3*16 + 2*i) <= serdes_out_raw(i + 6*8); -- CH4 even bits
serdes_out_data(3*16 + 2*i+1) <= serdes_out_raw(i + 7*8); -- CH4 odd bits
serdes_out_fr(i) <= serdes_out_raw(i + 8*8); -- FR
serdes_out_data(0*16 + 2*i) <= serdes_out_raw(0 + i*9); -- CH1 even bits
serdes_out_data(0*16 + 2*i+1) <= serdes_out_raw(1 + i*9); -- CH1 odd bits
serdes_out_data(1*16 + 2*i) <= serdes_out_raw(2 + i*9); -- CH2 even bits
serdes_out_data(1*16 + 2*i+1) <= serdes_out_raw(3 + i*9); -- CH2 odd bits
serdes_out_data(2*16 + 2*i) <= serdes_out_raw(4 + i*9); -- CH3 even bits
serdes_out_data(2*16 + 2*i+1) <= serdes_out_raw(5 + i*9); -- CH3 odd bits
serdes_out_data(3*16 + 2*i) <= serdes_out_raw(6 + i*9); -- CH4 even bits
serdes_out_data(3*16 + 2*i+1) <= serdes_out_raw(7 + i*9); -- CH4 odd bits
serdes_out_fr(i) <= serdes_out_raw(8 + i*9); -- FR
end generate gen_serdes_dout_reorder;
-- serdes bitslip generation
p_bitslip : process (fs_clk, sys_rst_n_i)
p_auto_bitslip : process (fs_clk, sys_rst_n_i)
begin
if sys_rst_n_i = '0' then
bitslip_sreg <= std_logic_vector(to_unsigned(1, bitslip_sreg'length));
serdes_bitslip <= '0';
serdes_auto_bitslip <= '0';
serdes_synced <= '0';
elsif rising_edge(fs_clk) then
......@@ -504,19 +510,21 @@ begin
-- Generate bitslip and synced signal
if(bitslip_sreg(bitslip_sreg'left) = '1') then
if(serdes_out_fr /= "11110000") then
serdes_bitslip <= '1';
serdes_auto_bitslip <= '1';
serdes_synced <= '0';
else
serdes_bitslip <= '0';
serdes_auto_bitslip <= '0';
serdes_synced <= '1';
end if;
else
serdes_bitslip <= '0';
serdes_auto_bitslip <= '0';
end if;
end if;
end process;
serdes_bitslip <= serdes_auto_bitslip or serdes_man_bitslip;
------------------------------------------------------------------------------
-- ADC core control and status registers (CSR)
------------------------------------------------------------------------------
......@@ -537,6 +545,7 @@ begin
fmc_adc_core_ctl_fsm_cmd_wr_o => fsm_cmd_wr,
fmc_adc_core_ctl_fmc_clk_oe_o => gpio_si570_oe_o,
fmc_adc_core_ctl_offset_dac_clr_n_o => gpio_dac_clr_n_o,
fmc_adc_core_ctl_man_bitslip_o => serdes_man_bitslip,
fmc_adc_core_sta_fsm_i => "000",
fmc_adc_core_sta_serdes_pll_i => locked_out,
fmc_adc_core_sta_serdes_synced_i => serdes_synced,
......@@ -562,13 +571,13 @@ begin
fmc_adc_core_post_samples_o => post_trig_value,
fmc_adc_core_samp_cnt_i => X"00000000",
fmc_adc_core_ch1_ssr_o => gpio_ssr_ch1_o,
fmc_adc_core_ch1_val_i => X"0000",
fmc_adc_core_ch1_val_i => sync_fifo_dout(15 downto 0),
fmc_adc_core_ch2_ssr_o => gpio_ssr_ch2_o,
fmc_adc_core_ch2_val_i => X"0000",
fmc_adc_core_ch2_val_i => sync_fifo_dout(31 downto 16),
fmc_adc_core_ch3_ssr_o => gpio_ssr_ch3_o,
fmc_adc_core_ch3_val_i => X"0000",
fmc_adc_core_ch3_val_i => sync_fifo_dout(47 downto 32),
fmc_adc_core_ch4_ssr_o => gpio_ssr_ch4_o,
fmc_adc_core_ch4_val_i => X"0000"
fmc_adc_core_ch4_val_i => sync_fifo_dout(63 downto 48)
);
------------------------------------------------------------------------------
......
hdl/spec/rtl/fmc_adc_100Ms_csr.vhd
View file @ d5592fa4
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Fri Mar 4 14:20:32 2011
-- Created : Wed Mar 16 11:36:21 2011
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -34,6 +34,8 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_ctl_fmc_clk_oe_o : out std_logic;
-- Port for BIT field: 'Offset DACs clear (active low)' in reg: 'Control register'
fmc_adc_core_ctl_offset_dac_clr_n_o : out std_logic;
-- Port for BIT field: 'Manual serdes bitslip' in reg: 'Control register'
fmc_adc_core_ctl_man_bitslip_o : out std_logic;
-- Port for std_logic_vector field: 'State machine status' in reg: 'Status register'
fmc_adc_core_sta_fsm_i : in std_logic_vector(2 downto 0);
-- Port for BIT field: 'SerDes PLL status' in reg: 'Status register'
......@@ -104,6 +106,7 @@ architecture syn of fmc_adc_100Ms_csr is
signal fmc_adc_core_ctl_fmc_clk_oe_int : std_logic ;
signal fmc_adc_core_ctl_offset_dac_clr_n_int : std_logic ;
signal fmc_adc_core_ctl_man_bitslip_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_int : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync0 : std_logic ;
signal fmc_adc_core_trig_cfg_hw_trig_sel_sync1 : std_logic ;
......@@ -180,6 +183,7 @@ begin
fmc_adc_core_ctl_fsm_cmd_wr_o <= '0';
fmc_adc_core_ctl_fmc_clk_oe_int <= '0';
fmc_adc_core_ctl_offset_dac_clr_n_int <= '0';
fmc_adc_core_ctl_man_bitslip_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_sel_int <= '0';
fmc_adc_core_trig_cfg_ext_trig_pol_int <= '0';
fmc_adc_core_trig_cfg_hw_trig_en_int <= '0';
......@@ -231,12 +235,13 @@ begin
fmc_adc_core_ctl_fsm_cmd_wr_o <= '1';
fmc_adc_core_ctl_fmc_clk_oe_int <= wrdata_reg(2);
fmc_adc_core_ctl_offset_dac_clr_n_int <= wrdata_reg(3);
fmc_adc_core_ctl_man_bitslip_int <= wrdata_reg(4);
else
rddata_reg(2) <= fmc_adc_core_ctl_fmc_clk_oe_int;
rddata_reg(3) <= fmc_adc_core_ctl_offset_dac_clr_n_int;
rddata_reg(4) <= fmc_adc_core_ctl_man_bitslip_int;
rddata_reg(0) <= 'X';
rddata_reg(1) <= 'X';
rddata_reg(4) <= 'X';
rddata_reg(5) <= 'X';
rddata_reg(6) <= 'X';
rddata_reg(7) <= 'X';
......@@ -734,6 +739,8 @@ begin
fmc_adc_core_ctl_fmc_clk_oe_o <= fmc_adc_core_ctl_fmc_clk_oe_int;
-- Offset DACs clear (active low)
fmc_adc_core_ctl_offset_dac_clr_n_o <= fmc_adc_core_ctl_offset_dac_clr_n_int;
-- Manual serdes bitslip
fmc_adc_core_ctl_man_bitslip_o <= fmc_adc_core_ctl_man_bitslip_int;
-- State machine status
-- SerDes PLL status
-- SerDes synchronization status
......
hdl/spec/rtl/spec_top_fmc_adc_100Ms.vhd
View file @ d5592fa4
......@@ -31,7 +31,7 @@ library UNISIM;
use UNISIM.vcomponents.all;
entity spec_top is
entity spec_top_fmc_adc_100Ms is
generic(
g_SIMULATION : string := "FALSE";
g_CALIB_SOFT_IP : string := "TRUE");
......@@ -130,10 +130,10 @@ entity spec_top is
prsnt_m2c_n_i : in std_logic -- Mezzanine present (active low)
);
end spec_top;
end spec_top_fmc_adc_100Ms;
architecture rtl of spec_top is
architecture rtl of spec_top_fmc_adc_100Ms is
------------------------------------------------------------------------------
-- Components declaration
......@@ -574,6 +574,7 @@ architecture rtl of spec_top is
signal spi_sck_t : std_logic_vector(2 downto 0);
signal spi_din_t : std_logic_vector(2 downto 0);
signal spi_dout_t : std_logic_vector(2 downto 0);
signal spi_ss_t : std_logic_vector(7 downto 0);
begin
......@@ -751,15 +752,16 @@ begin
------------------------------------------------------------------------------
-- CSR wishbone bus slaves
-- 0 -> Carrier SPI master
-- 1 -> Carrier I2C master
-- 2 -> Carrier CSR
-- 3 -> UTC core
-- 4 -> Interrupt controller
-- 5 -> Mezzanine system managment I2C master
-- 6 -> Mezzanine SPI master
-- 7 -> Mezzanine I2C master
-- 8 -> Mezzanine ADC core
-- (0x00000 -> DMA configuration)
-- 0x10000 -> Carrier SPI master
-- 0x20000 -> Carrier I2C master
-- 0x30000 -> Carrier CSR
-- 0x40000 -> UTC core
-- 0x50000 -> Interrupt controller
-- 0x60000 -> Mezzanine system managment I2C master
-- 0x70000 -> Mezzanine SPI master
-- 0x80000 -> Mezzanine I2C master
-- 0x90000 -> Mezzanine ADC core
------------------------------------------------------------------------------
------------------------------------------------------------------------------
......@@ -861,14 +863,7 @@ begin
wb_ack_o => wb_ack_fmc_spi,
wb_err_o => open,
wb_int_o => open,
ss_pad_o(0) => spi_cs_adc_n_o,
ss_pad_o(1) => spi_cs_dac1_n_o,
ss_pad_o(2) => spi_cs_dac2_n_o,
ss_pad_o(3) => spi_cs_dac3_n_o,
ss_pad_o(4) => spi_cs_dac4_n_o,
ss_pad_o(5) => open,
ss_pad_o(6) => open,
ss_pad_o(7) => open,
ss_pad_o => spi_ss_t,
sclk_pad_o => spi_sck_o,
mosi_pad_o => spi_dout_o,
miso_pad_i => spi_din_t(2)
......@@ -877,8 +872,15 @@ begin
-- 32-bit word to byte address
wb_adr_fmc_spi <= wb_adr(2 downto 0) & "00";
-- Assign slave select lines
spi_cs_adc_n_o <= spi_ss_t(0);
spi_cs_dac1_n_o <= spi_ss_t(1);
spi_cs_dac2_n_o <= spi_ss_t(2);
spi_cs_dac3_n_o <= spi_ss_t(3);
spi_cs_dac4_n_o <= spi_ss_t(4);
-- Add some FF after the input pin to solve timing problem
p_fmc_spi: process (sys_clk_125)
p_fmc_spi : process (sys_clk_125)
begin
if rising_edge(sys_clk_125) then
if sys_rst_n = '0' then
......@@ -899,7 +901,7 @@ begin
ARST_LVL => '0')
port map (
wb_clk_i => sys_clk_125,
wb_rst_i => sys_rst_n,
wb_rst_i => sys_rst,
arst_i => '1',
wb_adr_i => wb_adr_fmc_i2c(2 downto 0),
wb_dat_i => wb_dat_o(7 downto 0),
......
hdl/spec/wb_gen/Makefile
View file @ d5592fa4
......@@ -2,7 +2,7 @@ WBGEN2=../../../../wbgen2/wishbone-gen/wbgen2
RTL=../rtl/
carrier_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -C $@.h $@.wb
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm $@.wb
fmc_adc_100Ms_csr:
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -C $@.h $@.wb
\ No newline at end of file
$(WBGEN2) -l vhdl -V $(RTL)$@.vhd -D $@.htm $@.wb
\ No newline at end of file
hdl/spec/wb_gen/fmc_adc_100Ms_csr.wb
View file @ d5592fa4
......@@ -34,6 +34,14 @@ peripheral {
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
field {
name = "Manual serdes bitslip";
prefix = "man_bitslip";
type = BIT;
access_bus = READ_WRITE;
access_dev = READ_ONLY;
};
};
reg {
......
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