Commit da5ed0eb authored by Dimitris Lampridis's avatar Dimitris Lampridis

Repository cleanup and restructuring.

parent 6848b9b4

Too many changes to show.

To preserve performance only 1000 of 1000+ files are displayed.

--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Offset and gain correction
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: offset_gain_corr (offset_gain_corr.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 24-11-2011
--
-- version: 1.0
--
-- description: Offset and gain correction with saturation.
-- Latency = 2
--
-- ___ ___ ________
-- | | offset_data | | product | |
-- data_i ---->| + |------------>| X |-------->|saturate|--> data_o
-- |___| |___| |________|
-- ^ ^
-- | |
-- offset_i gain_i
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
------------------------------------------------------------------------------
-- Entity declaration
------------------------------------------------------------------------------
entity offset_gain is
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(16 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
data_i : in std_logic_vector(15 downto 0); --! Unsigned data input
data_o : out std_logic_vector(15 downto 0) --! Unsigned data output
);
end entity offset_gain;
------------------------------------------------------------------------------
-- Architecture declaration
------------------------------------------------------------------------------
architecture rtl of offset_gain is
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal rst : std_logic := '0';
signal data_offset : std_logic_vector(17 downto 0) := (others => '0');
signal gain : std_logic_vector(17 downto 0) := (others => '0');
signal product : std_logic_vector(35 downto 0) := (others => '0');
begin
------------------------------------------------------------------------------
-- Active high reset for MULT_MACRO
------------------------------------------------------------------------------
rst <= not(rst_n_i);
------------------------------------------------------------------------------
-- Add offset to input data
------------------------------------------------------------------------------
p_offset : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
data_offset <= (others => '0');
gain <= (others => '0');
else
-- propagate sign for signed offset_i
data_offset <= std_logic_vector(unsigned(("00" & data_i)) +
unsigned((offset_i(16) & offset_i)));
gain <= "00" & gain_i;
end if;
end if;
end process p_offset;
------------------------------------------------------------------------------
-- Multiple input data + offset by gain
------------------------------------------------------------------------------
-- MULT_MACRO: Multiply Function implemented in a DSP48E
-- Xilinx HDL Libraries Guide, version 12.4
------------------------------------------------------------------------------
cmp_multiplier : MULT_MACRO
generic map (
DEVICE => "SPARTAN6", -- Target Device: "VIRTEX5", "VIRTEX6", "SPARTAN6"
LATENCY => 0, -- Desired clock cycle latency, 0-4
WIDTH_A => 18, -- Multiplier A-input bus width, 1-25
WIDTH_B => 18) -- Multiplier B-input bus width, 1-18
port map (
P => product, -- Multiplier ouput, WIDTH_A+WIDTH_B
A => gain, -- Multiplier input A, WIDTH_A
B => data_offset, -- Multiplier input B, WIDTH_B
CE => '1', -- 1-bit active high input clock enable
CLK => clk_i, -- 1-bit positive edge clock input
RST => rst -- 1-bit input active high reset
);
------------------------------------------------------------------------------
-- Saturate addition and multiplication result
------------------------------------------------------------------------------
p_saturate : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
data_o <= (others => '0');
else
if product(34) = '1' then
data_o <= (others => '0'); -- saturate negative
elsif (product(34) = '0' and product(31) = '1') then
data_o <= (others => '1'); -- saturate positive
else
data_o <= product(30 downto 15);
end if;
end if;
end if;
end process p_saturate;
end architecture rtl;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:48:27 02/05/2010
-- Design Name:
-- Module Name: offset_gain_s_tb.vhd
-- Project Name:
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: offsetgain
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity offset_gain_s_tb is
end offset_gain_s_tb;
architecture behavior of offset_gain_s_tb is
-- Component Declaration for the Unit Under Test (UUT)
component offset_gain_s
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(15 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
data_i : in std_logic_vector(15 downto 0); --! Unsigned data input
data_o : out std_logic_vector(15 downto 0) --! Unsigned data output
);
end component offset_gain_s;
--Inputs
signal rst_n_i : std_logic := '0';
signal clk_i : std_logic := '0';
signal offset_i : std_logic_vector(15 downto 0) := (others => '0');
signal gain_i : std_logic_vector(15 downto 0) := (others => '0');
signal data_i : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal data_o : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_i_period : time := 8 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : offset_gain_s port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
offset_i => offset_i,
gain_i => gain_i,
data_i => data_i,
data_o => data_o
);
-- Clock process definitions
clk_i_process : process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state
rst_n_i <= '0';
wait for 10 us;
rst_n_i <= '1';
wait for clk_i_period*10;
-- insert stimulus here
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(1000, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(32700, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-1000, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(-32700, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10000, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(32700, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10000, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(-32700, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(0, 16));
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16)); -- gain = 1
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(49152, 16)); -- gain = 1.5
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 16));
gain_i <= std_logic_vector(to_unsigned(16384, 16)); -- gain = 0.5
data_i <= std_logic_vector(to_signed(-1000, 16));
wait for 1 us;
wait;
end process;
end;
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:48:27 02/05/2010
-- Design Name:
-- Module Name: C:/mcattin/fpga_design/cvorb_cvorg/sources/offsetgain_tb.vhd
-- Project Name: cvorg_v3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: offsetgain
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity offsetgain_tb is
end offsetgain_tb;
architecture behavior of offsetgain_tb is
-- Component Declaration for the Unit Under Test (UUT)
component offset_gain
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
offset_i : in std_logic_vector(16 downto 0); --! Signed offset input (two's complement)
gain_i : in std_logic_vector(15 downto 0); --! Unsigned gain input
data_i : in std_logic_vector(15 downto 0); --! Unsigned data input
data_o : out std_logic_vector(15 downto 0) --! Unsigned data output
);
end component offset_gain;
--Inputs
signal rst_n_i : std_logic := '0';
signal clk_i : std_logic := '0';
signal offset_i : std_logic_vector(16 downto 0) := (others => '0');
signal gain_i : std_logic_vector(15 downto 0) := (others => '0');
signal data_i : std_logic_vector(15 downto 0) := (others => '0');
--Outputs
signal data_o : std_logic_vector(15 downto 0);
-- Clock period definitions
constant clk_i_period : time := 8 ns;
begin
-- Instantiate the Unit Under Test (UUT)
uut : offset_gain port map (
rst_n_i => rst_n_i,
clk_i => clk_i,
offset_i => offset_i,
gain_i => gain_i,
data_i => data_i,
data_o => data_o
);
-- Clock process definitions
clk_i_process : process
begin
clk_i <= '0';
wait for clk_i_period/2;
clk_i <= '1';
wait for clk_i_period/2;
end process;
-- Stimulus process
stim_proc : process
begin
-- hold reset state
rst_n_i <= '0';
wait for 10 us;
rst_n_i <= '1';
wait for clk_i_period*10;
-- insert stimulus here
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
data_i <= std_logic_vector(to_unsigned(1, 16));
wait for 1 us;
wait until rising_edge(clk_i);
data_i <= std_logic_vector(to_unsigned(3, 16));
wait for 1 us;
wait until rising_edge(clk_i);
data_i <= std_logic_vector(to_unsigned(32768, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(65535, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-10, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(10, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 17));
gain_i <= std_logic_vector(to_unsigned(32000, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 17));
gain_i <= std_logic_vector(to_unsigned(34000, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(32768, 17));
gain_i <= std_logic_vector(to_unsigned(32768, 16));
data_i <= std_logic_vector(to_unsigned(32768, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-32768, 17));
gain_i <= std_logic_vector(to_unsigned(33768, 16));
data_i <= std_logic_vector(to_unsigned(0, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(-298, 17));
gain_i <= std_logic_vector(to_unsigned(32090, 16));
data_i <= std_logic_vector(to_unsigned(60857, 16));
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= std_logic_vector(to_signed(0, 17));
gain_i <= std_logic_vector(to_unsigned(16384, 16));
data_i <= std_logic_vector(to_unsigned(1000, 16));
wait for 1 us;
wait until rising_edge(clk_i);
-- offset_i <= "010000000000000";
offset_i <= "01111111111111111";
gain_i <= X"8000";
data_i <= (others => '1');
wait for 1 us;
wait until rising_edge(clk_i);
offset_i <= "10000000000000000";
-- offset_i <= "011111111111111";
gain_i <= X"8000";
data_i <= (others => '0');
wait;
end process;
end;
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Variable saturation, signed data input and output (two's complement)
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: var_sat_s (var_sat_s.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 14-03-2013
--
-- version: 1.0
--
-- description: Variable saturation.
-- Latency = 1
--
-- ________
-- | |
-- data_i ---->|saturate|--> data_o
-- |________|
-- ^
-- |
-- sat_i
--
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
------------------------------------------------------------------------------
-- Entity declaration
------------------------------------------------------------------------------
entity var_sat_s is
port (
rst_n_i : in std_logic; --! Reset (active low)
clk_i : in std_logic; --! Clock
sat_i : in std_logic_vector(14 downto 0); --! Unsigned saturation value input
data_i : in std_logic_vector(15 downto 0); --! Signed data input (two's complement)
data_o : out std_logic_vector(15 downto 0) --! Signed data output (two's complement)
);
end entity var_sat_s;
------------------------------------------------------------------------------
-- Architecture declaration
------------------------------------------------------------------------------
architecture rtl of var_sat_s is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
constant c_one : signed(15 downto 0) := X"0001";
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal pos_sat : signed(15 downto 0);
signal neg_sat : signed(15 downto 0);
begin
pos_sat <= signed('0' & sat_i);
neg_sat <= signed(not('0' & sat_i))+c_one;
------------------------------------------------------------------------------
-- Saturate
------------------------------------------------------------------------------
p_saturate : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
data_o <= (others => '0');
elsif signed(data_i) >= pos_sat then
data_o <= std_logic_vector(pos_sat); -- saturate positive
elsif signed(data_i) <= neg_sat then
data_o <= std_logic_vector(neg_sat); -- saturate negative
else
data_o <= data_i;
end if;
end if;
end process p_saturate;
end architecture rtl;
#
# Mezzanine top level pin assignment file:
# syntax: pin FMC_pin_name Core_Pin_name IO_Standard
# % is replaced with FMC number if the carrier supports more than 1 mezzanine
#
mezzanine fmc-adc-v5
pin la_n17 adc%_ext_trigger_n_i lvds_25
pin la_p17 adc%_ext_trigger_p_i lvds_25
pin la_n0 adc%_dco_n_i lvds_25
pin la_p0 adc%_dco_p_i lvds_25
pin la_n1 adc%_fr_n_i lvds_25
pin la_p1 adc%_fr_p_i lvds_25
pin la_n14 adc%_outa_n_i[0] lvds_25
pin la_p14 adc%_outa_p_i[0] lvds_25
pin la_n15 adc%_outb_n_i[0] lvds_25
pin la_p15 adc%_outb_p_i[0] lvds_25
pin la_n16 adc%_outa_n_i[1] lvds_25
pin la_p16 adc%_outa_p_i[1] lvds_25
pin la_n13 adc%_outb_n_i[1] lvds_25
pin la_p13 adc%_outb_p_i[1] lvds_25
pin la_n10 adc%_outa_n_i[2] lvds_25
pin la_p10 adc%_outa_p_i[2] lvds_25
pin la_n9 adc%_outb_n_i[2] lvds_25
pin la_p9 adc%_outb_p_i[2] lvds_25
pin la_n7 adc%_outa_n_i[3] lvds_25
pin la_p7 adc%_outa_p_i[3] lvds_25
pin la_n5 adc%_outb_n_i[3] lvds_25
pin la_p5 adc%_outb_p_i[3] lvds_25
pin la_p25 adc%_spi_din_i lvcmos25
pin la_n31 adc%_spi_dout_o lvcmos25
pin la_p31 adc%_spi_sck_o lvcmos25
pin la_p30 adc%_spi_cs_adc_n_o lvcmos25
pin la_p32 adc%_spi_cs_dac1_n_o lvcmos25
pin la_n32 adc%_spi_cs_dac2_n_o lvcmos25
pin la_p33 adc%_spi_cs_dac3_n_o lvcmos25
pin la_n33 adc%_spi_cs_dac4_n_o lvcmos25
pin la_n30 adc%_gpio_dac_clr_n_o lvcmos25
pin la_n28 adc%_gpio_led_acq_o lvcmos25
pin la_p28 adc%_gpio_led_trig_o lvcmos25
pin la_p26 adc%_gpio_ssr_ch1_o[0] lvcmos25
pin la_n26 adc%_gpio_ssr_ch1_o[1] lvcmos25
pin la_n27 adc%_gpio_ssr_ch1_o[2] lvcmos25
pin la_n25 adc%_gpio_ssr_ch1_o[3] lvcmos25
pin la_p24 adc%_gpio_ssr_ch1_o[4] lvcmos25
pin la_n24 adc%_gpio_ssr_ch1_o[5] lvcmos25
pin la_p29 adc%_gpio_ssr_ch1_o[6] lvcmos25
pin la_p20 adc%_gpio_ssr_ch2_o[0] lvcmos25
pin la_n19 adc%_gpio_ssr_ch2_o[1] lvcmos25
pin la_p22 adc%_gpio_ssr_ch2_o[2] lvcmos25
pin la_n22 adc%_gpio_ssr_ch2_o[3] lvcmos25
pin la_p21 adc%_gpio_ssr_ch2_o[4] lvcmos25
pin la_p27 adc%_gpio_ssr_ch2_o[5] lvcmos25
pin la_n21 adc%_gpio_ssr_ch2_o[6] lvcmos25
pin la_p8 adc%_gpio_ssr_ch3_o[0] lvcmos25
pin la_n8 adc%_gpio_ssr_ch3_o[1] lvcmos25
pin la_p12 adc%_gpio_ssr_ch3_o[2] lvcmos25
pin la_n12 adc%_gpio_ssr_ch3_o[3] lvcmos25
pin la_p11 adc%_gpio_ssr_ch3_o[4] lvcmos25
pin la_n11 adc%_gpio_ssr_ch3_o[5] lvcmos25
pin la_n20 adc%_gpio_ssr_ch3_o[6] lvcmos25
pin la_p2 adc%_gpio_ssr_ch4_o[0] lvcmos25
pin la_n2 adc%_gpio_ssr_ch4_o[1] lvcmos25
pin la_p3 adc%_gpio_ssr_ch4_o[2] lvcmos25
pin la_n3 adc%_gpio_ssr_ch4_o[3] lvcmos25
pin la_p4 adc%_gpio_ssr_ch4_o[4] lvcmos25
pin la_p6 adc%_gpio_ssr_ch4_o[5] lvcmos25
pin la_n4 adc%_gpio_ssr_ch4_o[6] lvcmos25
pin la_n6 adc%_gpio_si570_oe_o lvcmos25
pin la_n18 adc%_si570_scl_b lvcmos25
pin la_p18 adc%_si570_sda_b lvcmos25
pin la_n29 adc%_one_wire_b lvcmos25
#eof
ddr3-sp6-core @ 94a664ed
Subproject commit 503171933f184ae878836f28e67a78a7c81b4325
Subproject commit 94a664ed3906079bf5a645a4a0face78d03839b9
general-cores @ 1a0f59f3
Subproject commit ea05c88360e5cb82450aa9205db655876d8aa4db
Subproject commit 1a0f59f38dab795352f2f0093cec7bd81f465769
gn4124-core @ 5066970c
Subproject commit e7cd73db41ba056ed4b27731c21a3b2aa53eaa51
Subproject commit 5066970c44f5031e2c74e55ba54bf0e9ee3dc82f
......@@ -7,7 +7,11 @@ files = [
"fmc_adc_100Ms_csr_wbgen2_pkg.vhd",
"fmc_adc_eic.vhd",
"offset_gain_s.vhd",
"var_sat_s.vhd"]
]
modules = { "local" : [ "timetag_core/rtl",
"../../ip_cores/adc-serdes-core" ] }
modules = {
"local" : [
"timetag_core",
"../ip_cores/adc-serdes-core",
],
}
......@@ -40,8 +40,7 @@ use work.fmc_adc_100Ms_csr_wbgen2_pkg.all;
entity fmc_adc_100Ms_core is
generic(
g_multishot_ram_size : natural := 2048;
g_carrier_type : string := "SPEC"
g_multishot_ram_size : natural := 2048
);
port (
-- Clock, reset
......@@ -509,23 +508,6 @@ begin
end if;
end process p_fs_freq;
--gen_fb_clk_check : if (g_carrier_type /= "SPEC" and
-- g_carrier_type /= "SVEC") generate
-- assert false report "[fmc_adc_100Ms_core] Selected carrier type not supported. Must be SPEC or SVEC." severity failure;
--end generate gen_fb_clk_check;
--gen_fb_clk_spec : if g_carrier_type = "SPEC" generate
-- cmp_fb_clk_buf : BUFG
-- port map (
-- O => clk_fb,
-- I => clk_fb_buf
-- );
--end generate gen_fb_clk_spec;
--gen_fb_clk_svec : if g_carrier_type = "SVEC" generate
-- clk_fb <= clk_fb_buf;
--end generate gen_fb_clk_svec;
------------------------------------------------------------------------------
-- ADC data and frame SerDes
------------------------------------------------------------------------------
......
......@@ -9,7 +9,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2012-11-16
-- Last update: 2018-01-24
-- Last update: 2018-10-26
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for FMC ADC 100Ms/s core.
......@@ -51,8 +51,7 @@ package fmc_adc_100Ms_core_pkg is
------------------------------------------------------------------------------
component fmc_adc_100Ms_core
generic(
g_multishot_ram_size : natural := 2048;
g_carrier_type : string := "SPEC"
g_multishot_ram_size : natural := 2048
);
port (
-- Clock, reset
......
......@@ -39,8 +39,7 @@ use work.timetag_core_pkg.all;
entity fmc_adc_mezzanine is
generic(
g_multishot_ram_size : natural := 2048;
g_carrier_type : string := "SPEC"
g_multishot_ram_size : natural := 2048
);
port (
-- Clock, reset
......@@ -452,9 +451,8 @@ begin
------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
generic map (
g_multishot_ram_size => g_multishot_ram_size,
g_carrier_type => g_carrier_type
)
g_multishot_ram_size => g_multishot_ram_size
)
port map(
sys_clk_i => sys_clk_i,
sys_rst_n_i => sys_rst_n_i,
......
......@@ -8,7 +8,7 @@
-- Dimitrios Lampridis <dimitrios.lampridis@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2013-07-03
-- Last update: 2016-06-28
-- Last update: 2018-10-26
-- Standard : VHDL'93/02
-------------------------------------------------------------------------------
-- Description: Package for FMC ADC mezzanine
......@@ -50,9 +50,8 @@ package fmc_adc_mezzanine_pkg is
------------------------------------------------------------------------------
component fmc_adc_mezzanine
generic(
g_multishot_ram_size : natural := 2048;
g_carrier_type : string := "SPEC"
);
g_multishot_ram_size : natural := 2048
);
port (
-- Clock, reset
sys_clk_i : in std_logic;
......
......@@ -2,4 +2,5 @@ files = [
"timetag_core_regs.vhd",
"timetag_core_regs_wbgen2_pkg.vhd",
"timetag_core.vhd",
"timetag_core_pkg.vhd"]
"timetag_core_pkg.vhd",
]
WBGEN2=$(shell which wbgen2)
RTL=../rtl/
TEX=../../../../../doc/manual/
RTL=../
TEX=../../../../doc/manual/
timetag_core_regs:
$(WBGEN2) -l vhdl -H record -V $(RTL)$@.vhd -p $(RTL)$@_wbgen2_pkg.vhd -f html -D $@.htm -C $@.h $@.wb
......
WBGEN2=$(shell which wbgen2)
RTL=../rtl/
SIM=../../spec/testbench/include/
RTL=../
SIM=../../testbench/include/
TEX=../../../doc/manual/
all: fmc_adc_100Ms_csr fmc_adc_eic
......
This diff is collapsed.
This source diff could not be displayed because it is too large. You can view the blob instead.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment