Commit e2180fcb authored by Dimitris Lampridis's avatar Dimitris Lampridis

hdl+doc: replace all instances of 'decimation' with 'under-sampling', closes issue #1290

parent e349ef45
......@@ -356,13 +356,13 @@ Sampling clock frequency
@headitem Bits @tab Access @tab Prefix @tab Default @tab Name
@item @code{31...0}
@tab R/W @tab
@code{DECI}
@code{UNDERSAMPLE}
@tab @code{0} @tab
Sample rate decimation
Undersampling ratio
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{deci} @tab Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).
@item @code{undersample} @tab Undersampling ratio. Takes one sample every N samples and discards the others (N = undersampling ratio).
@end multitable
@regsection @code{pre_samples} - Pre-trigger samples
@multitable @columnfractions .10 .10 .15 .10 .55
......@@ -674,5 +674,5 @@ Multi-shot sample depth
@end multitable
@multitable @columnfractions 0.15 0.85
@headitem Field @tab Description
@item @code{multi_depth} @tab Maximum sample depth allowed in multi-shot acquisition mode
@item @code{multi_depth} @tab Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag
@end multitable
......@@ -188,7 +188,7 @@ architecture rtl of fmc_adc_100Ms_core is
fmc_adc_core_shots_cnt_val_i : in std_logic_vector(15 downto 0);
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
fmc_adc_core_fs_freq_i : in std_logic_vector(31 downto 0);
fmc_adc_core_sr_deci_o : out std_logic_vector(31 downto 0);
fmc_adc_core_sr_undersample_o : out std_logic_vector(31 downto 0);
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_post_samples_o : out std_logic_vector(31 downto 0);
fmc_adc_core_samples_cnt_i : in std_logic_vector(31 downto 0);
......@@ -347,10 +347,10 @@ architecture rtl of fmc_adc_100Ms_core is
signal int_trig_over_thres_filt_tst : std_logic_vector(15 downto 0);
signal trig_tst : std_logic_vector(15 downto 0);
-- Decimation
signal decim_factor : std_logic_vector(31 downto 0);
signal decim_cnt : unsigned(31 downto 0);
signal decim_en : std_logic;
-- Under-sampling
signal undersample_factor : std_logic_vector(31 downto 0);
signal undersample_cnt : unsigned(31 downto 0);
signal undersample_en : std_logic;
-- Sync FIFO (from fs_clk to sys_clk_i)
signal sync_fifo_din : std_logic_vector(64 downto 0);
......@@ -765,7 +765,7 @@ begin
fmc_adc_core_shots_cnt_val_i => remaining_shots,
fmc_adc_core_trig_pos_i => trig_addr,
fmc_adc_core_fs_freq_i => fs_freq,
fmc_adc_core_sr_deci_o => decim_factor,
fmc_adc_core_sr_undersample_o => undersample_factor,
fmc_adc_core_pre_samples_o => pre_trig_value,
fmc_adc_core_post_samples_o => post_trig_value,
fmc_adc_core_samples_cnt_i => std_logic_vector(samples_cnt),
......@@ -936,27 +936,27 @@ begin
end process p_trig_delay;
------------------------------------------------------------------------------
-- Samples decimation and trigger alignment
-- When the decimantion is enabled, if the trigger occurs between two
-- Under-sampling and trigger alignment
-- When under-sampling is enabled, if the trigger occurs between two
-- samples it will be realigned to the next sample
------------------------------------------------------------------------------
p_deci_cnt : process (fs_clk, fs_rst_n)
p_undersample_cnt : process (fs_clk, fs_rst_n)
begin
if fs_rst_n = '0' then
decim_cnt <= to_unsigned(1, decim_cnt'length);
decim_en <= '0';
undersample_cnt <= to_unsigned(1, undersample_cnt'length);
undersample_en <= '0';
elsif rising_edge(fs_clk) then
if decim_cnt = to_unsigned(0, decim_cnt'length) then
if decim_factor /= X"00000000" then
decim_cnt <= unsigned(decim_factor) - 1;
if undersample_cnt = to_unsigned(0, undersample_cnt'length) then
if undersample_factor /= X"00000000" then
undersample_cnt <= unsigned(undersample_factor) - 1;
end if;
decim_en <= '1';
undersample_en <= '1';
else
decim_cnt <= decim_cnt - 1;
decim_en <= '0';
undersample_cnt <= undersample_cnt - 1;
undersample_en <= '0';
end if;
end if;
end process p_deci_cnt;
end process p_undersample_cnt;
p_trig_align : process (fs_clk, fs_rst_n)
begin
......@@ -965,7 +965,7 @@ begin
elsif rising_edge(fs_clk) then
if trig_d = '1' then
trig_align <= '1';
elsif decim_en = '1' then
elsif undersample_en = '1' then
trig_align <= '0';
end if;
end if;
......@@ -1053,7 +1053,7 @@ begin
-- "000000000000000" & serdes_synced &
-- "00000000" & serdes_out_fr;
sync_fifo_wr <= decim_en and serdes_synced and not(sync_fifo_full);
sync_fifo_wr <= undersample_en and serdes_synced and not(sync_fifo_full);
sync_fifo_rd <= not(sync_fifo_empty); -- read sync fifo as soon as data are available
......
......@@ -3,7 +3,7 @@
---------------------------------------------------------------------------------------
-- File : ../rtl/fmc_adc_100Ms_csr.vhd
-- Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
-- Created : Thu Mar 17 13:38:44 2016
-- Created : Mon Apr 18 16:09:20 2016
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -82,8 +82,8 @@ entity fmc_adc_100Ms_csr is
fmc_adc_core_trig_pos_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sampling clock frequency' in reg: 'Sampling clock frequency'
fmc_adc_core_fs_freq_i : in std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Sample rate decimation' in reg: 'Sample rate'
fmc_adc_core_sr_deci_o : out std_logic_vector(31 downto 0);
-- Port for asynchronous (clock: fs_clk_i) std_logic_vector field: 'Undersampling ratio' in reg: 'Sample rate'
fmc_adc_core_sr_undersample_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Pre-trigger samples' in reg: 'Pre-trigger samples'
fmc_adc_core_pre_samples_o : out std_logic_vector(31 downto 0);
-- Port for std_logic_vector field: 'Post-trigger samples' in reg: 'Post-trigger samples'
......@@ -195,12 +195,12 @@ signal fmc_adc_core_fs_freq_lwb_in_progress : std_logic ;
signal fmc_adc_core_fs_freq_lwb_s0 : std_logic ;
signal fmc_adc_core_fs_freq_lwb_s1 : std_logic ;
signal fmc_adc_core_fs_freq_lwb_s2 : std_logic ;
signal fmc_adc_core_sr_deci_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_sr_deci_swb : std_logic ;
signal fmc_adc_core_sr_deci_swb_delay : std_logic ;
signal fmc_adc_core_sr_deci_swb_s0 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s1 : std_logic ;
signal fmc_adc_core_sr_deci_swb_s2 : std_logic ;
signal fmc_adc_core_sr_undersample_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_sr_undersample_swb : std_logic ;
signal fmc_adc_core_sr_undersample_swb_delay : std_logic ;
signal fmc_adc_core_sr_undersample_swb_s0 : std_logic ;
signal fmc_adc_core_sr_undersample_swb_s1 : std_logic ;
signal fmc_adc_core_sr_undersample_swb_s2 : std_logic ;
signal fmc_adc_core_pre_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_post_samples_int : std_logic_vector(31 downto 0);
signal fmc_adc_core_ch1_ctl_ssr_int : std_logic_vector(6 downto 0);
......@@ -304,9 +304,9 @@ begin
fmc_adc_core_fs_freq_lwb <= '0';
fmc_adc_core_fs_freq_lwb_delay <= '0';
fmc_adc_core_fs_freq_lwb_in_progress <= '0';
fmc_adc_core_sr_deci_int <= "00000000000000000000000000000000";
fmc_adc_core_sr_deci_swb <= '0';
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_sr_undersample_int <= "00000000000000000000000000000000";
fmc_adc_core_sr_undersample_swb <= '0';
fmc_adc_core_sr_undersample_swb_delay <= '0';
fmc_adc_core_pre_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_post_samples_int <= "00000000000000000000000000000000";
fmc_adc_core_ch1_ctl_ssr_int <= "0000000";
......@@ -363,8 +363,8 @@ begin
rddata_reg(31 downto 0) <= fmc_adc_core_fs_freq_int;
fmc_adc_core_fs_freq_lwb_in_progress <= '0';
end if;
fmc_adc_core_sr_deci_swb <= fmc_adc_core_sr_deci_swb_delay;
fmc_adc_core_sr_deci_swb_delay <= '0';
fmc_adc_core_sr_undersample_swb <= fmc_adc_core_sr_undersample_swb_delay;
fmc_adc_core_sr_undersample_swb_delay <= '0';
fmc_adc_core_ch1_sta_val_lwb <= fmc_adc_core_ch1_sta_val_lwb_delay;
fmc_adc_core_ch1_sta_val_lwb_delay <= '0';
if ((ack_sreg(1) = '1') and (fmc_adc_core_ch1_sta_val_lwb_in_progress = '1')) then
......@@ -611,11 +611,11 @@ begin
ack_in_progress <= '1';
when "001001" =>
if (wb_we_i = '1') then
fmc_adc_core_sr_deci_int <= wrdata_reg(31 downto 0);
fmc_adc_core_sr_deci_swb <= '1';
fmc_adc_core_sr_deci_swb_delay <= '1';
fmc_adc_core_sr_undersample_int <= wrdata_reg(31 downto 0);
fmc_adc_core_sr_undersample_swb <= '1';
fmc_adc_core_sr_undersample_swb_delay <= '1';
end if;
rddata_reg(31 downto 0) <= fmc_adc_core_sr_deci_int;
rddata_reg(31 downto 0) <= fmc_adc_core_sr_undersample_int;
ack_sreg(3) <= '1';
ack_in_progress <= '1';
when "001010" =>
......@@ -1389,21 +1389,21 @@ begin
end process;
-- Sample rate decimation
-- asynchronous std_logic_vector register : Sample rate decimation (type RW/RO, fs_clk_i <-> clk_sys_i)
-- Undersampling ratio
-- asynchronous std_logic_vector register : Undersampling ratio (type RW/RO, fs_clk_i <-> clk_sys_i)
process (fs_clk_i, rst_n_i)
begin
if (rst_n_i = '0') then
fmc_adc_core_sr_deci_swb_s0 <= '0';
fmc_adc_core_sr_deci_swb_s1 <= '0';
fmc_adc_core_sr_deci_swb_s2 <= '0';
fmc_adc_core_sr_deci_o <= "00000000000000000000000000000000";
fmc_adc_core_sr_undersample_swb_s0 <= '0';
fmc_adc_core_sr_undersample_swb_s1 <= '0';
fmc_adc_core_sr_undersample_swb_s2 <= '0';
fmc_adc_core_sr_undersample_o <= "00000000000000000000000000000000";
elsif rising_edge(fs_clk_i) then
fmc_adc_core_sr_deci_swb_s0 <= fmc_adc_core_sr_deci_swb;
fmc_adc_core_sr_deci_swb_s1 <= fmc_adc_core_sr_deci_swb_s0;
fmc_adc_core_sr_deci_swb_s2 <= fmc_adc_core_sr_deci_swb_s1;
if ((fmc_adc_core_sr_deci_swb_s2 = '0') and (fmc_adc_core_sr_deci_swb_s1 = '1')) then
fmc_adc_core_sr_deci_o <= fmc_adc_core_sr_deci_int;
fmc_adc_core_sr_undersample_swb_s0 <= fmc_adc_core_sr_undersample_swb;
fmc_adc_core_sr_undersample_swb_s1 <= fmc_adc_core_sr_undersample_swb_s0;
fmc_adc_core_sr_undersample_swb_s2 <= fmc_adc_core_sr_undersample_swb_s1;
if ((fmc_adc_core_sr_undersample_swb_s2 = '0') and (fmc_adc_core_sr_undersample_swb_s1 = '1')) then
fmc_adc_core_sr_undersample_o <= fmc_adc_core_sr_undersample_int;
end if;
end if;
end process;
......
......@@ -3,7 +3,7 @@
* File : fmc_adc_100Ms_csr.h
* Author : auto-generated by wbgen2 from fmc_adc_100Ms_csr.wb
* Created : Thu Mar 17 13:38:44 2016
* Created : Mon Apr 18 16:09:20 2016
* Standard : ANSI C
THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE fmc_adc_100Ms_csr.wb
......@@ -138,11 +138,11 @@
/* definitions for register: Sample rate */
/* definitions for field: Sample rate decimation in reg: Sample rate */
#define FMC_ADC_CORE_SR_DECI_MASK WBGEN2_GEN_MASK(0, 32)
#define FMC_ADC_CORE_SR_DECI_SHIFT 0
#define FMC_ADC_CORE_SR_DECI_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define FMC_ADC_CORE_SR_DECI_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for field: Undersampling ratio in reg: Sample rate */
#define FMC_ADC_CORE_SR_UNDERSAMPLE_MASK WBGEN2_GEN_MASK(0, 32)
#define FMC_ADC_CORE_SR_UNDERSAMPLE_SHIFT 0
#define FMC_ADC_CORE_SR_UNDERSAMPLE_W(value) WBGEN2_GEN_WRITE(value, 0, 32)
#define FMC_ADC_CORE_SR_UNDERSAMPLE_R(reg) WBGEN2_GEN_READ(reg, 0, 32)
/* definitions for register: Pre-trigger samples */
......
......@@ -1479,7 +1479,7 @@ fmc_adc_core_fs_freq_i[31:0]
</td>
<td class="td_pblock_right">
fmc_adc_core_sr_deci_o[31:0]
fmc_adc_core_sr_undersample_o[31:0]
</td>
<td class="td_arrow_right">
&rArr;
......@@ -5166,7 +5166,7 @@ SR
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[31:24]
UNDERSAMPLE[31:24]
</td>
<td >
......@@ -5220,7 +5220,7 @@ DECI[31:24]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[23:16]
UNDERSAMPLE[23:16]
</td>
<td >
......@@ -5274,7 +5274,7 @@ DECI[23:16]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[15:8]
UNDERSAMPLE[15:8]
</td>
<td >
......@@ -5328,7 +5328,7 @@ DECI[15:8]
</tr>
<tr>
<td style="border: solid 1px black;" colspan=8 class="td_field">
DECI[7:0]
UNDERSAMPLE[7:0]
</td>
<td >
......@@ -5355,9 +5355,9 @@ DECI[7:0]
</table>
<ul>
<li><b>
DECI
</b>[<i>read/write</i>]: Sample rate decimation
<br>Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).
UNDERSAMPLE
</b>[<i>read/write</i>]: Undersampling ratio
<br>Undersampling ratio. Takes one sample every N samples and discards the others (N = undersampling ratio).
</ul>
<a name="PRE_SAMPLES"></a>
<h3><a name="sect_3_11">3.11. Pre-trigger samples</a></h3>
......@@ -11549,7 +11549,7 @@ MULTI_DEPTH[7:0]
<li><b>
MULTI_DEPTH
</b>[<i>read-only</i>]: Multi-shot sample depth
<br>Maximum sample depth allowed in multi-shot acquisition mode
<br>Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag
</ul>
......
......@@ -345,9 +345,9 @@ peripheral {
prefix = "sr";
field {
name = "Sample rate decimation";
description = "Decimation factor. Takes one sample every N samples and discards the others (N = decimation factor).";
prefix = "deci";
name = "Undersampling ratio";
description = "Undersampling ratio. Takes one sample every N samples and discards the others (N = undersampling ratio).";
prefix = "undersample";
type = SLV;
size = 32;
access_bus = READ_WRITE;
......@@ -928,7 +928,7 @@ peripheral {
field {
name = "Multi-shot sample depth";
description = "Maximum sample depth allowed in multi-shot acquisition mode";
description = "Maximum sample depth allowed in multi-shot acquisition mode, excluding two samples already reserved for time tag";
type = SLV;
size = 32;
access_bus = READ_ONLY;
......
......@@ -306,9 +306,9 @@ add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_delay_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_d
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/trig_align
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_factor
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/decim_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/undersample_factor
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/undersample_cnt
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/undersample_en
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_din
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_dout
add wave -noupdate -radix hexadecimal -group ADC /main/DUT/cmp_fmc_adc_mezzanine_0/cmp_fmc_adc_100Ms_core/sync_fifo_empty
......
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