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FMC ADC 100M 14b 4cha - Gateware
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FMC ADC 100M 14b 4cha - Gateware
Commits
e3d9d1cb
Commit
e3d9d1cb
authored
Jul 19, 2013
by
Matthieu Cattin
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coregen: Remove useless coregen files.
parent
77717e72
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4 changed files
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436 deletions
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-436
.lso
hdl/ip_cores/.lso
+0
-1
ngcbuild.xmsgs
hdl/ip_cores/_xmsgs/ngcbuild.xmsgs
+0
-9
pn_parser.xmsgs
hdl/ip_cores/_xmsgs/pn_parser.xmsgs
+0
-15
xst.xmsgs
hdl/ip_cores/_xmsgs/xst.xmsgs
+0
-411
No files found.
hdl/ip_cores/.lso
deleted
100644 → 0
View file @
77717e72
fifo_generator_v6_2
hdl/ip_cores/_xmsgs/ngcbuild.xmsgs
deleted
100644 → 0
View file @
77717e72
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>
hdl/ip_cores/_xmsgs/pn_parser.xmsgs
deleted
100644 → 0
View file @
77717e72
<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2010 Xilinx, Inc. All rights reserved. -->
<messages>
<msg
type=
"info"
file=
"ProjectMgmt"
num=
"1061"
><arg
fmt=
"%s"
index=
"1"
>
Parsing VHDL file
"
/home/mcattin/projects/fmc_adc_100Ms/hdl/spec/ip_cores/tmp/_cg/wb_ddr_fifo.vhd
"
into library work
</arg>
</msg>
</messages>
hdl/ip_cores/_xmsgs/xst.xmsgs
deleted
100644 → 0
View file @
77717e72
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