sim: Introduction of new, simpler testbench for FMC-ADC core, without any SPEC…

sim: Introduction of new, simpler testbench for FMC-ADC core, without any SPEC or SVEC specific details

sim: Introduction of new, simpler testbench for FMC-ADC core, without any SPEC…
sim: Introduction of new, simpler testbench for FMC-ADC core, without any SPEC or SVEC specific details
e7bcef61 · Dimitris Lampridis · da5ed0eb · e7bcef61 · e7bcef61 · e7bcef61
Commit e7bcef61 authored Oct 29, 2018 by Dimitris Lampridis
5 changed files
--- a/hdl/testbench/fmc_adc_mezzanine/.gitignore
+++ b/hdl/testbench/fmc_adc_mezzanine/.gitignore
+Makefile
+work/
+transcript
+vsim.wlf
+NullFile
+modelsim.ini
--- a/hdl/testbench/fmc_adc_mezzanine/Manifest.py
+++ b/hdl/testbench/fmc_adc_mezzanine/Manifest.py
+board      = "spec"
+sim_tool   = "modelsim"
+top_module = "main"
+action     = "simulation"
+target     = "xilinx"
+syn_device = "xc6slx45t"
+
+vcom_opt = "-93 -mixedsvvh"
+
+fetchto = "../../ip_cores"
+
+include_dirs = [
+    "../include",
+    fetchto + "/general-cores/sim/",
+]
+
+files = [
+    "main.sv",
+]
+
+modules = {
+    "local" : [
+        "../../rtl/",
+    ],
+    "git" : [
+        "git://ohwr.org/hdl-core-lib/general-cores.git",
+    ],
+}
+
+ctrls = [ "bank3_64b_32b" ]
--- a/hdl/testbench/fmc_adc_mezzanine/main.sv
+++ b/hdl/testbench/fmc_adc_mezzanine/main.sv
--- a/hdl/testbench/fmc_adc_mezzanine/run.do
+++ b/hdl/testbench/fmc_adc_mezzanine/run.do
+vsim -quiet -L unisim work.main
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+radix -hexadecimal
+
+log -r /*
+
+run -all
+
+wave zoomfull
--- a/hdl/testbench/fmc_adc_mezzanine/run_ci.do
+++ b/hdl/testbench/fmc_adc_mezzanine/run_ci.do
+vsim -quiet -L unisim work.main
+
+set StdArithNoWarnings 1
+set NumericStdNoWarnings 1
+
+run -all