Commit eb67f948 authored by Matthieu Cattin's avatar Matthieu Cattin

hdl: Change fifo and dpram from adc core to general-cores.

Was using custom coregen fifo and dpram.
parent 16d17ea6
This diff is collapsed.
...@@ -43,12 +43,15 @@ package fmc_adc_100Ms_core_pkg is ...@@ -43,12 +43,15 @@ package fmc_adc_100Ms_core_pkg is
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Constants declaration -- Constants declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
-- Components declaration -- Components declaration
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
component fmc_adc_100Ms_core component fmc_adc_100Ms_core
generic(
g_multishot_ram_size : natural := 2048
);
port ( port (
-- Clock, reset -- Clock, reset
sys_clk_i : in std_logic; sys_clk_i : in std_logic;
...@@ -109,6 +112,6 @@ end fmc_adc_100Ms_core_pkg; ...@@ -109,6 +112,6 @@ end fmc_adc_100Ms_core_pkg;
package body fmc_adc_100Ms_core_pkg is package body fmc_adc_100Ms_core_pkg is
end fmc_adc_100Ms_core_pkg; end fmc_adc_100Ms_core_pkg;
...@@ -1051,6 +1051,9 @@ begin ...@@ -1051,6 +1051,9 @@ begin
-- ADC core control and status -- ADC core control and status
------------------------------------------------------------------------------ ------------------------------------------------------------------------------
cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core cmp_fmc_adc_100Ms_core : fmc_adc_100Ms_core
generic map (
g_multishot_ram_size => 2048
)
port map( port map(
sys_clk_i => sys_clk_125, sys_clk_i => sys_clk_125,
sys_rst_n_i => sys_rst_n, sys_rst_n_i => sys_rst_n,
......
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