Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
F
FMC ADC 100M 14b 4cha - Gateware
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
8
Issues
8
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
FMC ADC 100M 14b 4cha - Gateware
Commits
f416ccd1
Commit
f416ccd1
authored
Nov 19, 2012
by
Matthieu Cattin
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Add a package for fmc_adc_100ms core.
parent
67d2154d
Show whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
114 additions
and
0 deletions
+114
-0
fmc_adc_100Ms_core_pkg.vhd
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
+114
-0
No files found.
hdl/adc/rtl/fmc_adc_100Ms_core_pkg.vhd
0 → 100644
View file @
f416ccd1
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: fmc_adc_100Ms_core_pkg (fmc_adc_100Ms_core_pkg.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 16-11-2012
--
-- version: 1.0
--
-- description: Package for FMC ADC 100Ms/s core
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library
IEEE
;
use
IEEE
.
STD_LOGIC_1164
.
all
;
use
IEEE
.
NUMERIC_STD
.
all
;
package
fmc_adc_100Ms_core_pkg
is
------------------------------------------------------------------------------
-- Constants declaration
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component
fmc_adc_100Ms_core
port
(
-- Clock, reset
sys_clk_i
:
in
std_logic
;
sys_rst_n_i
:
in
std_logic
;
-- CSR wishbone interface
wb_csr_adr_i
:
in
std_logic_vector
(
4
downto
0
);
wb_csr_dat_i
:
in
std_logic_vector
(
31
downto
0
);
wb_csr_dat_o
:
out
std_logic_vector
(
31
downto
0
);
wb_csr_cyc_i
:
in
std_logic
;
wb_csr_sel_i
:
in
std_logic_vector
(
3
downto
0
);
wb_csr_stb_i
:
in
std_logic
;
wb_csr_we_i
:
in
std_logic
;
wb_csr_ack_o
:
out
std_logic
;
-- DDR wishbone interface
wb_ddr_clk_i
:
in
std_logic
;
wb_ddr_adr_o
:
out
std_logic_vector
(
31
downto
0
);
wb_ddr_dat_o
:
out
std_logic_vector
(
63
downto
0
);
wb_ddr_sel_o
:
out
std_logic_vector
(
7
downto
0
);
wb_ddr_stb_o
:
out
std_logic
;
wb_ddr_we_o
:
out
std_logic
;
wb_ddr_cyc_o
:
out
std_logic
;
wb_ddr_ack_i
:
in
std_logic
;
wb_ddr_stall_i
:
in
std_logic
;
-- Events output pulses
trigger_p_o
:
out
std_logic
;
acq_start_p_o
:
out
std_logic
;
acq_stop_p_o
:
out
std_logic
;
acq_end_p_o
:
out
std_logic
;
-- FMC interface
ext_trigger_p_i
:
in
std_logic
;
-- External trigger
ext_trigger_n_i
:
in
std_logic
;
adc_dco_p_i
:
in
std_logic
;
-- ADC data clock
adc_dco_n_i
:
in
std_logic
;
adc_fr_p_i
:
in
std_logic
;
-- ADC frame start
adc_fr_n_i
:
in
std_logic
;
adc_outa_p_i
:
in
std_logic_vector
(
3
downto
0
);
-- ADC serial data (odd bits)
adc_outa_n_i
:
in
std_logic_vector
(
3
downto
0
);
adc_outb_p_i
:
in
std_logic_vector
(
3
downto
0
);
-- ADC serial data (even bits)
adc_outb_n_i
:
in
std_logic_vector
(
3
downto
0
);
gpio_dac_clr_n_o
:
out
std_logic
;
-- offset DACs clear (active low)
gpio_led_acq_o
:
out
std_logic
;
-- Mezzanine front panel power LED (PWR)
gpio_led_trig_o
:
out
std_logic
;
-- Mezzanine front panel trigger LED (TRIG)
gpio_ssr_ch1_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 1 solid state relays control
gpio_ssr_ch2_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 2 solid state relays control
gpio_ssr_ch3_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 3 solid state relays control
gpio_ssr_ch4_o
:
out
std_logic_vector
(
6
downto
0
);
-- Channel 4 solid state relays control
gpio_si570_oe_o
:
out
std_logic
-- Si570 (programmable oscillator) output enable
);
end
component
fmc_adc_100Ms_core
;
end
fmc_adc_100Ms_core_pkg
;
package
body
fmc_adc_100Ms_core_pkg
is
end
fmc_adc_100Ms_core_pkg
;
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment