hdl: expose acq config status bit

f98f833b · Dimitris Lampridis · 1ecef9a7 · f98f833b · f98f833b · f98f833b
Commit f98f833b authored Nov 14, 2018 by Dimitris Lampridis
4 changed files
--- a/hdl/rtl/fmc_adc_100Ms_core.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core.vhd
@@ -60,6 +60,9 @@ entity fmc_adc_100Ms_core is
    wb_ddr_master_i : in  t_wishbone_master_data64_in;
    wb_ddr_master_o : out t_wishbone_master_data64_out;

+    -- Acquisition configuration status flag
+    acq_cfg_ok_o : out std_logic;
+
    -- Events output pulses
    trigger_p_o   : out std_logic;
    acq_start_p_o : out std_logic;
@@ -1267,6 +1270,8 @@ begin
    end if;
  end process p_acq_cfg_ok;

+  acq_cfg_ok_o <= acq_config_ok;
+
  -- FSM transitions
  p_acq_fsm_transitions : process(sys_clk_i)
  begin

--- a/hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
+++ b/hdl/rtl/fmc_adc_100Ms_core_pkg.vhd
@@ -69,6 +69,9 @@ package fmc_adc_100Ms_core_pkg is
      wb_ddr_master_i : in  t_wishbone_master_data64_in;
      wb_ddr_master_o : out t_wishbone_master_data64_out;

+      -- Acquisition configuration status flag
+      acq_cfg_ok_o : out std_logic;
+
      -- Events output pulses
      trigger_p_o   : out std_logic;
      acq_start_p_o : out std_logic;

--- a/hdl/rtl/fmc_adc_mezzanine.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine.vhd
@@ -56,11 +56,12 @@ entity fmc_adc_mezzanine is
    wb_ddr_master_i : in  t_wishbone_master_data64_in;
    wb_ddr_master_o : out t_wishbone_master_data64_out;

-    -- Interrupts
+    -- Interrupts and status
    ddr_wr_fifo_empty_i : in  std_logic;
    trig_irq_o          : out std_logic;
    acq_end_irq_o       : out std_logic;
    eic_irq_o           : out std_logic;
+    acq_cfg_ok_o        : out std_logic;

    -- FMC interface
    ext_trigger_p_i : in std_logic;               -- External trigger
@@ -413,6 +414,8 @@ begin
      wb_ddr_master_o => wb_ddr_master_o,
      wb_ddr_master_i => wb_ddr_master_i,

+      acq_cfg_ok_o => acq_cfg_ok_o,
+
      trigger_p_o   => trigger_p,
      acq_start_p_o => acq_start_p,
      acq_stop_p_o  => acq_stop_p,

--- a/hdl/rtl/fmc_adc_mezzanine_pkg.vhd
+++ b/hdl/rtl/fmc_adc_mezzanine_pkg.vhd
@@ -61,11 +61,12 @@ package fmc_adc_mezzanine_pkg is
      wb_ddr_master_i : in  t_wishbone_master_data64_in;
      wb_ddr_master_o : out t_wishbone_master_data64_out;

-      -- Interrupt
+      -- Interrupt and status
      ddr_wr_fifo_empty_i : in  std_logic;
      trig_irq_o          : out std_logic;
      acq_end_irq_o       : out std_logic;
      eic_irq_o           : out std_logic;
+      acq_cfg_ok_o        : out std_logic;

      -- FMC interface
      ext_trigger_p_i : in std_logic;             -- External trigger