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FMC ADC 100M 14b 4cha - Gateware
Commit feba6ffa authored by tstana's avatar tstana
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Added the *play* project, as a reference project to the hdlmake tutorial, as… 

Added the *play* project, as a reference project to the hdlmake tutorial, as well as an exampleof accessing SPEC registers via the *rawrabbit* driver.

git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@131 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
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play/hdl/design/addr_dec.vhd 0 → 100644
View file @ feba6ffa
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: Address decoder (addr_dec.vhd)
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2011-09-21
--
-- version: 1.0
--
-- description: Top entity for LED control project
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--=============================================================================
-- Entity declaration for address decoder
--=============================================================================
entity addr_dec is
port (
-- Input signals
cyc_i : in std_logic;
adr_i : in std_logic;
dat_i : in std_logic_vector(63 downto 0);
ack_i : in std_logic_vector(1 downto 0);
-- Output signals
cyc_o : out std_logic_vector(1 downto 0);
ack_o : out std_logic;
dat_o : out std_logic_vector(31 downto 0)
);
end entity;
--=============================================================================
--=============================================================================
-- Architecture declaration for address decoder
--=============================================================================
architecture behavioral of addr_dec is
--=============================================================================
-- architecture begin
--=============================================================================
begin
cyc_o(0) <= cyc_i when (adr_i = '0') else '0';
cyc_o(1) <= cyc_i when (adr_i = '1') else '0';
-- cyc_o(to_integer(unsigned(adr_i))) <= cyc_i;
ack_o <= ack_i(0) when (adr_i = '0') else
ack_i(1); --(to_integer(unsigned(adr_i));
dat_o <= dat_i(31 downto 0) when (adr_i = '0') else
dat_i(63 downto 32);
end architecture;
--=============================================================================
-- architecture end
--=============================================================================
play/hdl/design/clk_div.vhd 0 → 100644
View file @ feba6ffa
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:43:07 09/11/2012
-- Design Name:
-- Module Name: clk_div - behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity clk_div is
-- generic
-- (
-- g_DIV_RATE : integer := 1
-- );
Port
(
clk_i : in STD_LOGIC;
reset_i : in std_logic;
clk_o : out STD_LOGIC
);
end clk_div;
architecture behavioral of clk_div is
signal s_div_cnt : std_logic_vector(32 downto 0) := (others => '0');
--signal s_clk_o :
begin
clk_o <= s_div_cnt(23);
p_div_count: process (reset_i, clk_i)
begin
if (reset_i = '1') then
s_div_cnt <= (others => '0');
elsif rising_edge(clk_i) then
s_div_cnt <= s_div_cnt + 1;
end if;
end process p_div_count;
end behavioral;
play/hdl/design/irq_controller.vhd 0 → 100644
View file @ feba6ffa
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- IRQ controller
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: irq_controller (irq_controller.vhd)
--
-- author: Matthieu Cattin (matthieu.cattin@cern.ch)
--
-- date: 18-11-2011
--
-- version: 1.0
--
-- description:
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library UNISIM;
--use UNISIM.vcomponents.all;
entity irq_controller is
port (
-- Clock, reset
clk_i : in std_logic;
rst_n_i : in std_logic;
-- Interrupt sources input, must be 1 clk_i tick long
irq_src_p_i : in std_logic_vector(31 downto 0);
-- IRQ pulse output
irq_p_o : out std_logic;
-- Wishbone interface
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end irq_controller;
architecture rtl of irq_controller is
------------------------------------------------------------------------------
-- Components declaration
------------------------------------------------------------------------------
component irq_controller_regs
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_load_o : out std_logic;
irq_ctrl_src_o : out std_logic_vector(31 downto 0);
irq_ctrl_src_i : in std_logic_vector(31 downto 0);
irq_ctrl_src_load_o : out std_logic;
irq_ctrl_en_mask_o : out std_logic_vector(31 downto 0)
);
end component irq_controller_regs;
------------------------------------------------------------------------------
-- Signals declaration
------------------------------------------------------------------------------
signal irq_en_mask : std_logic_vector(31 downto 0);
signal irq_pending : std_logic_vector(31 downto 0);
signal irq_pending_d : std_logic_vector(31 downto 0);
signal irq_pending_re : std_logic_vector(31 downto 0);
signal irq_src_rst : std_logic_vector(31 downto 0);
signal irq_src_rst_en : std_logic;
signal multi_irq : std_logic_vector(31 downto 0);
signal multi_irq_rst : std_logic_vector(31 downto 0);
signal multi_irq_rst_en : std_logic;
signal irq_p_or : std_logic_vector(32 downto 0);
begin
------------------------------------------------------------------------------
-- Wishbone interface to IRQ controller registers
------------------------------------------------------------------------------
cmp_irq_controller_regs : irq_controller_regs
port map(
rst_n_i => rst_n_i,
wb_clk_i => clk_i,
wb_addr_i => wb_adr_i,
wb_data_i => wb_dat_i,
wb_data_o => wb_dat_o,
wb_cyc_i => wb_cyc_i,
wb_sel_i => wb_sel_i,
wb_stb_i => wb_stb_i,
wb_we_i => wb_we_i,
wb_ack_o => wb_ack_o,
irq_ctrl_multi_irq_o => multi_irq_rst,
irq_ctrl_multi_irq_load_o => multi_irq_rst_en,
irq_ctrl_multi_irq_i => multi_irq,
irq_ctrl_src_o => irq_src_rst,
irq_ctrl_src_i => irq_pending,
irq_ctrl_src_load_o => irq_src_rst_en,
irq_ctrl_en_mask_o => irq_en_mask
);
------------------------------------------------------------------------------
-- Register interrupt sources
-- IRQ is pending until a '1' is written to the corresponding bit
------------------------------------------------------------------------------
p_irq_src : process (clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to irq_pending'length-1 loop
if rst_n_i = '0' then
irq_pending(I) <= '0';
elsif irq_src_p_i(I) = '1' then
irq_pending(I) <= '1';
elsif irq_src_rst_en = '1' and irq_src_rst(I) = '1' then
irq_pending(I) <= '0';
end if;
end loop; -- I
end if;
end process p_irq_src;
------------------------------------------------------------------------------
-- Multiple interrupt detection
-- Rise a flag if an interrupt occurs while an irq is still pending
-- Write '1' to the flag to clear it
------------------------------------------------------------------------------
p_multi_irq_detect : process (clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to multi_irq'length-1 loop
if rst_n_i = '0' then
multi_irq(I) <= '0';
elsif irq_src_p_i(I) = '1' and irq_pending(I) = '1' then
multi_irq(I) <= '1';
elsif multi_irq_rst_en = '1' and multi_irq_rst(I) = '1' then
multi_irq(I) <= '0';
end if;
end loop; -- I
end if;
end process p_multi_irq_detect;
------------------------------------------------------------------------------
-- Generate IRQ output pulse
------------------------------------------------------------------------------
irq_p_or(0) <= '0';
l_irq_out_pulse : for I in 0 to irq_src_p_i'length-1 generate
irq_p_or(I+1) <= irq_p_or(I) or (irq_src_p_i(I) and irq_en_mask(I));
end generate l_irq_out_pulse;
p_irq_out_pulse : process (clk_i)
begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
irq_p_o <= '0';
else
irq_p_o <= irq_p_or(32);
end if;
end if;
end process p_irq_out_pulse;
end rtl;
play/hdl/design/irq_controller_regs.vhd 0 → 100644
View file @ feba6ffa
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for IRQ controller registers
---------------------------------------------------------------------------------------
-- File : ../rtl/irq_controller_regs.vhd
-- Author : auto-generated by wbgen2 from irq_controller_regs.wb
-- Created : Wed Jan 18 09:43:55 2012
-- Standard : VHDL'87
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE irq_controller_regs.wb
-- DO NOT HAND-EDIT UNLESS IT'S ABSOLUTELY NECESSARY!
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity irq_controller_regs is
port (
rst_n_i : in std_logic;
wb_clk_i : in std_logic;
wb_addr_i : in std_logic_vector(1 downto 0);
wb_data_i : in std_logic_vector(31 downto 0);
wb_data_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
-- Port for std_logic_vector field: 'Multiple interrupt' in reg: 'Multiple interrupt register'
irq_ctrl_multi_irq_o : out std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_i : in std_logic_vector(31 downto 0);
irq_ctrl_multi_irq_load_o : out std_logic;
-- Port for std_logic_vector field: 'Interrupt sources' in reg: 'Interrupt sources register '
irq_ctrl_src_o : out std_logic_vector(31 downto 0);
irq_ctrl_src_i : in std_logic_vector(31 downto 0);
irq_ctrl_src_load_o : out std_logic;
-- Port for std_logic_vector field: 'Interrupt enable mask' in reg: 'Interrupt enable mask register'
irq_ctrl_en_mask_o : out std_logic_vector(31 downto 0)
);
end irq_controller_regs;
architecture syn of irq_controller_regs is
signal irq_ctrl_en_mask_int : std_logic_vector(31 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(31 downto 0);
signal wrdata_reg : std_logic_vector(31 downto 0);
signal bwsel_reg : std_logic_vector(3 downto 0);
signal rwaddr_reg : std_logic_vector(1 downto 0);
signal ack_in_progress : std_logic ;
signal wr_int : std_logic ;
signal rd_int : std_logic ;
signal bus_clock_int : std_logic ;
signal allones : std_logic_vector(31 downto 0);
signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_data_i;
bwsel_reg <= wb_sel_i;
bus_clock_int <= wb_clk_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
allzeros <= (others => '0');
--
-- Main register bank access process.
process (bus_clock_int, rst_n_i)
begin
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
rddata_reg <= "00000000000000000000000000000000";
irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0';
irq_ctrl_en_mask_int <= "00000000000000000000000000000000";
elsif rising_edge(bus_clock_int) then
-- advance the ACK generator shift register
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (ack_in_progress = '1') then
if (ack_sreg(0) = '1') then
irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0';
ack_in_progress <= '0';
else
irq_ctrl_multi_irq_load_o <= '0';
irq_ctrl_src_load_o <= '0';
end if;
else
if ((wb_cyc_i = '1') and (wb_stb_i = '1')) then
case rwaddr_reg(1 downto 0) is
when "00" =>
if (wb_we_i = '1') then
irq_ctrl_multi_irq_load_o <= '1';
else
rddata_reg(31 downto 0) <= irq_ctrl_multi_irq_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "01" =>
if (wb_we_i = '1') then
irq_ctrl_src_load_o <= '1';
else
rddata_reg(31 downto 0) <= irq_ctrl_src_i;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when "10" =>
if (wb_we_i = '1') then
irq_ctrl_en_mask_int <= wrdata_reg(31 downto 0);
else
rddata_reg(31 downto 0) <= irq_ctrl_en_mask_int;
end if;
ack_sreg(0) <= '1';
ack_in_progress <= '1';
when others =>
-- prevent the slave from hanging the bus on invalid address
ack_in_progress <= '1';
ack_sreg(0) <= '1';
end case;
end if;
end if;
end if;
end process;
-- Drive the data output bus
wb_data_o <= rddata_reg;
-- Multiple interrupt
irq_ctrl_multi_irq_o <= wrdata_reg(31 downto 0);
-- Interrupt sources
irq_ctrl_src_o <= wrdata_reg(31 downto 0);
-- Interrupt enable mask
irq_ctrl_en_mask_o <= irq_ctrl_en_mask_int;
rwaddr_reg <= wb_addr_i;
-- ACK signal generation. Just pass the LSB of ACK counter.
wb_ack_o <= ack_sreg(0);
end syn;
play/hdl/design/led_ctrl.vhd 0 → 100644
View file @ feba6ffa
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: LED control (led_ctrl.vhd)
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2011-09-14
--
-- version: 1.0
--
-- description: Top entity for LED control project
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--=============================================================================
-- Entity declaration for LED control
--=============================================================================
entity led_ctrl is
Port (
-------------------------------------------------------------------------
-- WISHBONE SLAVE PORTS
-------------------------------------------------------------------------
-- input signals
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
wb_dat_i : in std_logic;
wb_adr_i : in std_logic;
wb_stb_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
-- output signals
wb_ack_o : out STD_LOGIC;
wb_dat_o : out std_logic;
-------------------------------------------------------------------------
-- OTHER ENTITY PORTS
-------------------------------------------------------------------------
irq_o : out std_logic_vector(1 downto 0);
leds_o : out STD_LOGIC_VECTOR (1 downto 0)
);
end led_ctrl;
--=============================================================================
--=============================================================================
-- Architecture declaration for leds_sm
--=============================================================================
architecture behavioral of led_ctrl is
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
signal s_ctrl_reg : std_logic_vector(1 downto 0);
-- signal s_adr : std_logic;
signal s_dat : std_logic;
signal s_irq : std_logic_vector(1 downto 0);
--=============================================================================
-- architecture begin
--=============================================================================
begin
-----------------------------------------------------------------------------
-- Input and output logic
-----------------------------------------------------------------------------
-- output logic
leds_o <= s_ctrl_reg;
wb_dat_o <= s_dat;
irq_o <= s_irq;
-----------------------------------------------------------------------------
-- WISHBONE registers process
-----------------------------------------------------------------------------
p_wb_reg: process (clk_i, rst_i) is
begin
if rising_edge(clk_i) then
if (rst_i = '1') then
wb_ack_o <= '0';
s_dat <= '0';
s_ctrl_reg <= "00";
s_irq <= "00";
else
wb_ack_o <= '0';
s_irq <= "00";
if (wb_stb_i = '1') and (wb_cyc_i = '1') then
wb_ack_o <= '1';
if (wb_we_i = '1') then
-- s_irq <= '1'; -- IRQ on write to any of the registers
if (wb_adr_i = '0') then
s_ctrl_reg(0) <= wb_dat_i;
s_irq(0) <= '1';
else
s_ctrl_reg(1) <= wb_dat_i;
s_irq(1) <= '1';
end if;
else
if (wb_adr_i = '0') then
s_dat <= s_ctrl_reg(0);
else
s_dat <= s_ctrl_reg(1);
end if;
end if;
end if;
end if;
end if;
end process p_wb_reg;
-----------------------------------------------------------------------------
end behavioral;
--==================================================================================
-- architecture end
--==================================================================================
play/hdl/design/led_ctrl_top.vhd 0 → 100644
View file @ feba6ffa
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Top level entity for Simple PCIe FMC Carrier
-- http://www.ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: Top-level for LED control (led_ctrl_top.vhd)
--
-- author: Theodor Stana (t.stana@cern.ch)
--
-- date of creation: 2011-09-14
--
-- version: 1.0
--
-- description: Top entity for LED control project
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library work;
use work.gn4124_core_pkg.all;
--=============================================================================
-- Entity declaration for LED control top-level
--=============================================================================
entity led_ctrl_top is
port
(
-- Local oscillator
sys_clk : in std_logic; -- 20MHz VCXO clock
-- GN4124 interface
L_CLKp : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_CLKn : in std_logic; -- Local bus clock (frequency set in GN4124 config registers)
L_RST_N : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
P2L_RDY : out std_logic; -- Rx Buffer Full Flag
P2L_CLKn : in std_logic; -- Receiver Source Synchronous Clock-
P2L_CLKp : in std_logic; -- Receiver Source Synchronous Clock+
P2L_DATA : in std_logic_vector(15 downto 0); -- Parallel receive data
P2L_DFRAME : in std_logic; -- Receive Frame
P2L_VALID : in std_logic; -- Receive Data Valid
P_WR_REQ : in std_logic_vector(1 downto 0); -- PCIe Write Request
P_WR_RDY : out std_logic_vector(1 downto 0); -- PCIe Write Ready
RX_ERROR : out std_logic; -- Receive Error
L2P_DATA : out std_logic_vector(15 downto 0); -- Parallel transmit data
L2P_DFRAME : out std_logic; -- Transmit Data Frame
L2P_VALID : out std_logic; -- Transmit Data Valid
L2P_CLKn : out std_logic; -- Transmitter Source Synchronous Clock-
L2P_CLKp : out std_logic; -- Transmitter Source Synchronous Clock+
L2P_EDB : out std_logic; -- Packet termination and discard
L2P_RDY : in std_logic; -- Tx Buffer Full Flag
L_WR_RDY : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
P_RD_D_RDY : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
TX_ERROR : in std_logic; -- Transmit Error
VC_RDY : in std_logic_vector(1 downto 0); -- Channel ready
GPIO : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- outputs:
leds : out std_logic_vector(1 downto 0)
);
end entity;
--=============================================================================
--=============================================================================
-- Architecture declaration for LED control top-level entity
--=============================================================================
architecture struct of led_ctrl_top is
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
-- address decoder
component addr_dec
port (
-- Input signals
cyc_i : in std_logic;
adr_i : in std_logic;
dat_i : in std_logic_vector(63 downto 0);
ack_i : in std_logic_vector(1 downto 0);
-- Output signals
cyc_o : out std_logic_vector(1 downto 0);
ack_o : out std_logic;
dat_o : out std_logic_vector(31 downto 0)
);
end component;
-- IRQ controller
component irq_controller
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
irq_src_p_i : in std_logic_vector(31 downto 0);
irq_p_o : out std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end component irq_controller;
-- LED control slave
component led_ctrl is
Port (
-------------------------------------------------------------------------
-- WISHBONE SLAVE PORTS
-------------------------------------------------------------------------
-- input signals
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
wb_dat_i : in std_logic;
wb_adr_i : in std_logic;
wb_stb_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
-- output signals
wb_ack_o : out STD_LOGIC;
wb_dat_o : out std_logic;
-------------------------------------------------------------------------
-- OTHER ENTITY PORTS
-------------------------------------------------------------------------
irq_o : out std_logic_vector(1 downto 0);
leds_o : out STD_LOGIC_VECTOR (1 downto 0)
);
end component led_ctrl;
-- clock divider
component clk_div is
port
(
clk_i : in STD_LOGIC;
reset_i : in std_logic;
clk_o : out STD_LOGIC
);
end component clk_div;
component leds_sm is
port
(
-- global input signals
clk_i : in STD_LOGIC;
reset_i : in STD_LOGIC;
-- global output signals
led1a_o : out STD_LOGIC; -- LED1A, '1' = on
-- '0' = off
led1b_o : out STD_LOGIC -- LED1B, '1' = on
-- '0' = off
);
end component leds_sm;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Local signals
signal s_rst : std_logic;
signal l_clk : std_logic;
signal s_pps : std_logic;
signal s_leds : std_logic_vector (1 downto 0);
signal s_leds_mux_sel : std_logic;
signal s_leds_mux_in_a : std_logic_vector (1 downto 0);
signal s_leds_mux_in_b : std_logic_vector (1 downto 0);
-- System clock
signal sys_clk_125_buf : std_logic;
signal sys_clk_250_buf : std_logic;
signal sys_clk_125 : std_logic;
signal sys_clk_250 : std_logic;
signal sys_clk_fb : std_logic;
signal sys_clk_pll_locked : std_logic;
-- Gennum interface signals
signal s_gennum_cyc_o : std_logic;
signal s_gennum_adr_o : std_logic_vector (31 downto 0);
signal s_gennum_sel_o : std_logic_vector(3 downto 0);
signal s_gennum_dat_i : std_logic_vector(31 downto 0);
signal s_gennum_dat_o : std_logic_vector(31 downto 0);
signal s_gennum_stb_o : std_logic;
signal s_gennum_we_o : std_logic;
signal s_gennum_we_o_d1 : std_logic;
signal s_gennum_we_o_d2 : std_logic;
signal s_gennum_ack_i : std_logic;
-- Address decoder signals
signal s_dec_cyc_o : std_logic_vector(1 downto 0);
signal s_dec_ack_i : std_logic_vector(1 downto 0);
signal s_dec_dat_i : std_logic_vector(63 downto 0);
-- IRQ controller signals
signal s_irq_p : std_logic;
signal s_leds_irq : std_logic_vector(1 downto 0);
signal s_irq : std_logic_vector(31 downto 0);
--=============================================================================
-- architecture begin
--=============================================================================
begin
-----------------------------------------------------------------------------
-- Input and output logic
-----------------------------------------------------------------------------
s_rst <= not L_RST_N;
leds <= s_leds;
GPIO(1) <= '0';
-----------------------------------------------------------------------------
-- Register for WE edge detection and selection
-----------------------------------------------------------------------------
p_reg : process (sys_clk, L_RST_N)
begin
if rising_edge(sys_clk) then
if (L_RST_N = '0') then
s_gennum_we_o_d1 <= '0';
s_gennum_we_o_d2 <= '0';
s_leds_mux_sel <= '0';
else
s_gennum_we_o_d1 <= s_gennum_we_o;
s_gennum_we_o_d2 <= s_gennum_we_o_d1;
if (s_gennum_we_o_d1 = '1') and (s_gennum_we_o_d2 = '0') and (s_dec_cyc_o(1) = '1') then
s_leds_mux_sel <= '1';
end if;
end if;
end if;
end process p_reg;
-----------------------------------------------------------------------------
-- MUX for LED output control
-----------------------------------------------------------------------------
s_leds <= s_leds_mux_in_a when s_leds_mux_sel = '0' else
s_leds_mux_in_b;
-----------------------------------------------------------------------------
-- Component instantiation
-----------------------------------------------------------------------------
-- PLL
-- cmp_sys_clk_pll : PLL_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED",
-- CLK_FEEDBACK => "CLKFBOUT",
-- COMPENSATION => "INTERNAL",
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT => 50,
-- CLKFBOUT_PHASE => 0.000,
-- CLKOUT0_DIVIDE => 8,
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DIVIDE => 4,
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DIVIDE => 3,
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKIN_PERIOD => 50.0,
-- REF_JITTER => 0.016)
-- port map (
-- CLKFBOUT => sys_clk_fb,
-- CLKOUT0 => sys_clk_125_buf,
-- CLKOUT1 => sys_clk_250_buf,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => sys_clk_pll_locked,
-- RST => '0',
-- CLKFBIN => sys_clk_fb,
-- CLKIN => sys_clk
-- );
-- GN4124 core
cmp_gn4124_core : gn4124_core
port map(
rst_n_a_i => L_RST_N,
status_o => open,
-- P2L Direction Source Sync DDR related signals
p2l_clk_p_i => P2L_CLKp,
p2l_clk_n_i => P2L_CLKn,
p2l_data_i => P2L_DATA,
p2l_dframe_i => P2L_DFRAME,
p2l_valid_i => P2L_VALID,
-- P2L Control
p2l_rdy_o => P2L_RDY,
p_wr_req_i => P_WR_REQ,
p_wr_rdy_o => P_WR_RDY,
rx_error_o => RX_ERROR,
-- L2P Direction Source Sync DDR related signals
l2p_clk_p_o => L2P_CLKp,
l2p_clk_n_o => L2P_CLKn,
l2p_data_o => L2P_DATA,
l2p_dframe_o => L2P_DFRAME,
l2p_valid_o => L2P_VALID,
l2p_edb_o => L2P_EDB,
-- L2P Control
l2p_rdy_i => L2P_RDY,
l_wr_rdy_i => L_WR_RDY,
p_rd_d_rdy_i => P_RD_D_RDY,
tx_error_i => TX_ERROR,
vc_rdy_i => VC_RDY,
-- Interrupt interface
dma_irq_o => open,
irq_p_i => s_irq_p,
irq_p_o => GPIO(0),
-- DMA registers wishbone interface (slave classic)
dma_reg_clk_i => '0',
dma_reg_adr_i => (others => '0'),
dma_reg_dat_i => (others => '0'),
dma_reg_sel_i => (others => '0'),
dma_reg_stb_i => '0',
dma_reg_we_i => '0',
dma_reg_cyc_i => '0',
dma_reg_dat_o => open,
dma_reg_ack_o => open,
dma_reg_stall_o => open,
-- CSR wishbone interface (master pipelined)
csr_clk_i => sys_clk,
csr_adr_o => s_gennum_adr_o,
csr_dat_o => s_gennum_dat_o,
csr_sel_o => s_gennum_sel_o,
csr_stb_o => s_gennum_stb_o,
csr_we_o => s_gennum_we_o,
csr_cyc_o => s_gennum_cyc_o,
csr_dat_i => s_gennum_dat_i,
csr_ack_i => s_gennum_ack_i,
csr_stall_i => '0',
-- DMA wishbone interface (pipelined)
dma_clk_i => '0',
dma_adr_o => open,
dma_dat_o => open,
dma_sel_o => open,
dma_stb_o => open,
dma_we_o => open,
dma_cyc_o => open,
dma_dat_i => (others => '0'),
dma_ack_i => '0',
dma_stall_i => '0'
);
-- local clock from Gennum clock
cmp_l_clk_buf : IBUFDS
generic map (
DIFF_TERM => false, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
IOSTANDARD => "DEFAULT")
port map (
O => l_clk, -- Buffer output
I => L_CLKp, -- Diff_p buffer input (connect directly to top-level port)
IB => L_CLKn -- Diff_n buffer input (connect directly to top-level port)
);
-- Address decoder; address map:
-- 0x0 : IRQ multi_irq
-- 0x1 : IRQ src
-- 0x2 : IRQ en_mask
-- 0x3 : RESERVED
-- 0x4 : LED LED1A
-- 0x5 : LED LED1B
cmp_addr_dec : addr_dec
port map (
adr_i => s_gennum_adr_o(2),
cyc_i => s_gennum_cyc_o,
dat_i => s_dec_dat_i,
ack_i => s_dec_ack_i,
cyc_o => s_dec_cyc_o,
ack_o => s_gennum_ack_i,
dat_o => s_gennum_dat_i
);
s_dec_dat_i(63 downto 33) <= (others => '0');
-- IRQ controller
cmp_irq_ctrl: irq_controller
port map
(
clk_i => sys_clk,
rst_n_i => L_RST_N,
irq_src_p_i => s_irq,
irq_p_o => s_irq_p,
wb_adr_i => s_gennum_adr_o(1 downto 0),
wb_dat_i => s_gennum_dat_o,
wb_dat_o => s_dec_dat_i(31 downto 0),
wb_cyc_i => s_dec_cyc_o(0),
wb_sel_i => s_gennum_sel_o,
wb_stb_i => s_gennum_stb_o,
wb_we_i => s_gennum_we_o,
wb_ack_o => s_dec_ack_i(0)
);
s_irq(31 downto 2) <= (others => '0');
s_irq(1 downto 0) <= s_leds_irq;
-- LED controller
cmp_led_ctrl: led_ctrl
port map
(
clk_i => sys_clk,
rst_i => s_rst,
wb_dat_i => s_gennum_dat_o(0),
wb_dat_o => s_dec_dat_i(32),
wb_adr_i => s_gennum_adr_o(0),
wb_stb_i => s_gennum_stb_o,
wb_we_i => s_gennum_we_o,
wb_cyc_i => s_dec_cyc_o(1),
wb_ack_o => s_dec_ack_i(1),
irq_o => s_leds_irq,
leds_o => s_leds_mux_in_b
);
-- clock divider
cmp_clk_div : clk_div
port map
(
clk_i => sys_clk,
reset_i => s_rst,
clk_o => s_pps
);
-- LED switcher
cmp_leds_sm : leds_sm
port map
(
clk_i => s_pps,
reset_i => s_rst,
led1a_o => s_leds_mux_in_a(0),
led1b_o => s_leds_mux_in_a(1)
);
end architecture;
--=============================================================================
-- architecture end
--=============================================================================
play/hdl/design/leds_sm.vhd 0 → 100644
View file @ feba6ffa
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:01:04 09/11/2012
-- Design Name:
-- Module Name: leds_sm - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--==================================================================================
-- Entity declaration for LEDs state machine
--==================================================================================
entity leds_sm is
Port
(
-- global input signals
clk_i : in STD_LOGIC;
reset_i : in STD_LOGIC;
-- global output signals
led1a_o : out STD_LOGIC; -- LED1A, '1' = on
-- '0' = off
led1b_o : out STD_LOGIC -- LED1B, '1' = on
-- '0' = off
);
end leds_sm;
--==================================================================================
----==================================================================================
---- Architecture declaration for leds_sm
----==================================================================================
architecture behavioral of leds_sm is
signal s_cnt : std_logic_vector(1 downto 0) := (others => '0');
----==================================================================================
---- architecture begin
----==================================================================================
begin
----------------------------------------------------------------
-- Entity input and output logic
----------------------------------------------------------------
led1a_o <= s_cnt(0);
led1b_o <= s_cnt(1);
----------------------------------------------------------------
----------------------------------------------------------------
-- Counter process
----------------------------------------------------------------
p_count: process (clk_i, reset_i)
begin
if (reset_i = '1') then
s_cnt <= "00";
elsif rising_edge(clk_i) then
s_cnt <= s_cnt + 1;
end if;
end process p_count;
----------------------------------------------------------------
end;
----==================================================================================
---- architecture end
----==================================================================================
----==================================================================================
---- Architecture declaration for leds_sm
----==================================================================================
--architecture behavioral of leds_sm is
--
---------------------------------------------------------------------
---- LED state machine type and signal declaration
---------------------------------------------------------------------
-- type t_state_mach is (ST_IDLE, ST_LED1A, ST_LED1B);
--
-- signal s_state_pres : t_state_mach;
---------------------------------------------------------------------
--
---------------------------------------------------------------------
---- Internal signals for entity outputs
---------------------------------------------------------------------
-- signal s_led1a, s_led1b : std_logic;
---------------------------------------------------------------------
--
--
----==================================================================================
---- architecture begin
----==================================================================================
--begin
--
-- ----------------------------------------------------------------
-- -- Entity input and output logic
-- ----------------------------------------------------------------
-- led1a_o <= s_led1a;
-- led1b_o <= s_led1b;
-- ----------------------------------------------------------------
--
-- ----------------------------------------------------------------
-- -- State logic for LED FSM
-- ----------------------------------------------------------------
-- fsm_proc: process (reset_i, clk_i)
-- begin
--
-- if (reset_i = '1') then
-- s_state_pres <= ST_IDLE;
--
-- elsif rising_edge(clk_i) then
--
-- case s_state_pres is
--
-- when ST_IDLE =>
-- s_state_pres <= ST_LED1A;
--
-- when ST_LED1A =>
-- s_state_pres <= ST_LED1B;
--
-- when ST_LED1B =>
-- s_state_pres <= ST_IDLE;
--
-- when others =>
-- s_state_pres <= ST_IDLE;
--
-- end case;
--
-- end if;
--
-- end process fsm_proc;
-- ----------------------------------------------------------------
--
-- ----------------------------------------------------------------
-- -- Output logic for LED FSM
-- ----------------------------------------------------------------
-- fsm_proc: process (reset_i, clk_i)
-- begin
--
-- if (reset_i = '1') then
-- s_led1a <= '0';
-- s_led1b <= '0';
--
-- elsif rising_edge(clk_i) then
--
-- case s_state_pres is
--
-- when ST_IDLE =>
-- s_led1a <= '0';
-- s_led1b <= '0';
--
-- when ST_LED1A =>
-- s_led1a <= '1';
-- s_led1b <= '0';
--
-- when ST_LED1B =>
-- s_led1a <= '0';
-- s_led1b <= '1';
--
-- when others =>
-- s_led1a <= '1';
-- s_led1b <= '1';
--
-- end case;
--
-- end if;
--
-- end process fsm_proc;
-- ----------------------------------------------------------------
--
--end Behavioral;
----==================================================================================
---- architecture end
----==================================================================================
play/hdl/tb/testbench.vhd 0 → 100644
View file @ feba6ffa
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:40:28 09/12/2012
-- Design Name:
-- Module Name: /home/tstana/Projects/play_fmcadc100m14b4cha/hdl/tb/testbench.vhd
-- Project Name: play_fmcadc100m14b4cha
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: led_ctrl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
-----------------------------------------------------------------------------
-- Components
-----------------------------------------------------------------------------
-- UUT
COMPONENT led_ctrl
PORT(
-------------------------------------------------------------------------
-- WISHBONE SLAVE PORTS
-------------------------------------------------------------------------
-- input signals
clk_i : in STD_LOGIC;
rst_i : in STD_LOGIC;
wb_dat_i : in std_logic;
wb_adr_i : in std_logic;
wb_stb_i : in STD_LOGIC;
wb_we_i : in STD_LOGIC;
wb_cyc_i : in STD_LOGIC;
-- output signals
wb_ack_o : out STD_LOGIC;
wb_dat_o : out std_logic;
-------------------------------------------------------------------------
-- OTHER ENTITY PORTS
-------------------------------------------------------------------------
irq_o : out std_logic_vector(1 downto 0);
leds_o : out STD_LOGIC_VECTOR (1 downto 0)
);
END COMPONENT;
-- IRQ controller
component irq_controller
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
irq_src_p_i : in std_logic_vector(31 downto 0);
irq_p_o : out std_logic;
wb_adr_i : in std_logic_vector(1 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic
);
end component irq_controller;
-- address decoder
component addr_dec
port (
-- Input signals
cyc_i : in std_logic;
adr_i : in std_logic;
dat_i : in std_logic_vector(63 downto 0);
ack_i : in std_logic_vector(1 downto 0);
-- Output signals
cyc_o : out std_logic_vector(1 downto 0);
ack_o : out std_logic;
dat_o : out std_logic_vector(31 downto 0)
);
end component;
-----------------------------------------------------------------------------
-- Type definitions
-----------------------------------------------------------------------------
type t_mst_fsm is (ST_IDLE, ST_WR1, ST_WR2, ST_RD1, ST_RD2, ST_DUMMY);
type t_fsm_act is (ACT_WR, ACT_RD); -- tells the master FSM what to do -- read/write
-----------------------------------------------------------------------------
-- Constants
-----------------------------------------------------------------------------
constant c_CLK20_PER : time := 50 ns;
constant c_CLK125_PER : time := 8 ns;
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- Clock, reset
signal s_clk : std_logic := '0';
signal s_clk125 : std_logic := '0';
signal s_rst : std_logic := '0';
signal s_rst_n : std_logic := '1';
-- Wishbone
signal s_wb_dat : std_logic_vector(31 downto 0) := (others => '0');
signal s_wb_we : std_logic := '0';
signal s_wb_stb : std_logic := '0';
signal s_wb_cyc : std_logic := '0';
signal s_wb_dat_i : std_logic_vector(31 downto 0);
signal s_wb_dat_o : std_logic_vector(31 downto 0);
signal s_wb_adr : std_logic_vector(31 downto 0);
signal s_ack : std_logic;
-- Master FSM signals
signal s_state : t_mst_fsm;
signal s_fsm_data : std_logic_vector(31 downto 0);
signal s_fsm_ctrl : std_logic; -- 1 = write, 0 = read
signal s_fsm_act : t_fsm_act; -- FSM action
-- Address decoder signals
signal s_dec_cyc_o : std_logic_vector(1 downto 0);
signal s_dec_ack_i : std_logic_vector(1 downto 0);
signal s_dec_dat_i : std_logic_vector(63 downto 0);
-- IRQ controller signals
signal s_irq_p : std_logic;
signal s_leds_irq : std_logic_vector(1 downto 0);
signal s_irq : std_logic_vector(31 downto 0);
signal s_leds : std_logic_vector(1 downto 0);
--=============================================================================
-- architecture begin
--=============================================================================
BEGIN
-----------------------------------------------------------------------------
-- Component instantiation
-----------------------------------------------------------------------------
-- Instantiate the Unit Under Test (UUT)
uut: led_ctrl PORT MAP (
clk_i => s_clk,
rst_i => s_rst,
wb_dat_i => s_wb_dat_o(0),
wb_adr_i => s_wb_adr(0),
wb_we_i => s_wb_we,
wb_stb_i => s_wb_stb,
wb_cyc_i => s_dec_cyc_o(1),
wb_ack_o => s_dec_ack_i(1),
wb_dat_o => s_dec_dat_i(32),
irq_o => s_leds_irq,
leds_o => s_leds
);
-- IRQ controller
cmp_irq_ctrl: irq_controller
port map
(
clk_i => s_clk125,
rst_n_i => s_rst_n,
irq_src_p_i => s_irq,
irq_p_o => s_irq_p,
wb_adr_i => s_wb_adr(1 downto 0),
wb_dat_i => s_wb_dat_o,
wb_dat_o => s_dec_dat_i(31 downto 0),
wb_cyc_i => s_dec_cyc_o(0),
wb_sel_i => (others => '0'),
wb_stb_i => s_wb_stb,
wb_we_i => s_wb_we,
wb_ack_o => s_dec_ack_i(0)
);
s_irq(31 downto 2) <= (others => '0');
s_irq(1 downto 0) <= s_leds_irq;
s_rst_n <= not s_rst;
-- Address decoder
cmp_addr_dec : addr_dec
port map (
adr_i => s_wb_adr(2),
cyc_i => s_wb_cyc,
dat_i => s_dec_dat_i,
ack_i => s_dec_ack_i,
cyc_o => s_dec_cyc_o,
ack_o => s_ack,
dat_o => s_wb_dat_i
);
s_dec_dat_i(63 downto 33) <= (others => '0');
-----------------------------------------------------------------------------
-- Clock generation processes
-----------------------------------------------------------------------------
p_clk20: process
begin
s_clk <= '0';
wait for c_CLK20_PER/2;
s_clk <= '1';
wait for c_CLK20_PER/2;
end process p_clk20;
p_clk125: process
begin
s_clk125 <= '0';
wait for c_CLK125_PER/2;
s_clk125 <= '1';
wait for c_CLK125_PER/2;
end process p_clk125;
-----------------------------------------------------------------------------
-- Stimulus process
-----------------------------------------------------------------------------
p_stim_irq: process is
begin
s_rst <= '1';
s_fsm_ctrl <= '0';
s_fsm_act <= ACT_WR;
s_fsm_data <= x"00000000";
s_wb_adr <= x"00000000";
-- hold reset state for 100 ns.
wait for 100 ns;
s_rst <= '0';
--wait for c_CLK20_PER*10;
wait for 10 ns;
-- IRQ_EN_MASK reg write
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_WR;
s_wb_adr <= x"00000002";
s_fsm_data <= x"00000001";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- IRQ_EN_MASK reg read
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_RD;
s_wb_adr <= x"00000002";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- LED R0 read
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_RD;
s_wb_adr <= x"00000004";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- LED R1 read
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_RD;
s_wb_adr <= x"00000005";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- LED R0 write
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_WR;
s_wb_adr <= x"00000004";
s_fsm_data <= x"00000001";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- LED R0 read
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_RD;
s_wb_adr <= x"00000004";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- IRQ_SRC read
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_RD;
s_wb_adr <= x"00000001";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- IRQ_SRC write
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_WR;
s_wb_adr <= x"00000001";
s_fsm_data <= x"00000001";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- LED R1 write
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_WR;
s_wb_adr <= x"00000005";
s_fsm_data <= x"00000001";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- LED R1 read
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_RD;
s_wb_adr <= x"00000005";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- IRQ_SRC read
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_RD;
s_wb_adr <= x"00000001";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- IRQ_SRC write
wait for c_CLK20_PER * 5;
s_fsm_ctrl <= '1';
s_fsm_act <= ACT_WR;
s_wb_adr <= x"00000001";
s_fsm_data <= x"00000001";
wait for c_CLK20_PER;
s_fsm_ctrl <= '0';
-- WAIT INDEFINITELY
wait;
end process p_stim_irq;
-- -- Stimulus process
-- stim_proc: process
-- begin
-- s_rst <= '1';
-- s_fsm_ctrl <= '0';
-- s_fsm_act <= ACT_WR;
-- s_fsm_data <= x"00000000";
-- s_wb_adr <= x"00000000";
-- -- hold reset state for 100 ns.
-- wait for 100 ns;
-- s_rst <= '0';
-- --wait for c_CLK20_PER*10;
-- wait for 10 ns;
-- -- insert stimulus here
-- -- WR 1 -> R0
-- s_fsm_ctrl <= '1';
-- s_fsm_act <= ACT_WR;
-- s_wb_adr <= x"00000000";
-- s_fsm_data <= x"00000001";
-- wait for c_CLK20_PER;
-- s_fsm_ctrl <= '0';
-- -- RD R0
-- wait for c_CLK20_PER * 5;
-- s_fsm_ctrl <= '1';
-- s_fsm_act <= ACT_RD;
-- s_wb_adr <= x"00000000";
-- wait for c_CLK20_PER;
-- s_fsm_ctrl <= '0';
-- -- RD R1
-- wait for c_CLK20_PER * 5;
-- s_fsm_ctrl <= '1';
-- s_fsm_act <= ACT_RD;
-- s_wb_adr <= x"00000001";
-- wait for c_CLK20_PER;
-- s_fsm_ctrl <= '0';
-- -- WR 1 -> R1
-- wait for c_CLK20_PER * 5;
-- s_fsm_ctrl <= '1';
-- s_fsm_act <= ACT_WR;
-- s_wb_adr <= x"00000001";
-- s_fsm_data <= x"00000001";
-- wait for c_CLK20_PER;
-- s_fsm_ctrl <= '0';
-- -- RD R1
-- wait for c_CLK20_PER * 5;
-- s_fsm_ctrl <= '1';
-- s_fsm_act <= ACT_RD;
-- s_wb_adr <= x"00000001";
-- -- s_fsm_data <= x"00000001";
-- wait for c_CLK20_PER;
-- s_fsm_ctrl <= '0';
-- -- WR 0 -> R0
-- wait for c_CLK20_PER * 5;
-- s_fsm_ctrl <= '1';
-- s_fsm_act <= ACT_WR;
-- s_wb_adr <= x"00000000";
-- s_fsm_data <= x"00000000";
-- wait for c_CLK20_PER;
-- s_fsm_ctrl <= '0';
-- -- RD R0
-- wait for c_CLK20_PER * 5;
-- s_fsm_ctrl <= '1';
-- s_fsm_act <= ACT_RD;
-- s_wb_adr <= x"00000000";
-- -- s_fsm_data <= x"00000001";
-- wait for c_CLK20_PER;
-- s_fsm_ctrl <= '0';
-- -- WAIT INDEFINITELY
-- wait;
-- end process;
-----------------------------------------------------------------------------
-- FSM process
-----------------------------------------------------------------------------
p_fsm: process (s_clk, s_rst, s_state) is
begin
if rising_edge(s_clk) then
if (s_rst = '1') then
s_state <= ST_IDLE;
s_wb_we <= '0';
s_wb_stb <= '0';
s_wb_cyc <= '0';
s_wb_dat_o <= (others => '0');
else
case s_state is
when ST_IDLE =>
s_wb_we <= '0';
s_wb_stb <= '0';
s_wb_cyc <= '0';
if (s_fsm_ctrl = '1') then
if (s_fsm_act = ACT_WR) then
s_state <= ST_WR1;
else
s_state <= ST_RD1;
end if;
end if;
when ST_WR1 =>
s_wb_dat_o <= s_fsm_data;
s_wb_we <= '1';
s_wb_stb <= '1';
s_wb_cyc <= '1';
s_state <= ST_WR2;
when ST_WR2 =>
if (s_ack = '1') then
s_wb_we <= '0';
s_wb_stb <= '0';
s_wb_cyc <= '0';
s_state <= ST_IDLE;
end if;
when ST_RD1 =>
s_wb_we <= '0';
s_wb_stb <= '1';
s_wb_cyc <= '1';
s_state <= ST_RD2;
when ST_RD2 =>
if (s_ack = '1') then
s_wb_stb <= '0';
s_wb_cyc <= '0';
s_state <= ST_IDLE;
end if;
when ST_DUMMY =>
s_wb_dat <= (others => '0');
s_state <= ST_IDLE;
when others =>
s_state <= ST_IDLE;
end case;
end if;
end if;
end process p_fsm;
-----------------------------------------------------------------------------
END;
--=============================================================================
-- architecture end
--=============================================================================
play/sim/run.do 0 → 100644
View file @ feba6ffa
vlib work
vcom -explicit -93 "../hdl/design/led_ctrl.vhd"
vcom -explicit -93 "../hdl/design/irq_controller_regs.vhd"
vcom -explicit -93 "../hdl/design/irq_controller.vhd"
vcom -explicit -93 "../hdl/design/addr_dec.vhd"
vcom -explicit -93 "../hdl/tb/testbench.vhd"
vsim -voptargs="+acc" -debugdb -lib work work.testbench
log -r /*
# add wave *
do wave.do
run 4 us
play/sim/wave.do 0 → 100644
View file @ feba6ffa
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate /testbench/s_clk
add wave -noupdate /testbench/s_rst
add wave -noupdate -radix unsigned /testbench/s_wb_dat
add wave -noupdate /testbench/s_wb_we
add wave -noupdate -radix unsigned /testbench/s_irq
add wave -noupdate /testbench/s_irq_p
add wave -noupdate /testbench/s_leds_irq
add wave -noupdate /testbench/s_wb_stb
add wave -noupdate /testbench/s_wb_cyc
add wave -noupdate /testbench/s_ack
add wave -noupdate /testbench/s_leds
add wave -noupdate -height 16 /testbench/s_state
add wave -noupdate -radix hexadecimal /testbench/s_fsm_data
add wave -noupdate /testbench/s_fsm_ctrl
add wave -noupdate /testbench/s_fsm_act
add wave -noupdate -radix hexadecimal /testbench/s_wb_dat_i
add wave -noupdate -radix hexadecimal /testbench/s_wb_dat_o
add wave -noupdate -radix hexadecimal -childformat {{/testbench/s_wb_adr(31) -radix hexadecimal} {/testbench/s_wb_adr(30) -radix hexadecimal} {/testbench/s_wb_adr(29) -radix hexadecimal} {/testbench/s_wb_adr(28) -radix hexadecimal} {/testbench/s_wb_adr(27) -radix hexadecimal} {/testbench/s_wb_adr(26) -radix hexadecimal} {/testbench/s_wb_adr(25) -radix hexadecimal} {/testbench/s_wb_adr(24) -radix hexadecimal} {/testbench/s_wb_adr(23) -radix hexadecimal} {/testbench/s_wb_adr(22) -radix hexadecimal} {/testbench/s_wb_adr(21) -radix hexadecimal} {/testbench/s_wb_adr(20) -radix hexadecimal} {/testbench/s_wb_adr(19) -radix hexadecimal} {/testbench/s_wb_adr(18) -radix hexadecimal} {/testbench/s_wb_adr(17) -radix hexadecimal} {/testbench/s_wb_adr(16) -radix hexadecimal} {/testbench/s_wb_adr(15) -radix hexadecimal} {/testbench/s_wb_adr(14) -radix hexadecimal} {/testbench/s_wb_adr(13) -radix hexadecimal} {/testbench/s_wb_adr(12) -radix hexadecimal} {/testbench/s_wb_adr(11) -radix hexadecimal} {/testbench/s_wb_adr(10) -radix hexadecimal} {/testbench/s_wb_adr(9) -radix hexadecimal} {/testbench/s_wb_adr(8) -radix hexadecimal} {/testbench/s_wb_adr(7) -radix hexadecimal} {/testbench/s_wb_adr(6) -radix hexadecimal} {/testbench/s_wb_adr(5) -radix hexadecimal} {/testbench/s_wb_adr(4) -radix hexadecimal} {/testbench/s_wb_adr(3) -radix hexadecimal} {/testbench/s_wb_adr(2) -radix hexadecimal} {/testbench/s_wb_adr(1) -radix hexadecimal} {/testbench/s_wb_adr(0) -radix hexadecimal}} -subitemconfig {/testbench/s_wb_adr(31) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(30) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(29) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(28) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(27) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(26) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(25) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(24) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(23) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(22) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(21) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(20) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(19) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(18) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(17) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(16) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(15) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(14) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(13) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(12) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(11) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(10) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(9) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(8) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(7) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(6) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(5) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(4) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(3) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(2) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(1) {-height 13 -radix hexadecimal} /testbench/s_wb_adr(0) {-height 13 -radix hexadecimal}} /testbench/s_wb_adr
add wave -noupdate -divider {ADDRESS DECODER}
add wave -noupdate /testbench/cmp_addr_dec/cyc_i
add wave -noupdate /testbench/cmp_addr_dec/adr_i
add wave -noupdate -radix hexadecimal /testbench/cmp_addr_dec/dat_i
add wave -noupdate /testbench/cmp_addr_dec/ack_i
add wave -noupdate /testbench/cmp_addr_dec/cyc_o
add wave -noupdate /testbench/cmp_addr_dec/ack_o
add wave -noupdate -radix hexadecimal /testbench/cmp_addr_dec/dat_o
add wave -noupdate -divider LEDs
add wave -noupdate /testbench/uut/wb_cyc_i
add wave -noupdate /testbench/uut/wb_ack_o
add wave -noupdate /testbench/uut/irq_o
add wave -noupdate /testbench/uut/leds_o
add wave -noupdate /testbench/uut/s_ctrl_reg
add wave -noupdate /testbench/uut/s_dat
add wave -noupdate /testbench/uut/s_irq
add wave -noupdate -divider IRQ
add wave -noupdate -radix hexadecimal /testbench/cmp_irq_ctrl/irq_src_p_i
add wave -noupdate /testbench/cmp_irq_ctrl/irq_p_o
add wave -noupdate /testbench/cmp_irq_ctrl/wb_cyc_i
add wave -noupdate /testbench/cmp_irq_ctrl/wb_stb_i
add wave -noupdate /testbench/cmp_irq_ctrl/wb_we_i
add wave -noupdate /testbench/cmp_irq_ctrl/cmp_irq_controller_regs/rwaddr_reg
add wave -noupdate /testbench/cmp_irq_ctrl/wb_ack_o
add wave -noupdate -radix hexadecimal /testbench/cmp_irq_ctrl/irq_pending
add wave -noupdate -radix hexadecimal /testbench/cmp_irq_ctrl/irq_en_mask
add wave -noupdate -radix hexadecimal /testbench/cmp_irq_ctrl/irq_src_rst
add wave -noupdate /testbench/cmp_irq_ctrl/irq_src_rst_en
add wave -noupdate -radix hexadecimal /testbench/cmp_irq_ctrl/cmp_irq_controller_regs/irq_ctrl_src_i
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2394 ns} 0}
configure wave -namecolwidth 268
configure wave -valuecolwidth 116
configure wave -justifyvalue left
configure wave -signalnamewidth 0
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {1007 ns} {3005 ns}
play/sw/python/bitstream_load.py 0 → 100755
View file @ feba6ffa
#! /usr/bin/env python
# coding: utf8
# Copyright CERN, 2011
# Author: Matthieu Cattin <matthieu.cattin@cern.ch>
# Licence: GPL v2 or later.
# Website: http://www.ohwr.org
# Last modifications: 10/5/2012
# Import system modules
import sys
import time
import os
# Add common modules and libraries location to path
sys.path.append('../../../')
sys.path.append('../../../gnurabbit/python/')
sys.path.append('../../../common/')
# Import common modules
from ptsexcept import *
import rr
# Import specific modules
from fmc_adc_spec import *
"""
Load firmware
"""
def main (default_directory='.'):
# Constants declaration
TEST_NB = 0
#FMC_ADC_ADDR = '1a39:0004/1a39:0004@000B:0000'
#FMC_ADC_BITSTREAM = '../firmwares/spec_fmcadc100m14b4cha.bin'
#FMC_ADC_BITSTREAM = os.path.join(default_directory, FMC_ADC_BITSTREAM)
EXPECTED_BITSTREAM_TYPE = 0x1
FMC_ADC_BITSTREAM = sys.argv[1]
start_test_time = time.time()
print "\n================================================================================"
print "==> Test%02d start\n" % TEST_NB
# SPEC object declaration
print "Loading hardware access library and opening device.\n"
spec = rr.Gennum()
# Bind SPEC object to FMC ADC card
#for name, value in spec.parse_addr(FMC_ADC_ADDR).iteritems():
# print "%9s:0x%04X"%(name, value)
#spec.bind(FMC_ADC_ADDR)
# Load FMC ADC firmware
print "Loading FMC ADC firmware: %s\n" % FMC_ADC_BITSTREAM
spec.load_firmware(FMC_ADC_BITSTREAM)
time.sleep(2)
print "==> End of test%02d" % TEST_NB
print "================================================================================"
end_test_time = time.time()
print "Test%02d elapsed time: %.2f seconds\n" % (TEST_NB, end_test_time-start_test_time)
if __name__ == '__main__' :
main()
play/sw/python/play_leds.py 0 → 100644
View file @ feba6ffa
#!/usr/bin/env python
# Copyright CERN, 2011
# Author: Theodor Stana <t.stana@cern.ch>
# Licence: GPL v2 or later.
# Import system modules
import sys
import time
import os
# Add common modules and libraries location to path
#sys.path.append('../')
sys.path.append('../../../../')
sys.path.append('../../../../gnurabbit/python/')
sys.path.append('../../../../common/')
# Import common modules
from ptsexcept import *
import rr
from csr import *
import gn4124
'''
PLAY project
Playing with the connection-panel LEDs on the FmcAdc100m14b4cha board.
'''
#def wr()
#reg = int(sys.argv[1])
#val = int(sys.argv[2])
#regs.wr_reg(reg,val)
def main():
# Define register constants
IRQ_MULTI = 0x0
IRQ_SRC = 0x4
IRQ_EN_MASK = 0x8
# Create a SPEC object using RawRabbit driver
spec = rr.Gennum()
spec.irqena()
# Define the registers' base addresses
irq_regs = CCSR(spec, 0)
led_regs = CCSR(spec, 16)
# Enable interrupt on LED write
irq_regs.wr_reg(IRQ_EN_MASK, 0x3)
msk = irq_regs.rd_reg(IRQ_EN_MASK)
print "Mask: 0x%x" % msk
act = ''
while (act != "q"):
act = raw_input("(w)rite/(r)ead/(q)uit? ")
act = act.lower()
if (act == "w"):
print "WRITE"
reg = input("reg? ")
val = input("val? ")
led_regs.wr_reg(reg,val)
time.sleep(0.002)
spec.irqwait()
print "interrupt!"
# multi = irq_regs.rd_reg(IRQ_MULTI)
# print "multi: 0x%x" % multi
# msk = irq_regs.rd_reg(IRQ_EN_MASK)
# print "Mask: 0x%x" % msk
src = irq_regs.rd_reg(IRQ_SRC)
print "src : 0x%x" % src
print "wrote to LED %d" % src
val = led_regs.rd_reg(reg)
print "value 0x%x" % val
irq_regs.wr_reg(IRQ_SRC, src)
elif (act == "r"):
print "READ"
reg = input("reg? ")
val = led_regs.rd_reg(reg)
# print "register: 0x%1x" % reg
print "value: 0x%1x" % val
elif (act == "q"):
print "quitting"
else:
print "Wrong input!!"
if __name__ == "__main__":
main()
play/syn/led_ctrl.ucf 0 → 100644
View file @ feba6ffa
#===============================================================================
# The IO Location Constraints
#===============================================================================
#----------------------------------------
# Clock inputs
#----------------------------------------
NET "sys_clk" LOC = H12; # CLK25_VCXO
NET "sys_clk" IOSTANDARD = "LVCMOS25";
#NET "clk_125m_pllref_n_i" LOC = F10;
#NET "clk_125m_pllref_n_i" IOSTANDARD = "LVDS_25";
#NET "clk_125m_pllref_p_i" LOC = G9;
#NET "clk_125m_pllref_p_i" IOSTANDARD = "LVDS_25";
#----------------------------------------
# SFP slot
# !! SFP_TX_DISABLE and SFP_MOD_DEF1 are swapped in V1.1 schematics for control signals
#----------------------------------------
#NET "SFPRX_123_N" LOC = C15;
#NET "SFPRX_123_N" IOSTANDARD = "LVCMOS25";
#NET "SFPRX_123_P" LOC = D15;
#NET "SFPRX_123_P" IOSTANDARD = "LVCMOS25";
#NET "SFPTX_123_N" LOC = A16;
#NET "SFPTX_123_N" IOSTANDARD = "LVCMOS25";
#NET "SFPTX_123_P" LOC = B16;
#NET "SFPTX_123_P" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_FAULT" LOC = B18;
#NET "SFP_TX_FAULT" IOSTANDARD = "LVCMOS25";
#NET "SFP_TX_DISABLE" LOC = F17;
#NET "SFP_TX_DISABLE" IOSTANDARD = "LVCMOS25";
#NET "SFP_LOS" LOC = D18;
#NET "SFP_LOS" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF1" LOC = C17;
#NET "SFP_MOD_DEF1" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF0" LOC = G15;
#NET "SFP_MOD_DEF0" IOSTANDARD = "LVCMOS25";
#NET "SFP_MOD_DEF2" LOC = G16;
#NET "SFP_MOD_DEF2" IOSTANDARD = "LVCMOS25";
#NET "SFP_RATE_SELECT" LOC = H14;
#NET "SFP_RATE_SELECT" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# DAC interface (for VCXO)
#----------------------------------------
#NET "PLL25DAC1_SYNC_N" LOC = A3;
#NET "PLL25DAC1_SYNC_N" IOSTANDARD = "LVCMOS25";
#NET "PLL25DAC2_SYNC_N" LOC = B3;
#NET "PLL25DAC2_SYNC_N" IOSTANDARD = "LVCMOS25";
#NET "PLL25DAC_DIN" LOC = C4;
#NET "PLL25DAC_DIN" IOSTANDARD = "LVCMOS25";
#NET "PLL25DAC_SCLK" LOC = A4;
#NET "PLL25DAC_SCLK" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# 1-wire thermometer w/ ID
#----------------------------------------
#NET "CARRIER_ONE_WIRE_B" LOC = D4;
#NET "CARRIER_ONE_WIRE_B" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# GN4124 interface
#----------------------------------------
NET "L_RST_N" LOC = N20;
NET "L_RST_N" IOSTANDARD = "LVCMOS18";
NET "L2P_CLKN" LOC = K22;
NET "L2P_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_CLKP" LOC = K21;
NET "L2P_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "L2P_DFRAME" LOC = U22;
NET "L2P_DFRAME" IOSTANDARD = "SSTL18_I";
NET "L2P_EDB" LOC = U20;
NET "L2P_EDB" IOSTANDARD = "SSTL18_I";
NET "L2P_RDY" LOC = U19;
NET "L2P_RDY" IOSTANDARD = "SSTL18_I";
NET "L2P_VALID" LOC = T18;
NET "L2P_VALID" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[0]" LOC = R20;
NET "L_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "L_WR_RDY[1]" LOC = T22;
NET "L_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L_CLKN" LOC = N19;
NET "L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "L_CLKP" LOC = P20;
NET "L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKN" LOC = M19;
NET "P2L_CLKN" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_CLKP" LOC = M20;
NET "P2L_CLKP" IOSTANDARD = "DIFF_SSTL18_I";
NET "P2L_DFRAME" LOC = J22;
NET "P2L_DFRAME" IOSTANDARD = "SSTL18_I";
NET "P2L_RDY" LOC = J16;
NET "P2L_RDY" IOSTANDARD = "SSTL18_I";
NET "P2L_VALID" LOC = L19;
NET "P2L_VALID" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[0]" LOC = N16;
NET "P_RD_D_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_RD_D_RDY[1]" LOC = P19;
NET "P_RD_D_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[0]" LOC = L15;
NET "P_WR_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_RDY[1]" LOC = K16;
NET "P_WR_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[0]" LOC = M22;
NET "P_WR_REQ[0]" IOSTANDARD = "SSTL18_I";
NET "P_WR_REQ[1]" LOC = M21;
NET "P_WR_REQ[1]" IOSTANDARD = "SSTL18_I";
NET "RX_ERROR" LOC = J17;
NET "RX_ERROR" IOSTANDARD = "SSTL18_I";
NET "TX_ERROR" LOC = M17;
NET "TX_ERROR" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[0]" LOC = B21;
NET "VC_RDY[0]" IOSTANDARD = "SSTL18_I";
NET "VC_RDY[1]" LOC = B22;
NET "VC_RDY[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[0]" LOC = P16;
NET "L2P_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[1]" LOC = P21;
NET "L2P_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[2]" LOC = P18;
NET "L2P_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[3]" LOC = T20;
NET "L2P_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[4]" LOC = V21;
NET "L2P_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[5]" LOC = V19;
NET "L2P_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[6]" LOC = W22;
NET "L2P_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[7]" LOC = Y22;
NET "L2P_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[8]" LOC = P22;
NET "L2P_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[9]" LOC = R22;
NET "L2P_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[10]" LOC = T21;
NET "L2P_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[11]" LOC = T19;
NET "L2P_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[12]" LOC = V22;
NET "L2P_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[13]" LOC = V20;
NET "L2P_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[14]" LOC = W20;
NET "L2P_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "L2P_DATA[15]" LOC = Y21;
NET "L2P_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[0]" LOC = K20;
NET "P2L_DATA[0]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[1]" LOC = H22;
NET "P2L_DATA[1]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[2]" LOC = H21;
NET "P2L_DATA[2]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[3]" LOC = L17;
NET "P2L_DATA[3]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[4]" LOC = K17;
NET "P2L_DATA[4]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[5]" LOC = G22;
NET "P2L_DATA[5]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[6]" LOC = G20;
NET "P2L_DATA[6]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[7]" LOC = K18;
NET "P2L_DATA[7]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[8]" LOC = K19;
NET "P2L_DATA[8]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[9]" LOC = H20;
NET "P2L_DATA[9]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[10]" LOC = J19;
NET "P2L_DATA[10]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[11]" LOC = E22;
NET "P2L_DATA[11]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[12]" LOC = E20;
NET "P2L_DATA[12]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[13]" LOC = F22;
NET "P2L_DATA[13]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[14]" LOC = F21;
NET "P2L_DATA[14]" IOSTANDARD = "SSTL18_I";
NET "P2L_DATA[15]" LOC = H19;
NET "P2L_DATA[15]" IOSTANDARD = "SSTL18_I";
NET "GPIO[0]" LOC = U16;
NET "GPIO[0]" IOSTANDARD = "LVCMOS25";
NET "GPIO[1]" LOC = AB19;
NET "GPIO[1]" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot
#----------------------------------------
#NET "ext_trigger_n_i" LOC = AB13; # LA17_N
#NET "ext_trigger_n_i" IOSTANDARD = "LVDS_25";
#NET "ext_trigger_p_i" LOC = Y13; # LA17_P
#NET "ext_trigger_p_i" IOSTANDARD = "LVDS_25";
#
## dco_p and dco_n are swapped compared to the FMC ADC schematics
## this is to be coherent in the hdl design
#NET "adc_dco_n_i" LOC = AB11; # LA00_N
#NET "adc_dco_n_i" IOSTANDARD = "LVDS_25";
#NET "adc_dco_p_i" LOC = Y11; # LA00_P
#NET "adc_dco_p_i" IOSTANDARD = "LVDS_25";
#
## fr_p and fr_n are swapped compared to the FMC ADC schematics
## this is to be coherent in the hdl design
#NET "adc_fr_n_i" LOC = AB12; # LA01_N
#NET "adc_fr_n_i" IOSTANDARD = "LVDS_25";
#NET "adc_fr_p_i" LOC = AA12; # LA01_P
#NET "adc_fr_p_i" IOSTANDARD = "LVDS_25";
#
#NET "adc_outa_n_i[0]" LOC = AB4; # LA14_N
#NET "adc_outa_n_i[0]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_p_i[0]" LOC = AA4; # LA14_P
#NET "adc_outa_p_i[0]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_n_i[0]" LOC = W11; # LA15_N
#NET "adc_outb_n_i[0]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_p_i[0]" LOC = V11; # LA15_P
#NET "adc_outb_p_i[0]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_n_i[1]" LOC = Y12; # LA16_N
#NET "adc_outa_n_i[1]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_p_i[1]" LOC = W12; # LA16_P
#NET "adc_outa_p_i[1]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_n_i[1]" LOC = AB9; # LA13_N
#NET "adc_outb_n_i[1]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_p_i[1]" LOC = Y9; # LA13_P
#NET "adc_outb_p_i[1]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_n_i[2]" LOC = AB8; # LA10_N
#NET "adc_outa_n_i[2]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_p_i[2]" LOC = AA8; # LA10_P
#NET "adc_outa_p_i[2]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_n_i[2]" LOC = AB7; # LA09_N
#NET "adc_outb_n_i[2]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_p_i[2]" LOC = Y7; # LA09_P
#NET "adc_outb_p_i[2]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_n_i[3]" LOC = V9; # LA07_N
#NET "adc_outa_n_i[3]" IOSTANDARD = "LVDS_25";
#NET "adc_outa_p_i[3]" LOC = U9; # LA07_P
#NET "adc_outa_p_i[3]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_n_i[3]" LOC = AB6; # LA05_N
#NET "adc_outb_n_i[3]" IOSTANDARD = "LVDS_25";
#NET "adc_outb_p_i[3]" LOC = AA6; # LA05_P
#NET "adc_outb_p_i[3]" IOSTANDARD = "LVDS_25";
#
#NET "spi_din_i" LOC = T15; # LA25_P
#NET "spi_din_i" IOSTANDARD = "LVCMOS25";
#NET "spi_dout_o" LOC = C18; # LA31_N
#NET "spi_dout_o" IOSTANDARD = "LVCMOS25";
#NET "spi_sck_o" LOC = D17; # LA31_P
#NET "spi_sck_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_adc_n_o" LOC = V17; # LA30_P
#NET "spi_cs_adc_n_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_dac1_n_o" LOC = B20; # LA32_P
#NET "spi_cs_dac1_n_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_dac2_n_o" LOC = A20; # LA32_N
#NET "spi_cs_dac2_n_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_dac3_n_o" LOC = C19; # LA33_P
#NET "spi_cs_dac3_n_o" IOSTANDARD = "LVCMOS25";
#NET "spi_cs_dac4_n_o" LOC = A19; # LA33_N
#NET "spi_cs_dac4_n_o" IOSTANDARD = "LVCMOS25";
#
#NET "gpio_dac_clr_n_o" LOC = W18; # LA30_N
#NET "gpio_dac_clr_n_o" IOSTANDARD = "LVCMOS25";
NET "leds[0]" LOC = W15; # LA28_N
NET "leds[0]" IOSTANDARD = "LVCMOS25";
NET "leds[1]" LOC = Y16; # LA28_P
NET "leds[1]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[0]" LOC = Y17; # LA26_P
#NET "gpio_ssr_ch1_o[0]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[1]" LOC = AB17; # LA26_N
#NET "gpio_ssr_ch1_o[1]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[2]" LOC = AB18; # LA27_N
#NET "gpio_ssr_ch1_o[2]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[3]" LOC = U15; # LA25_N
#NET "gpio_ssr_ch1_o[3]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[4]" LOC = W14; # LA24_P
#NET "gpio_ssr_ch1_o[4]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[5]" LOC = Y14; # LA24_N
#NET "gpio_ssr_ch1_o[5]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch1_o[6]" LOC = W17; # LA29_P
#NET "gpio_ssr_ch1_o[6]" IOSTANDARD = "LVCMOS25";
#
#NET "gpio_ssr_ch2_o[0]" LOC = R11; # LA20_P
#NET "gpio_ssr_ch2_o[0]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[1]" LOC = AB15; # LA19_N
#NET "gpio_ssr_ch2_o[1]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[2]" LOC = R13; # LA22_P
#NET "gpio_ssr_ch2_o[2]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[3]" LOC = T14; # LA22_N
#NET "gpio_ssr_ch2_o[3]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[4]" LOC = V13; # LA21_P
#NET "gpio_ssr_ch2_o[4]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[5]" LOC = AA18; # LA27_P
#NET "gpio_ssr_ch2_o[5]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch2_o[6]" LOC = W13; # LA21_N
#NET "gpio_ssr_ch2_o[6]" IOSTANDARD = "LVCMOS25";
#
#NET "gpio_ssr_ch3_o[0]" LOC = R9; # LA08_P
#NET "gpio_ssr_ch3_o[0]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[1]" LOC = R8; # LA08_N
#NET "gpio_ssr_ch3_o[1]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[2]" LOC = T10; # LA12_P
#NET "gpio_ssr_ch3_o[2]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[3]" LOC = U10; # LA12_N
#NET "gpio_ssr_ch3_o[3]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[4]" LOC = W10; # LA11_P
#NET "gpio_ssr_ch3_o[4]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[5]" LOC = Y10; # LA11_N
#NET "gpio_ssr_ch3_o[5]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch3_o[6]" LOC = T11; # LA20_N
#NET "gpio_ssr_ch3_o[6]" IOSTANDARD = "LVCMOS25";
#
#NET "gpio_ssr_ch4_o[0]" LOC = W6; # LA02_P
#NET "gpio_ssr_ch4_o[0]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[1]" LOC = Y6; # LA02_N
#NET "gpio_ssr_ch4_o[1]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[2]" LOC = V7; # LA03_P
#NET "gpio_ssr_ch4_o[2]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[3]" LOC = W8; # LA03_N
#NET "gpio_ssr_ch4_o[3]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[4]" LOC = T8; # LA04_P
#NET "gpio_ssr_ch4_o[4]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[5]" LOC = Y5; # LA06_P
#NET "gpio_ssr_ch4_o[5]" IOSTANDARD = "LVCMOS25";
#NET "gpio_ssr_ch4_o[6]" LOC = U8; # LA04_N
#NET "gpio_ssr_ch4_o[6]" IOSTANDARD = "LVCMOS25";
#
#NET "gpio_si570_oe_o" LOC = AB5; # LA06_N
#NET "gpio_si570_oe_o" IOSTANDARD = "LVCMOS25";
#
#NET "si570_scl_b" LOC = U12; # LA18_N
#NET "si570_scl_b" IOSTANDARD = "LVCMOS25";
#NET "si570_sda_b" LOC = T12; # LA18_P
#NET "si570_sda_b" IOSTANDARD = "LVCMOS25";
#
#NET "mezz_one_wire_b" LOC = Y18; # LA29_N
#NET "mezz_one_wire_b" IOSTANDARD = "LVCMOS25";
#
#NET "prsnt_m2c_n_i" LOC = AB14; # PRSNT_M2C_L
#NET "prsnt_m2c_n_i" IOSTANDARD = "LVCMOS25";
#
#NET "sys_scl_b" LOC = F7; # SCL
#NET "sys_scl_b" IOSTANDARD = "LVCMOS25";
#NET "sys_sda_b" LOC = F8; # SDA
#NET "sys_sda_b" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# FMC slot (unused pins)
#----------------------------------------
#NET "PG_C2M" LOC = AA14;
#NET "PG_C2M" IOSTANDARD = "LVCMOS25";
#NET "LA19_P" LOC = Y15;
#NET "LA19_P" IOSTANDARD = "LVCMOS25";
#NET "LA23_N" LOC = AB16;
#NET "LA23_N" IOSTANDARD = "LVCMOS25";
#NET "LA23_P" LOC = AA16;
#NET "LA23_P" IOSTANDARD = "LVCMOS25";
#NET "TDO_FROM_FMC" LOC = F9;
#NET "TDO_FROM_FMC" IOSTANDARD = "LVCMOS25";
#NET "TCK_TO_FMC" LOC = G8;
#NET "TCK_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TDI_TO_FMC" LOC = H11;
#NET "TDI_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TMS_TO_FMC" LOC = H10;
#NET "TMS_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "TRST_TO_FMC" LOC = E6;
#NET "TRST_TO_FMC" IOSTANDARD = "LVCMOS25";
#NET "CLK0_M2C_P" LOC = E16;
#NET "CLK0_M2C_P" IOSTANDARD = "LVDS_25";
#NET "CLK0_M2C_N" LOC = F16;
#NET "CLK0_M2C_N" IOSTANDARD = "LVDS_25";
#NET "CLK1_M2C_P" LOC = L20;
#NET "CLK1_M2C_P" IOSTANDARD = "LVDS_18";
#NET "CLK1_M2C_N" LOC = L22;
#NET "CLK1_M2C_N" IOSTANDARD = "LVDS_18";
#----------------------------------------
# SI57x interface
#----------------------------------------
#NET "SI57X_SCL" LOC = A18;
#NET "SI57X_SCL" IOSTANDARD = "LVCMOS25";
#NET "SI57X_SDA" LOC = A17;
#NET "SI57X_SDA" IOSTANDARD = "LVCMOS25";
#NET "SI57X_OE" LOC = H13;
#NET "SI57X_OE" IOSTANDARD = "LVCMOS25";
#NET "SI57X_CLK_N" LOC = F15;
#NET "SI57X_CLK_N" IOSTANDARD = "LVDS_25";
#NET "SI57X_CLK_P" LOC = F14;
#NET "SI57X_CLK_P" IOSTANDARD = "LVDS_25";
#----------------------------------------
# Carrier front panel LEDs
#----------------------------------------
#NET "led_red_o" LOC = D5;
#NET "led_red_o" IOSTANDARD = "LVCMOS25";
#NET "led_green_o" LOC = E5;
#NET "led_green_o" IOSTANDARD = "LVCMOS25";
#----------------------------------------
# PCB version number (coded with resistors)
#----------------------------------------
#NET "pcb_ver_i[0]" LOC = P5;
#NET "pcb_ver_i[0]" IOSTANDARD = "LVCMOS15";
#NET "pcb_ver_i[1]" LOC = P4;
#NET "pcb_ver_i[1]" IOSTANDARD = "LVCMOS15";
#NET "pcb_ver_i[2]" LOC = AA2;
#NET "pcb_ver_i[2]" IOSTANDARD = "LVCMOS15";
#NET "pcb_ver_i[3]" LOC = AA1;
#NET "pcb_ver_i[3]" IOSTANDARD = "LVCMOS15";
#----------------------------------------
# DDR3 interface
#----------------------------------------
#NET "DDR3_CAS_N" LOC = M4;
#NET "DDR3_CAS_N" IOSTANDARD = "SSTL15_II";
#NET "DDR3_CK_N" LOC = K3;
#NET "DDR3_CK_N" IOSTANDARD = "DIFF_SSTL15_II";
#NET "DDR3_CK_P" LOC = K4;
#NET "DDR3_CK_P" IOSTANDARD = "DIFF_SSTL15_II";
#NET "DDR3_CKE" LOC = F2;
#NET "DDR3_CKE" IOSTANDARD = "SSTL15_II";
#NET "DDR3_LDM" LOC = N4;
#NET "DDR3_LDM" IOSTANDARD = "SSTL15_II";
#NET "DDR3_LDQS_N" LOC = N1;
#NET "DDR3_LDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
#NET "DDR3_LDQS_P" LOC = N3;
#NET "DDR3_LDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
#NET "DDR3_ODT" LOC = L6;
#NET "DDR3_ODT" IOSTANDARD = "SSTL15_II";
#NET "DDR3_RAS_N" LOC = M5;
#NET "DDR3_RAS_N" IOSTANDARD = "SSTL15_II";
#NET "DDR3_RESET_N" LOC = E3;
#NET "DDR3_RESET_N" IOSTANDARD = "SSTL15_II";
#NET "DDR3_UDM" LOC = P3;
#NET "DDR3_UDM" IOSTANDARD = "SSTL15_II";
#NET "DDR3_UDQS_N" LOC = V1;
#NET "DDR3_UDQS_N" IOSTANDARD = "DIFF_SSTL15_II";
#NET "DDR3_UDQS_P" LOC = V2;
#NET "DDR3_UDQS_P" IOSTANDARD = "DIFF_SSTL15_II";
#NET "DDR3_WE_N" LOC = H2;
#NET "DDR3_WE_N" IOSTANDARD = "SSTL15_II";
#NET "DDR3_RZQ" LOC = K7;
#NET "DDR3_RZQ" IOSTANDARD = "SSTL15_II";
#NET "DDR3_ZIO" LOC = M7;
#NET "DDR3_ZIO" IOSTANDARD = "SSTL15_II";
#
#NET "DDR3_A[0]" LOC = K2;
#NET "DDR3_A[0]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[1]" LOC = K1;
#NET "DDR3_A[1]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[2]" LOC = K5;
#NET "DDR3_A[2]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[3]" LOC = M6;
#NET "DDR3_A[3]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[4]" LOC = H3;
#NET "DDR3_A[4]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[5]" LOC = M3;
#NET "DDR3_A[5]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[6]" LOC = L4;
#NET "DDR3_A[6]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[7]" LOC = K6;
#NET "DDR3_A[7]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[8]" LOC = G3;
#NET "DDR3_A[8]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[9]" LOC = G1;
#NET "DDR3_A[9]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[10]" LOC = J4;
#NET "DDR3_A[10]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[11]" LOC = E1;
#NET "DDR3_A[11]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[12]" LOC = F1;
#NET "DDR3_A[12]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_A[13]" LOC = J6;
#NET "DDR3_A[13]" IOSTANDARD = "SSTL15_II";
##NET "DDR3_A[14]" LOC = H5;
##NET "DDR3_A[14]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_BA[0]" LOC = J3;
#NET "DDR3_BA[0]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_BA[1]" LOC = J1;
#NET "DDR3_BA[1]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_BA[2]" LOC = H1;
#NET "DDR3_BA[2]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[0]" LOC = R3;
#NET "DDR3_DQ[0]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[1]" LOC = R1;
#NET "DDR3_DQ[1]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[2]" LOC = P2;
#NET "DDR3_DQ[2]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[3]" LOC = P1;
#NET "DDR3_DQ[3]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[4]" LOC = L3;
#NET "DDR3_DQ[4]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[5]" LOC = L1;
#NET "DDR3_DQ[5]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[6]" LOC = M2;
#NET "DDR3_DQ[6]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[7]" LOC = M1;
#NET "DDR3_DQ[7]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[8]" LOC = T2;
#NET "DDR3_DQ[8]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[9]" LOC = T1;
#NET "DDR3_DQ[9]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[10]" LOC = U3;
#NET "DDR3_DQ[10]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[11]" LOC = U1;
#NET "DDR3_DQ[11]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[12]" LOC = W3;
#NET "DDR3_DQ[12]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[13]" LOC = W1;
#NET "DDR3_DQ[13]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[14]" LOC = Y2;
#NET "DDR3_DQ[14]" IOSTANDARD = "SSTL15_II";
#NET "DDR3_DQ[15]" LOC = Y1;
#NET "DDR3_DQ[15]" IOSTANDARD = "SSTL15_II";
#
##----------------------------------------
## UART
##----------------------------------------
##NET "UART_TXD" LOC = A2; # FPGA input
##NET "UART_TXD" IOSTANDARD = "LVCMOS25";
##NET "UART_RXD" LOC = B2; # FPGA output
##NET "UART_RXD" IOSTANDARD = "LVCMOS25";
#
##----------------------------------------
## Buttons and LEDs
##----------------------------------------
#NET "AUX_BUTTONS_I[0]" LOC = C22;
#NET "AUX_BUTTONS_I[0]" IOSTANDARD = "LVCMOS18";
#NET "AUX_BUTTONS_I[1]" LOC = D21;
#NET "AUX_BUTTONS_I[1]" IOSTANDARD = "LVCMOS18";
#NET "AUX_LEDS_O[0]" LOC = G19;
#NET "AUX_LEDS_O[0]" IOSTANDARD = "LVCMOS18";
#NET "AUX_LEDS_O[1]" LOC = F20;
#NET "AUX_LEDS_O[1]" IOSTANDARD = "LVCMOS18";
#NET "AUX_LEDS_O[2]" LOC = F18;
#NET "AUX_LEDS_O[2]" IOSTANDARD = "LVCMOS18";
#NET "AUX_LEDS_O[3]" LOC = C20;
#NET "AUX_LEDS_O[3]" IOSTANDARD = "LVCMOS18";
#===============================================================================
# IOBs
#===============================================================================
INST "cmp_gn4124_core/l2p_rdy_t" IOB=FALSE;
INST "cmp_gn4124_core/l_wr_rdy_t*" IOB=FALSE;
#INST "cmp_fmc_spi/Wrapped_SPI/shift/s_out" IOB=FALSE;
#INST "cmp_fmc_spi/Wrapped_SPI/clgen/clk_out" IOB=FALSE;
#===============================================================================
# Terminations
#===============================================================================
# DDR3
#NET "DDR3_DQ[*]" IN_TERM = NONE;
#NET "DDR3_LDQS_P" IN_TERM = NONE;
#NET "DDR3_LDQS_N" IN_TERM = NONE;
#NET "DDR3_UDQS_P" IN_TERM = NONE;
#NET "DDR3_UDQS_N" IN_TERM = NONE;
#===============================================================================
# Clock constraints
#===============================================================================
# GN4124
NET "L_CLKp" TNM_NET = "l_clkp_grp";
TIMESPEC TS_l_clkp = PERIOD "l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKp" TNM_NET = "p2l_clkp_grp";
TIMESPEC TS_p2l_clkp = PERIOD "p2l_clkp_grp" 5 ns HIGH 50%;
NET "P2L_CLKn" TNM_NET = "p2l_clkn_grp";
TIMESPEC TS_p2l_clkn = PERIOD "p2l_clkn_grp" 5 ns HIGH 50%;
# System clock
NET "sys_clk" TNM_NET = "sys_clk_grp";
TIMESPEC TS_sys_clk = PERIOD "sys_clk_grp" 50 ns HIGH 50%;
# DDR3
#NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_infrastructure_inst/sys_clk_ibufg" TNM_NET = "SYS_CLK5";
#TIMESPEC "TS_SYS_CLK5" = PERIOD "SYS_CLK5" 3.0 ns HIGH 50 %;
# ADC
#NET "adc_dco_n_i" TNM_NET = adc_dco_n_i;
#TIMESPEC TS_adc_dco_n_i = PERIOD "adc_dco_n_i" 2 ns HIGH 50%;
#===============================================================================
# False Path
#===============================================================================
# GN4124
NET "l_rst_n" TIG;
NET "cmp_gn4124_core/rst_*" TIG;
# DDR3
#NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
#NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/c3_pll_lock" TIG;
#NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/hard_done_cal" TIG;
#NET "cmp_ddr_ctrl/cmp_ddr3_ctrl_wrapper/gen_spec_bank3_64b_32b.cmp_ddr3_ctrl/memc3_wrapper_inst/memc3_mcb_raw_wrapper_inst/gen_term_calib.mcb_soft_calibration_top_inst/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
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