- 19 Jul, 2013 4 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
Serdes pll feedback is now cancelling the clock path delay. See UG382 Spartan-6 FPGA Clocking Resources page 33.
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- 17 Jul, 2013 36 commits
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Matthieu Cattin authored
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Matthieu Cattin authored
spec -> feedback through a buffer. svec -> direct feedback (without buffer).
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
The timetag core is meant to be shared between different carriers.
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Matthieu Cattin authored
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Matthieu Cattin authored
The ip_cores dir is meant to be shared between different carriers.
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
The new module contains another wb crossbar. Therefore the memory mapping has changed. This has been done for the future svec design with two fmc slots.
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
This solves the problem of trigger firing even when the data was below the threshold.
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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Matthieu Cattin authored
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