hdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a, works. Did not verify simulation results

hdl: update ddr3-sp6-core pointer so that it includes the latest Manifest.py of ddr3-sp6-core without any local variables

syn: removed (and ignored) all hdlmake-generated files from SPEC and SVEC. Xilinx ISE project files could be added on official release commits if necessary

syn: updated Manifest.py for SPEC and SVEC to work with latest hdlmake notation for git revisions (@@) and align them with current git submodules

hdl: Change ddr-sp6-core module to master branch, add custom variable to select ddr copntrollers (requires hdlmake v2.1).

The sampling frequency can't be changed dynamically in the current design.
This is due to the internal fpga pll that is configured for a fixed 400MHz input.

- Rename folders with shorter names.
- Remove documents un-related to gateware (e.g. board design).

- fixed and variable saturation blocks merged into one.
- registers added before the crossbar in the fmc-adc mezzanine component.
- acq_config_ok signal is now registered.

It was creating a big multiplexer in the wishbone crossbar and violating timing constrains.
Those reserved fields are replaced by "don't care" -> better optimised during synthesis.

- Variable data saturation.
- Optional trigger threshold detection deglitch filter.
- Internal trigger test mode.
- Sampling frequency counter.
- Remaining shot counter.
- Defined DAC (for VCXO) control outputs value.
- Check number of samples in multi-shot (shouldn't exceed ram depth).

hdl: Add spexi top hdl design (Note that it's not compliant to the latest architecture and gnum core, yet).

The new GN4124 core version implements a timeout and ERR treatment on the csr wishbone interface.