syn/svec: split timing constraints for sync_ffs and sync_reg to solve potential issue with sync_reg input bits arriving on different clock cycles

 - Remove duplicate code and introduce a "for loop" generate for the two mezzanines.
 - Complete rework of timing constraints
 - Use SVEC BSP from WR for PLLs and reset
 - Replace xwb_clock_crossing with new xwb_clock_bridge
 - Redefine front panel LED functions, eliminate "heart-beat" LED
 - Fix bug where tm_time_valid was not re-synchronised

 - switch to pipelined
 - replace xwb_register_link with new xwb_register
 - enable pipelined mode for SDB ROM

Adjust tb

See merge request dlamprid/fmc-adc-100m14b4cha-gw!1

hdl: further sanitise resets and switch the core to using synchronous resets (safer, easier to meet timing)

sim: Introduction of new, simpler testbench for FMC-ADC core, without any SPEC or SVEC specific details

hdl: fix bug where newly-arriving triggers could cause trigger delay logic to reset while counting for previous trigger