FMC ADC 100M 14b 4cha - Gateware:master commitshttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commits/master2016-04-20T15:38:58Zhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/c8295403bbb4af0dcdeb8c9a744ea07c63deb9cfsyn: synthesis files for gateware release 4.12016-04-20T15:38:58ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/a37d85ff17a01a013e48e028abfb18c066c66cb4Merge branch 'proposed_master'2016-04-20T14:51:42ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/dfb7b6bf1ed617ba8fbd7e021df4800a05e8e7cadoc: remove link to "missing features", from paragraph on WR enable of the AD...2016-04-20T07:33:26ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/e652759b059b08311ef6cde20659db3a2478cc80hdl+doc: update SDB meta info2016-04-19T10:08:54ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/ca9e387578310b36ec5c1f0499cd91a68e59e3eehdl: fixed identation and updated headers on all modified files, prior to new...2016-04-19T09:22:42ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/1f69cf8c488cf71df577122a2702cc976b51fac4doc: update all documentation in view of release 4.12016-04-18T14:48:43ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/e2180fcb58558c83830ba938fd07a3fbe1e45d91hdl+doc: replace all instances of 'decimation' with 'under-sampling', closes ...2016-04-18T14:48:21ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/e349ef452797442a61ed0d28651dea9f80a50aa2hdl: increased the sync FIFO size to cope with increased dpram size2016-04-14T15:25:17ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/d39908decf1ae0b6b3cb5cdabbafb5742e858c43hdl: increased the multishot ram size for second FMC-ADC in SVEC2016-04-14T15:24:35ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/4eaf8f2492f9aed2a6c897cf5d3dd23f2a468f18hdl: prevent FSM from going through the pre-trigger state, if there are no…2016-04-13T13:49:33ZDimitris LampridisDimitris.Lampridis@cern.chhdl: prevent FSM from going through the pre-trigger state, if there are no pre-trigger samples to be acquired. Fixes the error in the samples counter register when pre_trigger samples was zero.
https://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/f83845146c9c4d7714a6327dc9cd173e18ad1c4ahdl: reduce by 1 the max allowed number of samples in multi-shot mode.2016-04-13T13:45:46ZDimitris LampridisDimitris.Lampridis@cern.ch
Because of a -yet to be fully understood- bug, acquisition produces
corrupted samples when number_of_samples is exactly equal to multi_shot dpram
size. So for now, number_of_samples should be less than multi_shot ram size.https://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/03827e031ba762feb92a09f182758d32d5033db6hdl: allow samples to completely fill on-chip dprams2016-04-08T12:00:03ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/cf77a2a26919454c9aab0dad92391431b7fbad69hdl: dpram0 now also uses single clock for both ports2016-04-08T11:55:29ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/426788b54d97183a3329c9a45791da93e2d460eahdl/sim: sanitized and updated SVEC simulation. Tested with ModelSIM 10.2a, w...2016-04-08T09:42:29ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/2e05f2a205d605fd562a9e71a0fad7d15f119678hdl: decrease remaining shots register also in single-shot mode. Solves issue...2016-04-07T15:34:08ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/d69f1840fd825f5fdf912c12455daba6a589126aMerge branch 'dlamprid-dev' into dlamprid-mshotmem2016-04-01T15:37:43ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/bfce755891f991ba3cf374b66270215cb72555dehdl/testbench: corrected and expanded new system verilog testbench for SPEC. ...2016-04-01T15:37:16ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/cdaafa330b3cb4a6cca30972566b6d4f8f2f6ba2hdl/sim: renamed deprecated sim to sim-old2016-04-01T08:22:19ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/4da0fe722e724a04ba91da78ebbccf9dcd111fdeMerge branch 'dlamprid-dev' into dlamprid-mshotmem2016-03-31T09:12:51ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/523e8a0a1b12601cdfa8e3d6c14cb45f49101e43hdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a,…2016-03-31T09:12:37ZDimitris LampridisDimitris.Lampridis@cern.chhdl/sim: sanitized and updated SPEC simulation. Tested with ModelSIM 10.2a, works. Did not verify simulation results
https://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/2213467d3e1aec7ef6e02ae21ff86a7ceb48785ahdl: introduce extra read-only register to allow retrieval of multi-shot memo...2016-03-30T09:20:18ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/025f3f63e30e71d7f926a00463a5f424d14cd751hdl: remove hard-coded link to wbgen2 executable from makefile2016-03-30T09:19:49ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/35d6302769a57103a3d45ef95abce216a8780da0hdl: increase multi-shot memory to 8K2016-03-30T09:19:05ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/d9169fd0c358a6d79ada7f87a09602e37637dfc2testbench: minor compatibility updates to SPEC testbench2016-03-16T12:59:16ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/053b66a6c4ca4231aed6af227f584f860a6a4adahdl: update ddr3-sp6-core pointer2016-03-04T13:49:06ZDimitris LampridisDimitris.Lampridis@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/f4d0c7a47a8878ee59c2eb9f55cad12a5778887bhdl: update ddr3-sp6-core pointer so that it includes the latest Manifest.py of…2016-02-24T10:28:49ZDimitris LampridisDimitris.Lampridis@cern.chhdl: update ddr3-sp6-core pointer so that it includes the latest Manifest.py of ddr3-sp6-core without any local variables
https://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/a26af79918bfa25c22fbda57d31f1d3cf55a916csyn: removed (and ignored) all hdlmake-generated files from SPEC and SVEC.…2016-02-15T16:07:36ZDimitris LampridisDimitris.Lampridis@cern.chsyn: removed (and ignored) all hdlmake-generated files from SPEC and SVEC. Xilinx ISE project files could be added on official release commits if necessary
https://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/0d62e067bc070816cb90afa541a5d074424fe475syn: updated Manifest.py for SPEC and SVEC to work with latest hdlmake notation…2016-02-15T15:50:51ZDimitris LampridisDimitris.Lampridis@cern.chsyn: updated Manifest.py for SPEC and SVEC to work with latest hdlmake notation for git revisions (@@) and align them with current git submodules
https://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/f202b3a6b7990800127cdb2e83c5c4d217b469c8testbench for DMA2015-06-26T08:38:15ZTomasz Włostowskitomasz.wlostowski@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/5e84804ab93e9974489c771e384fc34b3e5081fahdl: Add syn_tool variable, required by hdlmake v2.12015-02-17T13:48:15ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/776745dedaa19efa764786526427f5f5d277d43chdl: Change ddr-sp6-core module to master branch, add custom variable to select…2015-02-17T13:38:14ZMatthieu Cattinmatthieu.cattin@cern.chhdl: Change ddr-sp6-core module to master branch, add custom variable to select ddr copntrollers (requires hdlmake v2.1).
https://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/e746eb6d1ca5cda8a08698c611723dd315db91eegit: update general-cores submodule.2014-08-20T15:04:17ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/d27e5a09b60d89f18f7a88f1262461f6825a09ccdoc, hdl: add note about the sampling frequency.2014-08-20T15:01:19ZMatthieu Cattinmatthieu.cattin@cern.ch
The sampling frequency can't be changed dynamically in the current design.
This is due to the internal fpga pll that is configured for a fixed 400MHz input.https://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/70a2a7553f18d5be0f6c5c841f33201f579d4fd7git: define dependencies as git submodules.2014-08-20T14:45:26ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/94c7ce240aad469c5ea7e6a821ffe4697b94da46doc: Re-organise the documentation folder.2014-05-12T09:20:19ZMatthieu Cattinmatthieu.cattin@cern.ch
- Rename folders with shorter names.
- Remove documents un-related to gateware (e.g. board design).https://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/2208f57e29e43b6274455422e34635764917363edoc: Remove todo list as it's already in the gateware manual.2014-05-07T09:20:48ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/471d64b381fe537f65402587ce639170e65b7fb5syn: svec-fmc-adc gateware release 4.02014-04-25T14:56:19ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/ad1db4c26c867d92101a1bbc838fcb64cedc3494syn: spec-fmc-adc gateware release 4.02014-04-25T14:50:51ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/5caab66fd6df7191c75bcf7d0d1e861259343d09doc: Update gateware manual and offset/gain correction drawing.2014-04-25T14:09:28ZMatthieu Cattinmatthieu.cattin@cern.chhttps://ohwr.org/project/fmc-adc-100m14b4cha-gw/commit/06ab5cf448d60292313543c30d611e385bc1f088hdl: Fix bug in saturation block, add registers to improve timing.2014-04-25T11:57:25ZMatthieu Cattinmatthieu.cattin@cern.ch
- fixed and variable saturation blocks merged into one.
- registers added before the crossbar in the fmc-adc mezzanine component.
- acq_config_ok signal is now registered.