Programming languages used in this repository

  •   Verilog
    74.76 %
  •   VHDL
    12.73 %
  •   HTML
    4.26 %
  •   SystemVerilog
    4.22 %
  •   Stata
    1.88 %
  •   C
    1.5 %
  •   Coq
    0.24 %
  •   Tcl
    0.2 %
  •   Python
    0.08 %
  •   Shell
    0.07 %
  •   Batchfile
    0.04 %
  •   Makefile
    0.03 %

Commit statistics for master Nov 23 - Apr 20

  • Total: 285 commits
  • Average per day: 0.1 commits
  • Authors: 9

Commits per day of month

Commits per weekday

Commits per day hour (UTC)