hdl: dpram0 erroneously instantiates dual clock memory
In the adc-core design, dpram0 (used in multi-shot mode) instantiates a dual port on-chip memory with two separate clocks (one per port), even though the same clock signal (sys_clk_125) is used on both ports.
dpram0 should be converted to single clock and the second clock input can be left open or driven to ground.
dpram1 is correctly instantiated as single clock.