FmcAdc100M14b4cha firmware release 2.0 Changelog: - Fix bug in pre/post_trig_done signals generation. - Update wbgen wishbone interfaces (port name change). - Change utc core name into timetag core. - Takes the adc data for trigger threshold after offset/gain correction block. - Move mezzanine related wb cores to a separate module. - Rename top level fmc slot ports to be compatible with the svec (2 fmc slots). - Change spec mapping to fit the svec mapping. - Change serdes pll feedback. - Add a software reset register to reset the mezzanine related cores. - [ddr core] Fix wishbone interface to ignore stb if cyc is '0'.