fmc-adc-100m14b4cha
Adding WR support toOverview
CERN currently provides the White Rabbit PTP Core (WRPC), an Ethernet MAC implementation capable of providing precise timing. WRPC simplifies the process of adding WR support in an FPGA design, by encapsulating all WR time-specific functionality and providing a standard MAC interface to the FPGA fabric for sending and receiving Ethernet frames.
The WRPC also includes a timing interface which provides current time to the FPGA fabric, in a form that can be easily used. It consists of a 1-PPS signal and a UTC timecode aligned to the time of WR Master.
Furthermore, the WRPC can "discipline" other clock signals via a loop-back mechanism. The FPGA provides the clock signals to the WRPC, and the WRPC generates a set of signals to control an external DAC, which in turns controls the clock source (eg. a VCXO).
Thus, within WRPC, there are multiple ways of synchronizing the instrument to WR time. One is to simply use the provided timing interface for timestamping and/or event scheduling. The other is to align the system clock(s) to the WR clock via the look-back mechanism. Depending on the instrument and its functionality, either or both methods might be applicable and/or required.
Available options for Time Synchronization
Option 1: WRPC timing interface
Option 2: System clock alignment
Option 3: Sampling clock alignment
This option has already been studied and presented in here. Those notes will be updated and integrated into this page.
SPEC-specific implementation details
SVEC-specific implementation details
Dimitris Lampridis - 11 February 2016