Commit 071abd5f authored by Matthieu Cattin's avatar Matthieu Cattin

struct: Remove files un-related to hardware (e.g. gateware).

parent f76522d8
hdl/ip_cores/ddr3-sp6-core/
hdl/ip_cores/general-cores/
hdl/ip_cores/gn4124-core/
hdl/ip_cores/vme64x-core/
hdl/ip_cores/wr-cores/
hdl/ip_cores/.lso
hdl/ip_cores/_xmsgs
hdl/*/sim/modelsim.ini
hdl/*/sim/work/
hdl/*/sim/fifo_generator_v6_1/
hdl/*/syn/_ngo/
hdl/*/syn/_xmsgs/
hdl/*/syn/par_usage_statistics.html
hdl/*/syn/run.tcl
hdl/*/syn/*.gise
hdl/*/syn/*.bgn
hdl/*/syn/*.bin
hdl/*/syn/*.bit
hdl/*/syn/*.bld
hdl/*/syn/*.cmd_log
hdl/*/syn/*.drc
hdl/*/syn/*.lso
hdl/*/syn/*.ncd
hdl/*/syn/*.ngc
hdl/*/syn/*.ngd
hdl/*/syn/*.ngr
hdl/*/syn/*.pad
hdl/*/syn/*.pcf
hdl/*/syn/*.prj
hdl/*/syn/*.ptwx
hdl/*/syn/*.stx
hdl/*/syn/*.twx
hdl/*/syn/*.unroutes
hdl/*/syn/*.ut
hdl/*/syn/*.xpi
hdl/*/syn/*.xst
hdl/*/syn/*_bitgen.xwbt
hdl/*/syn/*_guide.ncd
hdl/*/syn/*_map.map
hdl/*/syn/*_map.ncd
hdl/*/syn/*_map.ngm
hdl/*/syn/*_map.xrpt
hdl/*/syn/*_ngdbuild.xrpt
hdl/*/syn/*_pad.csv
hdl/*/syn/*_pad.txt
hdl/*/syn/*_par.xrpt
hdl/*/syn/*_summary.xml
hdl/*/syn/*_usage.xml
hdl/*/syn/*_xst.xrpt
hdl/*/syn/webtalk.log
hdl/*/syn/webtalk_pn.xml
hdl/*/syn/xlnx_auto_0_xdb/
hdl/*/syn/xst/
hdl/*/syn/iseconfig/
hdl/*/syn/*_envsettings.html
hdl/*/syn/*_fpga_editor.log
hdl/*/syn/*_summary.html
hdl/*/release/
hdl/*/chipscope/*.vcd
hdl/*/chipscope/*.wlf
hdl/svec/sim/testbench/fifo_generator_v6_1/
hdl/svec/sim/testbench/modelsim.ini
hdl/svec/sim/testbench/simdrv_defs.svh
hdl/svec/sim/testbench/transcript
hdl/svec/sim/testbench/vsim.wlf
hdl/svec/sim/testbench/vsim_stacktrace.vstf
hdl/svec/sim/testbench/work/
documentation/manuals/*/*.html
*.texi
*.aux
*.log
......
# Makefile for Latex work
TEXFILE = adc100m14b4cha.tex
DIAGRAM = block_diagram.dia
S_MACHINE = state_machine.dia
.PHONY: clean view
$(TEXFILE:.tex=.pdf): $(TEXFILE) $(DIAGRAM:.dia=.pdf) $(S_MACHINE:.dia=.pdf)
pdflatex $(TEXFILE)
# Not very nice hack to get references right
pdflatex $(TEXFILE)
$(DIAGRAM:.dia=.pdf): $(DIAGRAM:.dia=.eps)
epstopdf $(DIAGRAM:.dia=.eps)
$(DIAGRAM:.dia=.eps): $(DIAGRAM)
dia -e $(DIAGRAM:.dia=.eps) $(DIAGRAM)
$(S_MACHINE:.dia=.pdf): $(S_MACHINE:.dia=.eps)
epstopdf $(S_MACHINE:.dia=.eps)
$(S_MACHINE:.dia=.eps): $(S_MACHINE)
dia -e $(S_MACHINE:.dia=.eps) $(S_MACHINE)
view: $(TEXFILE:.tex=.pdf)
evince $(TEXFILE:.tex=.pdf)
clean:
@rm -f \
$(TEXFILE:.tex=.aux) \
$(TEXFILE:.tex=.log) \
$(TEXFILE:.tex=.out) \
$(TEXFILE:.tex=.toc) \
$(TEXFILE:.tex=.pdf) \
$(DIAGRAM:.dia=.pdf) \
$(DIAGRAM:.dia=.eps) \
$(S_MACHINE:.dia=.pdf) \
$(S_MACHINE:.dia=.eps)
\ No newline at end of file
This diff is collapsed.
Trigger:
- Hardware external rising edge
- Hardware external falling edge
- Hardware internal positive slope
- Hardware internal negative slope
- Hardware internal positive slope, threshold range
- Hardware internal negative slope, threshold range
- Hardware internal on channel 1
- Hardware internal on channel 2
- Hardware internal on channel 3
- Hardware internal on channel 4
- Hardware enable
- Software
- Software enable
- Delay range
- Trigger alignment when decimation factor is > 1
Datapath:
- ADC offset correction
- ADC gain correction
- Decimation range
- Pre-trigger samples range
- Post-trigger samples range
- Total number of samples range (full memory, overlapping, etc...)
- Number of shots range
- Multi-shot mode, memory arrangement
- Multi-shot mode, number of samples range (up to max dpram size)
-
ADC core CSR:
* Acq and trig LEDs manual control bits => tested with production test03
- Test data (Write the address counter value instead of ADC data to DDR)
! Manual bitslip of adc data serdes => Cannot be tested as automatic bitslip is generated in hdl
- Offset DAC clear
- FMC clock enable
- FSM start command
- FSM stop command
- FSM unused commands (shouldn't do anything)
! FSM state => cannot test all states (e.g. DECR_SHOT lasts only 1 tick)
- SerDes PLL lock status (use FMC clock enable)
! SerDes sync status, must be 1 => cannot test more
* Trigger config, delay and software trigger registers => see Trigger chapter
* Number of shots => see Datapath chapter
* Trigger position => see Datapath chapter
* Decimation rate => see Datapath chapter
* Pre-trigger samples => see Datapath chapter
* Post-trigger samples => see Datapath chapter
- Samples counter
* Channel N control register (switches) => tested with production test08
- Channel N value register (use pattern from ADC)
* Channel N correction gain and offset registers => see Datapath chapter
-
Interrupts:
- Interrupt mask
- DMA done interrupt
? DMA error interrupt => how to force a DMA error
- Trigger interrupt
- End of acquisition interrupt
- Multi-interrupt
Time-tags:
- UTC set register
- Coarse set register
- Trigger tag
- Acquisition start tag
- Acquisition stop tag
- Acquisition end tag
Carrier CSR:
* Carrier type => tested in fmc_adc_spec access class
? Carrier PCB revision => how to automate this test?
! FMC mezzanine presence => cannot automated this test
! P2L PLL lock status, must be 1 => cannot test more
! SysClk PLL lock status, must be 1 => cannot test more
! DDR calibration done status, must be 1 => cannot test more
! SPEC LEDs => cannot automated this test
=> carrier specific firmaware parts will be hard to test...
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment