Commit a37a5c69 authored by serrano's avatar serrano

Clarified 32-bit read and write contraint only applies to control and status registers, not to DMA.


git-svn-id: http://svn.ohwr.org/fmc-adc-100m14b4cha/trunk@22 ddd67a1a-c8ad-4635-afe9-0b8a11d8f8e4
parent 4ef7220d
...@@ -83,7 +83,7 @@ The proposed internal structure of the FPGA design can be seen in figure~\ref{fi ...@@ -83,7 +83,7 @@ The proposed internal structure of the FPGA design can be seen in figure~\ref{fi
\end{figure} \end{figure}
\section{FPGA blocks} \section{FPGA blocks}
For each internal block, we give a summary description of its function along with internal registers which can be read of written from the Wishbone master. Registers are presented in tables with their name, address offset (in 32-bit long words), access mode, value after reset and description. The address offset is the offset of a given register with respect to the beginning of the memory area pointed to by a given PCIe Base Address Register (BAR). This design only supports full 32-bit reads and writes. Even if some of the registers described below use different bits for different things, that does not mean they can be written to independently from the rest of the word, so care should be taken in each write to affect all bits in an appropriate way. In general, unused bits should be ignored on read and written to with a '0'. For status registers, bits read as '0' represent a normal state of affairs, while those set to '1' signal some departure from nominal operation. For each internal block, we give a summary description of its function along with internal registers which can be read of written from the Wishbone master. Registers are presented in tables with their name, address offset (in 32-bit long words), access mode, value after reset and description. The address offset is the offset of a given register with respect to the beginning of the memory area pointed to by a given PCIe Base Address Register (BAR). This design only supports full 32-bit reads and writes for control and status registers. Even if some of the registers described below use different bits for different things, that does not mean they can be written to independently from the rest of the word, so care should be taken in each write to affect all bits in an appropriate way. In general, unused bits should be ignored on read and written to with a '0'. For status registers, bits read as '0' represent a normal state of affairs, while those set to '1' signal some departure from nominal operation.
\subsection{GN4124 to Wishbone bridge} \subsection{GN4124 to Wishbone bridge}
\label{ssec:GN4124_WB} \label{ssec:GN4124_WB}
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