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FMC ADC 100M 14b 4cha - Software
Commit 0a286a2b authored by Alessandro Rubini's avatar Alessandro Rubini
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trivial: kernel: move regtable to a different file 

Signed-off-by: Alessandro Rubini's avatarAlessandro Rubini <rubini@gnudd.com>
parent c93a98a9
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Showing with 114 additions and 105 deletions
kernel/Makefile
View file @ 0a286a2b
......@@ -23,7 +23,8 @@ fmc-adc-objs += fa-zio-trg.o
fmc-adc-objs += fa-dma.o
fmc-adc-objs += onewire.o
fmc-adc-objs += spi.o
fmc-adc-objs += fa-regtable.o
all modules:
$(MAKE) -C $(LINUX) M=$(shell /bin/pwd) modules
......
kernel/fa-regtable.c 0 → 100644
View file @ 0a286a2b
/*
* Copyright CERN 2012
* Author: Federico Vaga <federico.vaga@gmail.com>
*
* Table of register masks, used by driver functions
*/
#include "fmc-adc.h"
/* Definition of the fmc-adc registers address - mask - mask offset */
const struct zio_field_desc zfad_regs[] = {
/* Control registers */
[ZFA_CTL_FMS_CMD] = {FA_ADC_MEM_OFF + 0x00, 0x0003, 0},
[ZFA_CTL_CLK_EN] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 2},
[ZFA_CTL_DAC_CLR_N] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 3},
[ZFA_CTL_BSLIP] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 4},
[ZFA_CTL_TEST_DATA_EN] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 5},
[ZFA_CTL_TRIG_LED] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 6},
[ZFA_CTL_ACQ_LED] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 7},
/* Status registers */
[ZFA_STA_FSM] = {FA_ADC_MEM_OFF + 0x04, 0x0007, 0},
[ZFA_STA_SERDES_PLL] = {FA_ADC_MEM_OFF + 0x04, 0x0001, 3},
[ZFA_STA_SERDES_SYNCED] = {FA_ADC_MEM_OFF + 0x04, 0x0001, 4},
/* Trigger */
/* Config register */
[ZFAT_CFG_HW_SEL] = {FA_ADC_MEM_OFF + 0x08, 0x00000001, 0},
[ZFAT_CFG_HW_POL] = {FA_ADC_MEM_OFF + 0x08, 0x00000001, 1},
[ZFAT_CFG_HW_EN] = {FA_ADC_MEM_OFF + 0x08, 0x00000001, 2},
[ZFAT_CFG_SW_EN] = {FA_ADC_MEM_OFF + 0x08, 0x00000001, 3},
[ZFAT_CFG_INT_SEL] = {FA_ADC_MEM_OFF + 0x08, 0x00000003, 4},
[ZFAT_CFG_THRES] = {FA_ADC_MEM_OFF + 0x08, 0x0000FFFF, 16},
/* Delay */
[ZFAT_DLY] = {FA_ADC_MEM_OFF + 0x0C, 0xFFFFFFFF, 0},
/* Software */
[ZFAT_SW] = {FA_ADC_MEM_OFF + 0x10, 0xFFFFFFFF, 0},
/* Number of shots */
[ZFAT_SHOTS_NB] = {FA_ADC_MEM_OFF + 0x14, 0x0000FFFF, 0},
/* Sample rate */
[ZFAT_SR_DECI] = {FA_ADC_MEM_OFF + 0x1C, 0xFFFF, 0},
/* Position address */
[ZFAT_POS] = {FA_ADC_MEM_OFF + 0x18, 0xFFFFFFFF, 0},
/* Pre-sample */
[ZFAT_PRE] = {FA_ADC_MEM_OFF + 0x20, 0xFFFFFFFF, 0},
/* Post-sample */
[ZFAT_POST] = {FA_ADC_MEM_OFF + 0x24, 0xFFFFFFFF, 0},
/* Sample counter */
[ZFAT_CNT] = {FA_ADC_MEM_OFF + 0x28, 0xFFFFFFFF, 0},
/* Channel 1 */
[ZFA_CH1_CTL_RANGE] = {FA_ADC_MEM_OFF + 0x2C, 0x0077, 0},
[ZFA_CH1_STA] = {FA_ADC_MEM_OFF + 0x30, 0xFFFF, 0},
[ZFA_CH1_GAIN] = {FA_ADC_MEM_OFF + 0x34, 0xFFFF, 0},
[ZFA_CH1_OFFSET] = {FA_ADC_MEM_OFF + 0x38, 0xFFFF, 0},
[ZFA_CH1_CTL_TERM] = {FA_ADC_MEM_OFF + 0x2C, 0x0001, 3},
/* Channel 2 */
[ZFA_CH2_CTL_RANGE] = {FA_ADC_MEM_OFF + 0x3C, 0x0077, 0},
[ZFA_CH2_STA] = {FA_ADC_MEM_OFF + 0x40, 0xFFFF, 0},
[ZFA_CH2_GAIN] = {FA_ADC_MEM_OFF + 0x44, 0xFFFF, 0},
[ZFA_CH2_OFFSET] = {FA_ADC_MEM_OFF + 0x48, 0xFFFF, 0},
[ZFA_CH2_CTL_TERM] = {FA_ADC_MEM_OFF + 0x3C, 0x0001, 3},
/* Channel 3 */
[ZFA_CH3_CTL_RANGE] = {FA_ADC_MEM_OFF + 0x4C, 0x0077, 0},
[ZFA_CH3_STA] = {FA_ADC_MEM_OFF + 0x50, 0xFFFF, 0},
[ZFA_CH3_GAIN] = {FA_ADC_MEM_OFF + 0x54, 0xFFFF, 0},
[ZFA_CH3_OFFSET] = {FA_ADC_MEM_OFF + 0x58, 0xFFFF, 0},
[ZFA_CH3_CTL_TERM] = {FA_ADC_MEM_OFF + 0x4C, 0x0001, 3},
/* Channel 4 */
[ZFA_CH4_CTL_RANGE] = {FA_ADC_MEM_OFF + 0x5C, 0x0077, 0},
[ZFA_CH4_STA] = {FA_ADC_MEM_OFF + 0x60, 0xFFFF, 0},
[ZFA_CH4_GAIN] = {FA_ADC_MEM_OFF + 0x64, 0xFFFF, 0},
[ZFA_CH4_OFFSET] = {FA_ADC_MEM_OFF + 0x68, 0xFFFF, 0},
[ZFA_CH4_CTL_TERM] = {FA_ADC_MEM_OFF + 0x5C, 0x0001, 3},
/* DMA */
[ZFA_DMA_CTL_SWP] = {FA_DMA_MEM_OFF + 0x00, 0x0003, 2},
[ZFA_DMA_CTL_ABORT] = {FA_DMA_MEM_OFF + 0x00, 0x0001, 1},
[ZFA_DMA_CTL_START] = {FA_DMA_MEM_OFF + 0x00, 0x0001, 0},
[ZFA_DMA_STA] = {FA_DMA_MEM_OFF + 0x04, 0x0007, 0},
[ZFA_DMA_ADDR] = {FA_DMA_MEM_OFF + 0x08, 0xFFFFFFFF, 0},
[ZFA_DMA_ADDR_L] = {FA_DMA_MEM_OFF + 0x0C, 0xFFFFFFFF, 0},
[ZFA_DMA_ADDR_H] = {FA_DMA_MEM_OFF + 0x10, 0xFFFFFFFF, 0},
[ZFA_DMA_LEN] = {FA_DMA_MEM_OFF + 0x14, 0xFFFFFFFF, 0},
[ZFA_DMA_NEXT_L] = {FA_DMA_MEM_OFF + 0x18, 0xFFFFFFFF, 0},
[ZFA_DMA_NEXT_H] = {FA_DMA_MEM_OFF + 0x1C, 0xFFFFFFFF, 0},
[ZFA_DMA_BR_DIR] = {FA_DMA_MEM_OFF + 0x20, 0x0001, 1},
[ZFA_DMA_BR_LAST] = {FA_DMA_MEM_OFF + 0x20, 0x0001, 0},
/* IRQ */
[ZFA_IRQ_MULTI] = {FA_IRQ_MEM_OFF + 0x00, 0x000F, 0},
[ZFA_IRQ_SRC] = {FA_IRQ_MEM_OFF + 0x04, 0x000F, 0},
[ZFA_IRQ_MASK] = {FA_IRQ_MEM_OFF + 0x08, 0x000F, 0},
/* UTC */
[ZFA_UTC_SECONDS] = {FA_UTC_MEM_OFF + 0x00, ~0x0, 0},
[ZFA_UTC_COARSE] = {FA_UTC_MEM_OFF + 0x04, ~0x0, 0},
[ZFA_UTC_TRIG_META] = {FA_UTC_MEM_OFF + 0x08, ~0x0, 0},
[ZFA_UTC_TRIG_SECONDS] = {FA_UTC_MEM_OFF + 0x0C, ~0x0, 0},
[ZFA_UTC_TRIG_COARSE] = {FA_UTC_MEM_OFF + 0x10, ~0x0, 0},
[ZFA_UTC_TRIG_FINE] = {FA_UTC_MEM_OFF + 0x14, ~0x0, 0},
[ZFA_UTC_ACQ_START_META] {FA_UTC_MEM_OFF + 0x18, ~0x0, 0},
[ZFA_UTC_ACQ_START_SECONDS] = {FA_UTC_MEM_OFF + 0x1C, ~0x0, 0},
[ZFA_UTC_ACQ_START_COARSE] = {FA_UTC_MEM_OFF + 0x20, ~0x0, 0},
[ZFA_UTC_ACQ_START_FINE] = {FA_UTC_MEM_OFF + 0x24, ~0x0, 0},
[ZFA_UTC_ACQ_STOP_META] = {FA_UTC_MEM_OFF + 0x28, ~0x0, 0},
[ZFA_UTC_ACQ_STOP_SECONDS] = {FA_UTC_MEM_OFF + 0x2C, ~0x0, 0},
[ZFA_UTC_ACQ_STOP_COARSE] = {FA_UTC_MEM_OFF + 0x30, ~0x0, 0},
[ZFA_UTC_ACQ_STOP_FINE] = {FA_UTC_MEM_OFF + 0x34, ~0x0, 0},
[ZFA_UTC_ACQ_END_META] = {FA_UTC_MEM_OFF + 0x38, ~0x0, 0},
[ZFA_UTC_ACQ_END_SECONDS] = {FA_UTC_MEM_OFF + 0x3C, ~0x0, 0},
[ZFA_UTC_ACQ_END_COARSE] = {FA_UTC_MEM_OFF + 0x40, ~0x0, 0},
[ZFA_UTC_ACQ_END_FINE] = {FA_UTC_MEM_OFF + 0x44, ~0x0, 0},
/* Carrier CSR */
[ZFA_CAR_FMC_PRES] = {FA_CAR_MEM_OFF + 0x04, 0x1, 0},
[ZFA_CAR_P2L_PLL] = {FA_CAR_MEM_OFF + 0x04, 0x1, 1},
[ZFA_CAR_SYS_PLL] = {FA_CAR_MEM_OFF + 0x04, 0x1, 2},
[ZFA_CAR_DDR_CAL] = {FA_CAR_MEM_OFF + 0x04, 0x1, 3},
};
kernel/fa-zio-drv.c
View file @ 0a286a2b
......@@ -29,110 +29,6 @@ static int enable_test_data = 0;
module_param(enable_test_data, int, 0444);
/* Definition of the fmc-adc registers address - mask - mask offset */
const struct zio_field_desc zfad_regs[] = {
/* Control registers */
[ZFA_CTL_FMS_CMD] = {FA_ADC_MEM_OFF + 0x00, 0x0003, 0},
[ZFA_CTL_CLK_EN] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 2},
[ZFA_CTL_DAC_CLR_N] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 3},
[ZFA_CTL_BSLIP] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 4},
[ZFA_CTL_TEST_DATA_EN] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 5},
[ZFA_CTL_TRIG_LED] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 6},
[ZFA_CTL_ACQ_LED] = {FA_ADC_MEM_OFF + 0x00, 0x0001, 7},
/* Status registers */
[ZFA_STA_FSM] = {FA_ADC_MEM_OFF + 0x04, 0x0007, 0},
[ZFA_STA_SERDES_PLL] = {FA_ADC_MEM_OFF + 0x04, 0x0001, 3},
[ZFA_STA_SERDES_SYNCED] = {FA_ADC_MEM_OFF + 0x04, 0x0001, 4},
/* Trigger */
/* Config register */
[ZFAT_CFG_HW_SEL] = {FA_ADC_MEM_OFF + 0x08, 0x00000001, 0},
[ZFAT_CFG_HW_POL] = {FA_ADC_MEM_OFF + 0x08, 0x00000001, 1},
[ZFAT_CFG_HW_EN] = {FA_ADC_MEM_OFF + 0x08, 0x00000001, 2},
[ZFAT_CFG_SW_EN] = {FA_ADC_MEM_OFF + 0x08, 0x00000001, 3},
[ZFAT_CFG_INT_SEL] = {FA_ADC_MEM_OFF + 0x08, 0x00000003, 4},
[ZFAT_CFG_THRES] = {FA_ADC_MEM_OFF + 0x08, 0x0000FFFF, 16},
/* Delay */
[ZFAT_DLY] = {FA_ADC_MEM_OFF + 0x0C, 0xFFFFFFFF, 0},
/* Software */
[ZFAT_SW] = {FA_ADC_MEM_OFF + 0x10, 0xFFFFFFFF, 0},
/* Number of shots */
[ZFAT_SHOTS_NB] = {FA_ADC_MEM_OFF + 0x14, 0x0000FFFF, 0},
/* Sample rate */
[ZFAT_SR_DECI] = {FA_ADC_MEM_OFF + 0x1C, 0xFFFF, 0},
/* Position address */
[ZFAT_POS] = {FA_ADC_MEM_OFF + 0x18, 0xFFFFFFFF, 0},
/* Pre-sample */
[ZFAT_PRE] = {FA_ADC_MEM_OFF + 0x20, 0xFFFFFFFF, 0},
/* Post-sample */
[ZFAT_POST] = {FA_ADC_MEM_OFF + 0x24, 0xFFFFFFFF, 0},
/* Sample counter */
[ZFAT_CNT] = {FA_ADC_MEM_OFF + 0x28, 0xFFFFFFFF, 0},
/* Channel 1 */
[ZFA_CH1_CTL_RANGE] = {FA_ADC_MEM_OFF + 0x2C, 0x0077, 0},
[ZFA_CH1_STA] = {FA_ADC_MEM_OFF + 0x30, 0xFFFF, 0},
[ZFA_CH1_GAIN] = {FA_ADC_MEM_OFF + 0x34, 0xFFFF, 0},
[ZFA_CH1_OFFSET] = {FA_ADC_MEM_OFF + 0x38, 0xFFFF, 0},
[ZFA_CH1_CTL_TERM] = {FA_ADC_MEM_OFF + 0x2C, 0x0001, 3},
/* Channel 2 */
[ZFA_CH2_CTL_RANGE] = {FA_ADC_MEM_OFF + 0x3C, 0x0077, 0},
[ZFA_CH2_STA] = {FA_ADC_MEM_OFF + 0x40, 0xFFFF, 0},
[ZFA_CH2_GAIN] = {FA_ADC_MEM_OFF + 0x44, 0xFFFF, 0},
[ZFA_CH2_OFFSET] = {FA_ADC_MEM_OFF + 0x48, 0xFFFF, 0},
[ZFA_CH2_CTL_TERM] = {FA_ADC_MEM_OFF + 0x3C, 0x0001, 3},
/* Channel 3 */
[ZFA_CH3_CTL_RANGE] = {FA_ADC_MEM_OFF + 0x4C, 0x0077, 0},
[ZFA_CH3_STA] = {FA_ADC_MEM_OFF + 0x50, 0xFFFF, 0},
[ZFA_CH3_GAIN] = {FA_ADC_MEM_OFF + 0x54, 0xFFFF, 0},
[ZFA_CH3_OFFSET] = {FA_ADC_MEM_OFF + 0x58, 0xFFFF, 0},
[ZFA_CH3_CTL_TERM] = {FA_ADC_MEM_OFF + 0x4C, 0x0001, 3},
/* Channel 4 */
[ZFA_CH4_CTL_RANGE] = {FA_ADC_MEM_OFF + 0x5C, 0x0077, 0},
[ZFA_CH4_STA] = {FA_ADC_MEM_OFF + 0x60, 0xFFFF, 0},
[ZFA_CH4_GAIN] = {FA_ADC_MEM_OFF + 0x64, 0xFFFF, 0},
[ZFA_CH4_OFFSET] = {FA_ADC_MEM_OFF + 0x68, 0xFFFF, 0},
[ZFA_CH4_CTL_TERM] = {FA_ADC_MEM_OFF + 0x5C, 0x0001, 3},
/* DMA */
[ZFA_DMA_CTL_SWP] = {FA_DMA_MEM_OFF + 0x00, 0x0003, 2},
[ZFA_DMA_CTL_ABORT] = {FA_DMA_MEM_OFF + 0x00, 0x0001, 1},
[ZFA_DMA_CTL_START] = {FA_DMA_MEM_OFF + 0x00, 0x0001, 0},
[ZFA_DMA_STA] = {FA_DMA_MEM_OFF + 0x04, 0x0007, 0},
[ZFA_DMA_ADDR] = {FA_DMA_MEM_OFF + 0x08, 0xFFFFFFFF, 0},
[ZFA_DMA_ADDR_L] = {FA_DMA_MEM_OFF + 0x0C, 0xFFFFFFFF, 0},
[ZFA_DMA_ADDR_H] = {FA_DMA_MEM_OFF + 0x10, 0xFFFFFFFF, 0},
[ZFA_DMA_LEN] = {FA_DMA_MEM_OFF + 0x14, 0xFFFFFFFF, 0},
[ZFA_DMA_NEXT_L] = {FA_DMA_MEM_OFF + 0x18, 0xFFFFFFFF, 0},
[ZFA_DMA_NEXT_H] = {FA_DMA_MEM_OFF + 0x1C, 0xFFFFFFFF, 0},
[ZFA_DMA_BR_DIR] = {FA_DMA_MEM_OFF + 0x20, 0x0001, 1},
[ZFA_DMA_BR_LAST] = {FA_DMA_MEM_OFF + 0x20, 0x0001, 0},
/* IRQ */
[ZFA_IRQ_MULTI] = {FA_IRQ_MEM_OFF + 0x00, 0x000F, 0},
[ZFA_IRQ_SRC] = {FA_IRQ_MEM_OFF + 0x04, 0x000F, 0},
[ZFA_IRQ_MASK] = {FA_IRQ_MEM_OFF + 0x08, 0x000F, 0},
/* UTC */
[ZFA_UTC_SECONDS] = {FA_UTC_MEM_OFF + 0x00, ~0x0, 0},
[ZFA_UTC_COARSE] = {FA_UTC_MEM_OFF + 0x04, ~0x0, 0},
[ZFA_UTC_TRIG_META] = {FA_UTC_MEM_OFF + 0x08, ~0x0, 0},
[ZFA_UTC_TRIG_SECONDS] = {FA_UTC_MEM_OFF + 0x0C, ~0x0, 0},
[ZFA_UTC_TRIG_COARSE] = {FA_UTC_MEM_OFF + 0x10, ~0x0, 0},
[ZFA_UTC_TRIG_FINE] = {FA_UTC_MEM_OFF + 0x14, ~0x0, 0},
[ZFA_UTC_ACQ_START_META] {FA_UTC_MEM_OFF + 0x18, ~0x0, 0},
[ZFA_UTC_ACQ_START_SECONDS] = {FA_UTC_MEM_OFF + 0x1C, ~0x0, 0},
[ZFA_UTC_ACQ_START_COARSE] = {FA_UTC_MEM_OFF + 0x20, ~0x0, 0},
[ZFA_UTC_ACQ_START_FINE] = {FA_UTC_MEM_OFF + 0x24, ~0x0, 0},
[ZFA_UTC_ACQ_STOP_META] = {FA_UTC_MEM_OFF + 0x28, ~0x0, 0},
[ZFA_UTC_ACQ_STOP_SECONDS] = {FA_UTC_MEM_OFF + 0x2C, ~0x0, 0},
[ZFA_UTC_ACQ_STOP_COARSE] = {FA_UTC_MEM_OFF + 0x30, ~0x0, 0},
[ZFA_UTC_ACQ_STOP_FINE] = {FA_UTC_MEM_OFF + 0x34, ~0x0, 0},
[ZFA_UTC_ACQ_END_META] = {FA_UTC_MEM_OFF + 0x38, ~0x0, 0},
[ZFA_UTC_ACQ_END_SECONDS] = {FA_UTC_MEM_OFF + 0x3C, ~0x0, 0},
[ZFA_UTC_ACQ_END_COARSE] = {FA_UTC_MEM_OFF + 0x40, ~0x0, 0},
[ZFA_UTC_ACQ_END_FINE] = {FA_UTC_MEM_OFF + 0x44, ~0x0, 0},
/* Carrier CSR */
[ZFA_CAR_FMC_PRES] = {FA_CAR_MEM_OFF + 0x04, 0x1, 0},
[ZFA_CAR_P2L_PLL] = {FA_CAR_MEM_OFF + 0x04, 0x1, 1},
[ZFA_CAR_SYS_PLL] = {FA_CAR_MEM_OFF + 0x04, 0x1, 2},
[ZFA_CAR_DDR_CAL] = {FA_CAR_MEM_OFF + 0x04, 0x1, 3},
};
/* zio device attributes */
static ZIO_ATTR_DEFINE_STD(ZIO_DEV, zfad_cset_std_zattr) = {
......
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