Commit 32ef6bfc authored by Federico Vaga's avatar Federico Vaga

kernel: do a proper reset of the FMC mezzanine

In gateware version 5 the logic of the FMC reset bit change from active low
to active high: "reset: {1: reset, 0 unreset}".

Here with this patch we do a complete reset cycle of the FMC mezzanine.
The sleeping time between reset and unreset is huge but we do not care much,
this is just the initialization.
Signed-off-by: Federico Vaga's avatarFederico Vaga <federico.vaga@cern.ch>
parent 2a258a4d
......@@ -42,12 +42,13 @@ static int fa_spec_init(struct fa_dev *fa)
cdata->fa_irq_dma_base, cdata->fa_dma_base,
fa->fa_carrier_csr_base);
/* Wait 50ms, so device has time to calibrate */
/* Reset the FMC slot */
fa_writel(fa, fa->fa_carrier_csr_base,
&fa_spec_regs[ZFA_CAR_FMC_RES], 1);
mdelay(50);
/* set FMC0 in normal FMC operation */
fa_writel(fa, fa->fa_carrier_csr_base,
&fa_spec_regs[ZFA_CAR_FMC_RES], 1);
&fa_spec_regs[ZFA_CAR_FMC_RES], 0);
mdelay(50);
/* Verify that the FMC is plugged (0 is plugged) */
val = fa_readl(fa, fa->fa_carrier_csr_base,
......
......@@ -41,14 +41,13 @@ static int fa_svec_init(struct fa_dev *fa)
0x10006610,
fmc->slot_id, NULL);
if (fmc->slot_id == 0)
/* set FMC0 in normal FMC operation */
fa_writel(fa, fa->fa_carrier_csr_base,
&fa_svec_regfield[FA_CAR_FMC0_RES], 1);
else if (fmc->slot_id == 1)
/* set FMC1 in normal FMC operation */
fa_writel(fa, fa->fa_carrier_csr_base,
&fa_svec_regfield[FA_CAR_FMC1_RES], 1);
/* Reset the FMC slot*/
fa_writel(fa, fa->fa_carrier_csr_base,
&fa_svec_regfield[FA_CAR_FMC0_RES + fmc->slot_id], 1);
mdelay(50);
fa_writel(fa, fa->fa_carrier_csr_base,
&fa_svec_regfield[FA_CAR_FMC0_RES + fmc->slot_id], 0);
mdelay(50);
/* register carrier data */
fa->carrier_data = cdata;
......
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